TWI730109B - 晶片封裝結構及其形成方法 - Google Patents

晶片封裝結構及其形成方法 Download PDF

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TWI730109B
TWI730109B TW106118236A TW106118236A TWI730109B TW I730109 B TWI730109 B TW I730109B TW 106118236 A TW106118236 A TW 106118236A TW 106118236 A TW106118236 A TW 106118236A TW I730109 B TWI730109 B TW I730109B
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Taiwan
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chip
shielding film
conductive shielding
ground wire
chip package
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TW106118236A
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TW201820573A (zh
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林俊成
蔡柏豪
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台灣積體電路製造股份有限公司
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Abstract

提供晶片封裝結構，晶片封裝結構包含重佈線結構，重佈線結構包含介電結構和在介電結構中的接地線，接地線包含主要部分和連接至主要部分且從介電結構橫向露出的末端擴大部分。晶片封裝結構包含晶片結構位於重佈線結構上方。晶片封裝結構包含導電屏蔽膜設置於晶片結構和末端擴大部分的第一側壁上方，導電屏蔽膜電性連接至接地線，末端擴大部分的厚度從主要部分增加至導電屏蔽膜。

Description

晶片封裝結構及其形成方法
本發明實施例係有關於半導體技術，且特別是有關於半導體晶片封裝結構。
半導體積體電路(integrated circuit，IC)工業已經歷了快速成長。在積體電路材料和設計上的技術進步產生了數代積體電路，每一代都比前一代具有更小且更複雜的電路。然而，這些進步增加了加工與製造積體電路的複雜性。
在積體電路的發展史中，功能密度(即每一晶片區互連的裝置數目)增加，同時幾何尺寸(即製造過程中所產生的最小的組件(或線路))縮小。此元件尺寸微縮化的製程一般來說具有增加生產效率與降低相關費用的益處。
然而，由於部件(feature)尺寸持續縮減，製造製程持續變的更加難以實施，且半導體裝置的效能容易受到影響。舉例來說，電磁干擾(electromagnetic interference，EMI)對於大多數的半導體裝置是個挑戰。電磁干擾可干擾、降低或限制半導體裝置的效能。
在一些實施例中，提供晶片封裝結構，此晶片封 裝結構包含重佈線結構，重佈線結構包含介電結構和在介電結構中的接地線，其中接地線包含主要部分和連接至主要部分且從介電結構橫向露出的末端擴大部分；晶片結構位於重佈線結構上方；以及導電屏蔽膜設置於晶片結構和末端擴大部分的第一側壁上方，其中導電屏蔽膜電性連接至接地線，且其中末端擴大部分的厚度從主要部分增加至導電屏蔽膜。
在一些其他實施例中，提供晶片封裝結構，此晶片封裝結構包含重佈線結構，重佈線結構包含介電結構和在介電結構中的接地線，其中接地線包含主要部分和連接至主要部分且從介電結構橫向露出的末端擴大部分，其中末端擴大部分的最大厚度大於主要部分的最大厚度，其中末端擴大部分定義第一側壁，且其中介電結構不覆蓋第一側壁的至少一部份；晶片結構位於重佈線結構上方；以及導電屏蔽膜設置於晶片結構上方並透過末端擴大部分電性連接至接地線。
在另外一些實施例中，提供晶片封裝結構的形成方法，此方法包含提供第一晶片結構、第二晶片結構和圍繞第一晶片結構和第二晶片結構的模塑化合物層；形成重佈線結構於第一晶片結構、第二晶片結構和模塑化合物層上方，其中重佈線結構包含介電結構和在介電結構中的接地線；實施機械性單切製程於第一晶片結構與第二晶片結構之間以切割穿透模塑化合物層、介電結構和接地線，以形成第一晶片封裝結構和第二晶片封裝結構，並在接地線中產生從第一和第二晶片封裝結構之單切側壁分別暴露出的末端擴大部分；以及分別形成第 一導電屏蔽膜和第二導電屏蔽膜於第一晶片封裝結構和第二晶片封裝結構上方，其中第一和第二導電屏蔽膜分別電性連接至從第一和第二晶片封裝結構之各自的單切側壁暴露出的末端擴大部分。
110:承載基板
120、240、A1、A2:黏著層
130:緩衝層
140:導電層
150:遮罩層
152:通孔
160、334:導通孔結構
170、310、320:晶片
180、230、262、264、266、332:介電層
210、336、338:接合墊
220:內連線結構
250、350:模塑化合物層
260:重佈線結構
261、263、265:重佈線
132、262a、264a、266a、622:開口
267:接墊
272、360:導電凸塊
274、276:接地凸塊
280:框架
300:晶片封裝體
330、610:基底
342、344:導線
400、800:晶片封裝結構
401:頂表面
402、S1、S2、S3、S4:側壁
403:底表面
410:底部填充層
500:切割輪
600:托盤
620:支架結構
630:間隔物結構
710:導電屏蔽膜
710a:導電屏蔽材料層
C:晶片結構
D:介電結構
E1、E2、E3:末端擴大部分
GL1、GL2、GL3、GL4:接地線
GP1、GP2:接地墊
L11、L12、L22、L32:長度
M1、M2、M3:主要部分
R:區域
T1、T2、T3、T12’、T22’、T32’:厚度
T12、T22、T32:最大厚度
W、W260、W400、W620:寬度
W1、W2、W3:配線層
W11、W12:線寬
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。
第1A-1O圖為依據一些實施例之形成晶片封裝結構的製程的各種階段的剖面示意圖。
第1M-1圖為依據一些實施例之第1M圖的一區域的放大剖面示意圖。
第1M-2圖為依據一些實施例之第1M圖的接地線的放大上視圖。
第1N-1圖為依據一些實施例之第1N圖中的托盤(tray)的上視圖。
第1O-1圖為依據一些實施例之第1O圖的一區域的放大剖面示意圖。
第2圖為依據一些其他實施例之部分地顯示晶片封裝結構的放大剖面示意圖。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件 及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。應當理解的是，可提供額外的操作於本發明實施例的方法之前、本發明實施例的方法中和本發明實施例的方法之後，且在本發明實施例的方法的其他實施例中，可取代或消除所述的一些操作。
第1A-1O圖為依據一些實施例之形成晶片封裝結構的製程的各種階段的剖面示意圖。依據一些實施例，如第1A圖所示，提供承載基板110。依據一些實施例，配置承載基板 110以在後續製程步驟期間提供機械性和結構性支撐。依據一些實施例，承載基板110包含玻璃、氧化矽、氧化鋁、金屬、前述之組合及/或類似材料。依據一些實施例，承載基板110包含金屬框架。
依據一些實施例，如第1A圖所示，黏著層120形成於承載基板110上方。依據一些實施例，黏著層120包含任何合適的黏著材料，例如紫外(ultraviolet)膠或光熱轉換(Light-to-Heat Conversion，LTHC)膠，其當暴露於紫外光或雷射時會失去其黏著性質。黏著層120透過使用壓合製程、旋塗製程、印刷製程或其他合適的製程形成。
依據一些實施例，如第1A圖所示，緩衝層130形成於黏著層120上方。依據一些實施例，配置緩衝層130以在後續製程期間提供接合的結構支撐並幫助減少晶粒偏移。依據一些實施例，緩衝層130包含聚合物材料，例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺或環氧樹脂。依據一些實施例，緩衝層130透過使用旋塗製程、化學氣相沉積製程、壓合製程或印刷製程形成。
依據一些實施例，如第1A圖所示，導電層140形成於緩衝層130上方。導電層140包含銅、鈦、前述之組合或其他合適的導電材料。依據一些實施例，導電層140透過使用物理氣相沉積製程或化學氣相沉積製程形成。
依據一些實施例，如第1B圖所示，遮罩層150形成於導電層140上方。依據一些實施例，遮罩層150具有通孔152 暴露導電層140的一部分。遮罩層150包含光阻材料或其他合適的材料。
依據一些實施例，如第1C圖所示，導通孔結構160形成於通孔152中。依據一些實施例，導通孔結構160也被稱為導電結構。導通孔結構160包含銅或其他合適的導電材料。
依據一些實施例，導通孔結構160的形成包含實施電鍍製程。在一些其他實施例中，不形成導電層140，且導通孔結構160的形成包含實施沉積製程和平坦化製程。
依據一些實施例，如第1D圖所示，移除遮罩層150。依據一些實施例，透過將遮罩層150浸泡於化學溶液中移除遮罩層150。舉例來說，化學溶液包含乳酸乙酯(ethyl lactate)、苯甲醚(anisole)、乙酸異戊酯(methyl butyl acetate)、乙酸正戊酯(amyl acetate)、甲酚醛樹脂(cresol novolak resin)及/或重氮基光活性化合物(diazo photoactive compound)。
依據一些實施例，如第1D圖所示，移除不被導通孔結構160覆蓋的導電層140。依據一些實施例，此移除製程包含濕蝕刻製程或乾蝕刻製程。
依據一些實施例，如第1E圖所示，晶片結構C設置於緩衝層130上方。依據一些實施例，每一晶片結構C包含晶片170、介電層180、接合墊210、內連線結構220和介電層230。依據一些實施例，如第1E圖所示，晶片170設置於緩衝層130上方。依據一些實施例，晶片170也被稱為半導體基底、系統單晶片(System on Chip，SoC)、邏輯晶粒或記憶體晶粒。在一 些其他實施例(未顯示)中，每一晶片結構C包含多個晶片170。
依據一些實施例，如第1E圖所示，在每一晶片結構C中，介電層180形成於晶片170上方。依據一些實施例，接合墊210形成於介電層180中。依據一些實施例，接合墊210電性連接至形成於晶片170中/上方的裝置(未顯示)。
依據一些實施例，如第1E圖所示，內連線結構220各自形成於接合墊210上方。依據一些實施例，內連線結構220包含導電柱或導電凸塊。
依據一些實施例，如第1E圖所示，介電層230形成於介電層180上方並圍繞內連線結構220。依據一些實施例，如第1E圖所示，黏著層240設置於緩衝層130與晶片170之間，以將晶片170接合至緩衝層130。
依據一些實施例，如第1F圖所示，模塑化合物層250形成於緩衝層130上方以覆蓋導電層140、導通孔結構160、晶片結構C和黏著層240。依據一些實施例，模塑化合物層250包含聚合物材料。依據一些實施例，模塑化合物層250透過使用成型製程形成。
依據一些實施例，如第1G圖所示，移除模塑化合物層250的頂部。依據一些實施例，此移除製程包含化學機械研磨製程。依據一些實施例，在移除製程之後，模塑化合物層250圍繞晶片結構C、導電層140和導通孔結構160。
依據一些實施例，如第1H圖所示，配線層W1形成於晶片結構C、模塑化合物層250和導通孔結構160上方。依據 一些實施例，配線層W1包含重佈線261和接地線GL1。依據一些實施例，重佈線261電性連接至導通孔結構160和晶片結構C。
依據一些實施例，接地線GL1與重佈線261、導通孔結構160和晶片結構C電性絕緣。依據一些實施例，一些接地線GL1形成於晶片結構C之間的模塑化合物層250正上方(或正好在其上)。配線層W1包含銅、鋁、鎢、鈦、前述之組合或其他合適的導電材料。
依據一些實施例，如第1H圖所示，介電層262形成於配線層W1、模塑化合物層250和晶片結構C上方。依據一些實施例，介電層262具有開口262a暴露重佈線261和接地線GL1的一部分。
依據一些實施例，如第1H圖所示，配線層W2形成於介電層262上方。依據一些實施例，配線層W2包含重佈線263和接地線GL2。依據一些實施例，重佈線263延伸至開口262a中以電性連接至重佈線261。
依據一些實施例，接地線GL2延伸至開口262a中以電性連接至接地線GL1。依據一些實施例，接地線GL2與重佈線263電性絕緣。配線層W2包含銅、鋁、鎢、鈦、前述之組合或其他合適的導電材料。
依據一些實施例，如第1H圖所示，介電層264形成於配線層W2和介電層262上方。依據一些實施例，介電層264具有開口264a暴露重佈線263的一部分。
依據一些實施例，如第1H圖所示，配線層W3形成 於介電層264上方。依據一些實施例，配線層W3包含重佈線265、接地線GL3和接地線GL4。依據一些實施例，重佈線265延伸至開口264a中以電性連接至重佈線263。
依據一些實施例，接地線GL4電性連接至接地線GL1和GL2。依據一些實施例，接地線GL3和GL4與重佈線265電性絕緣。配線層W3包含銅、鋁、鎢、鈦、前述之組合或其他合適的導電材料。
依據一些實施例，如第1H圖所示，介電層266形成於配線層W3和介電層264上方。依據一些實施例，介電層266具有開口266a暴露重佈線265和接地線GL3的一部分。
依據一些實施例，如第1H圖所示，接墊267以及接地墊GP1和GP2形成於介電層266上方。依據一些實施例，接墊267延伸進入開口266a中以電性連接至其下的重佈線265。依據一些實施例，接地墊GP1延伸進入開口266a中以電性連接至接地線GL3。依據一些實施例，接地墊GP2延伸進入開口266a中以電性連接至接地線GL4。
依據一些實施例，介電層262、264和266共同形成介電結構D。在一些實施例中，介電結構D和模塑化合物層250由不同材料製成。依據一些實施例，接地線GL1、GL2、GL3和GL4透過介電結構D與重佈線261、263和265以及晶片結構C電性絕緣。依據一些實施例，介電結構D、配線層W1、W2和W3、接墊267以及接地墊GP1和GP2共同形成重佈線結構260。
依據一些實施例，如第1I圖所示，導電凸塊272以 及接地凸塊274和276分別形成於接墊267以及接地墊GP1和GP2上方。依據一些實施例，導電凸塊272以及接地凸塊274和276包含錫(Sn)或其他合適的材料。
依據一些實施例，導電凸塊272以及接地凸塊274和276的形成包含形成焊錫膏(solder paste)於接墊267以及接地墊GP1和GP2上方並將焊錫膏回焊(reflow)。
依據一些實施例，如第1J圖所示，將晶片結構C顛倒翻轉並設置於框架280(或載板)上方。依據一些實施例，如第1J圖所示，移除承載基板110和黏著層120。
依據一些實施例，如第1K圖所示，移除緩衝層130的一部分以形成開口132於緩衝層130中。依據一些實施例，開口132暴露出導電層140。依據一些實施例，此移除製程可為光微影製程、雷射剝離製程或蝕刻製程。在一些其他實施例(未顯示)中，完全移除緩衝層130以暴露出導電層140。
依據一些實施例，如第1L圖所示，晶片封裝體300設置於晶片結構C和模塑化合物層250上方以與導電層140接合。依據一些實施例，每一晶片封裝體300包含晶片310和320、基底330、導線342和344、模塑化合物層350、導電凸塊360。
依據一些實施例，晶片310和320設置於基底330上方。依據一些實施例，晶片310透過晶片310與基底330之間的黏著層A1接合至基底330。依據一些實施例，晶片320透過晶片320與晶片310之間的黏著層A2接合至晶片310。
依據一些實施例，基底330包含介電層332、導通 孔結構334以及接合墊336和338。介電層332可具有彼此堆疊的多個介電膜(未顯示)。依據一些實施例，介電層332具有相對的表面332a和332b。依據一些實施例，導通孔結構334穿過介電層332。
依據一些實施例，接合墊336位於表面332a上方。依據一些實施例，接合墊336位於相應的導通孔結構334上方以電性連接至相應的導通孔結構334。依據一些實施例，接合墊338位於表面332b上方。依據一些實施例，接合墊338位於相應的導通孔結構334下方以電性連接至相應的導通孔結構334。
依據一些實施例，導線342物理和電性連接晶片310與接合墊336。依據一些實施例，導線344物理和電性連接晶片320與接合墊336。依據一些實施例，模塑化合物層350成型於晶片310和320、導線342和344以及基底330上方。
依據一些實施例，配置模塑化合物層350以保護晶片310和320以及導線342和344在後續的製程期間免受損壞和汙染。依據一些實施例，模塑化合物層350包含聚合物材料。
第1L圖中顯示的晶片封裝體300為一範例。晶片封裝體300不限於第1L圖中顯示的晶片封裝體300的類型。也就是說，晶片封裝體300可為任何合適類型的晶片封裝體。舉例來說，晶片封裝體300包含透過模塑化合物層、底部填充層、聚合物層及/或類似物圍繞的晶片。晶片封裝體300包含層疊封裝(package-on-package，PoP)類型的半導體封裝體、多晶片堆疊封裝體、包含多個晶片堆疊於基底上的晶片封裝體、僅包含一 晶片的晶片封裝體或任何合適類型的晶片封裝體。
依據一些實施例，導電凸塊360連接接合墊338與導電層140。依據一些實施例，如第1L圖所示，底部填充層410填充於基底330與緩衝層130之間。依據一些實施例，底部填充層410包含聚合物材料。
依據一些實施例，如第1M圖所示，實施機械性單切(singulation)製程於晶片封裝體300之間的底部填充層410和緩衝層130、晶片結構C之間的模塑化合物層250以及重佈線結構260上方。依據一些實施例，機械性單切製程切割穿透底部填充層410、緩衝層130、模塑化合物層250、介電結構D以及接地線GL1、GL2和GL3，以形成獨立的晶片封裝結構400。
依據一些實施例，每一晶片封裝結構400包含晶片封裝體300、晶片結構C、模塑化合物層250的一部分、介電結構D、接地線GL1、GL2、GL3和GL4、重佈線261、263和265、接墊267、接地墊GP1和GP2、導電凸塊272、接地凸塊274和276、導電層140以及導通孔結構160。
第1M-1圖為依據一些實施例之第1M圖的區域R的放大剖面示意圖。依據一些實施例，如第1M-1圖所示，接地線GL1、GL2和GL3分別定義橫向可觸及的側壁S1、S2和S3。依據一些實施例，側壁S1、S2和S3的每一者的至少一部分不被介電結構D覆蓋。
在一些實施例中，整個側壁S1、S2和S3不被介電結構D覆蓋(舉例來說，介電結構D完全地橫向暴露出側壁S1、 S2和S3)。依據一些實施例，介電結構D定義側壁S4。依據一些實施例，模塑化合物層250定義側壁252。依據一些實施例，側壁S4和252也被稱為單切側壁。依據一些實施例，側壁S1、S2、S3、S4和252大至共平面。
特別來說，依據一些實施例，接地線GL1包含主要部分M1和連接至主要部分M1的末端擴大部分E1。依據一些實施例，主要部分M1的長度L11大於末端擴大部分E1的長度L12。
依據一些實施例，末端擴大部分E1的最大厚度T12大於主要部分M1的最大厚度T11。依據一些實施例，最大厚度T12與最大厚度T11的比值在約1.1至4之間。在一些實施例中，主要部分M1具有大致均勻的厚度。
依據一些實施例，接地線GL2包含主要部分M2和連接至主要部分M2的末端擴大部分E2。依據一些實施例，主要部分M2的長度(未顯示)大於末端擴大部分E2的長度L22。
依據一些實施例，末端擴大部分E2的最大厚度T22大於主要部分M2的最大厚度T21。依據一些實施例，最大厚度T22與最大厚度T21的比值在約1.1至4之間。
依據一些實施例，接地線GL3包含主要部分M3和連接至主要部分M3的末端擴大部分E3。依據一些實施例，主要部分M3的長度(未顯示)大於末端擴大部分E3的長度L32。依據一些實施例，末端擴大部分E1、E2和E3從單切側壁S4和252露出。
依據一些實施例，末端擴大部分E3的最大厚度T32 大於主要部分M3的最大厚度T31。依據一些實施例，最大厚度T32與最大厚度T31的比值在約1.1至4之間。在一些實施例中，主要部分M3具有大致均勻的厚度。
依據一些實施例，接地線GL1、GL3和GL3的材料的延展性(ductility)大於介電結構D的延展性，且因此末端擴大部分E1、E2和E3的最大厚度T12、T22和T32透過機械性單切製程擴大。因此，機械性單切製程擴大側壁S1、S2和S3的面積。
因此，也擴大了接地線GL1、GL3和GL3與後續形成於側壁S1、S2和S3上方的導電屏蔽膜之間的接觸面積。因此，依據一些實施例，減少了接地線GL1、GL3和GL3與導電屏蔽膜之間的接觸電阻。
依據一些實施例，如第1M圖和第1M-1圖所示，接地線GL1的末端擴大部分E1部分地延伸進入模塑化合物層250。依據一些其他實施例，第2圖為依據一些其他實施例之部分地顯示晶片封裝結構的放大剖面示意圖。在一些其他實施例中，如第2圖所示，當模塑化合物層250具有足夠大的硬度，接地線GL1的末端擴大部分E1不延伸進入模塑化合物層250。
第1M-2圖為依據一些實施例之第1M圖的接地線GL1的放大上視圖。如第1M-2圖所示，末端擴大部分E1的線寬W12大於主要部分M1的線寬W11。也就是說，依據一些實施例，末端擴大部分E1的線寬W12透過機械性單切製程擴大。
類似地，依據一些實施例，末端擴大部分E2和E3的線寬也透過機械性單切製程擴大。因此，依據一些實施例， 末端擴大部分E2的線寬大於主要部分M2的線寬，且末端擴大部分E3的線寬大於主要部分M3的線寬。
依據一些實施例，如第1M-2圖所示，末端擴大部分E1的線寬從主要部分M1到側壁S1連續地增加。類似地，依據一些實施例，末端擴大部分E2的線寬從主要部分M2到側壁S2連續地增加。依據一些實施例，末端擴大部分E3的線寬從主要部分M3到側壁S3連續地增加。
依據一些實施例，如第1M圖所示，使用切割輪500實施機械性單切製程。依據一些實施例，每一切割輪500具有從約50μm到約350μm的範圍內的寬度W。在一些實施例中，每一切割輪500的寬度W取決於兩相鄰晶片封裝結構400之間的切割道(saw street)的寬度。在一些實施例中，機械性單切製程的鋸片速度的範圍從約5000rpm到約45000rpm。
當寬度W和鋸片速度足夠大時(例如大於50μm和5000rpm)，機械性單切製程能夠有效地擴大側壁S1、S2和S3的面積。因此，依據一些實施例，有效地減少了接地線GL1、GL3和GL3與導電屏蔽膜之間的接觸電阻。
第1N-1圖為依據一些實施例之第1N圖中的托盤的上視圖。依據一些實施例，如第1N圖和第1N-1圖所示，晶片封裝結構400設置於托盤600上方。依據一些實施例，托盤600包含基底610、支架結構620和間隔物結構630。
依據一些實施例，支架結構620設置於基底610上方且彼此間隔開。依據一些實施例，支架結構620以陣列形式 排列。依據一些實施例，每一支架結構620具有開口622暴露出基底610。在一些實施例中，支架結構620的寬度W620小於晶片封裝結構400的寬度W400。在一些實施例中，支架結構620的寬度W620小於重佈線結構260的寬度W260。
依據一些實施例，支架結構620具有上視形狀對應於支架結構620上方之晶片封裝結構400(或重佈線結構260)的上視形狀。舉例來說，晶片封裝結構400具有正方形形狀，而支架結構620也具有正方形形狀。支架結構620可具有矩形形狀、鑽石形狀或其他合適的形狀。
依據一些實施例，間隔物結構630設置於基底610上方且在支架結構620之間。依據一些實施例，間隔物結構630與支架結構620間隔開。依據一些實施例，基底610、支架結構620和間隔物結構630由相同材料製成，例如金屬、陶瓷、合金(例如不鏽鋼或鋁合金)或聚合物。
依據一些實施例，晶片封裝結構400設置於相應的支架結構620上方。依據一些實施例，晶片封裝結構400的導電凸塊272以及接地凸塊274和276在晶片封裝結構400下方的支架結構620的開口622中。
依據一些實施例，如第1N圖所示，導電屏蔽材料層710a形成於晶片封裝結構400和托盤600上方。依據一些實施例，導電屏蔽材料層710a順應性地覆蓋晶片封裝結構400和托盤600。依據一些實施例，導電屏蔽材料層710a順應性地覆蓋每一晶片封裝結構400的頂表面401、側壁402和底表面403的周 邊部分。
導電屏蔽材料層710a包含金屬材料，例如銅、鈦、不鏽鋼、鐵鎳合金、鐵、鋁、鎳、銀、金、鉻或鈦鎢合金。依據一些實施例，導電屏蔽材料層710a的形成包含沉積製程，例如物理氣相沉積製程、化學氣相沉積製程(例如常壓電漿化學氣相沉積製程)，或噴灑(噴射)製程。在一些實施例中，導電屏蔽材料層710a的形成包含電鍍製程，例如無電電鍍製程。
依據一些實施例，如第1O圖所示，移除托盤600。依據一些實施例，在此步驟中，大致形成晶片封裝結構800。為了簡潔起見，第1O圖僅顯示其中一個晶片封裝結構800。依據一些實施例，在移除托盤600之後，餘留在晶片封裝結構400上方的導電屏蔽材料層710a形成導電屏蔽膜710。依據一些實施例，導電屏蔽膜710被配置為電磁干擾(electromagnetic interference，EMI)屏蔽膜。
依據一些實施例，導電屏蔽膜710電性連接至接地線GL1、GL2、GL3和GL4。依據一些實施例，導電屏蔽膜710透過接地線GL3和接地墊GP1電性連接至接地凸塊274。依據一些實施例，導電屏蔽膜710透過接地線GL1、GL2和GL4以及接地墊GP2電性連接至接地凸塊276。
依據一些實施例，導電屏蔽膜710直接接觸接地線GL1、GL2和GL3、介電結構D、模塑化合物層250、緩衝層130、底部填充層410以及模塑化合物層350。依據一些實施例，導電屏蔽膜710順應性地覆蓋接地線GL1、GL2和GL3、介電結構D、 模塑化合物層250、緩衝層130、底部填充層410以及模塑化合物層350。
第1O-1圖為依據一些實施例之第1O圖的區域R的放大剖面示意圖。依據一些實施例，如第1O圖和第1O-1圖所示，導電屏蔽膜710順應性地覆蓋並直接接觸接地線GL1、GL2和GL3、介電結構D、模塑化合物層250的側壁S1、S2、S3、S4和252。
依據一些實施例，如第1N圖、第1O圖和第1O-1圖所示，在導電屏蔽材料層710a的形成期間，由於重佈線結構260的屏蔽，導電屏蔽膜710(或導電屏蔽材料層710a)在底表面403上方具有厚度T1小於導電屏蔽膜710在側壁402上方的厚度T2。依據一些實施例，厚度T2的範圍從約0.05μm到約50μm。
依據一些實施例，由於厚度T1小，因此容易將在底表面403上方的導電屏蔽材料層710a與在支架結構620上方的導電屏蔽材料層710a分離，並不損壞餘留在底表面403上方的導電屏蔽材料層710a。
依據一些實施例，如第1N圖、第1O圖和第1O-1圖所示，當導電屏蔽材料層710a透過使用沉積製程形成時，導電屏蔽膜710在側壁402上方的厚度T2小於導電屏蔽膜710在頂表面401上方的厚度T3。也就是說，依據一些實施例，厚度T3大於厚度T2，且厚度T2大於厚度T1。
依據一些實施例，如第1O-1圖所示，末端擴大部分E1的厚度T12’從主要部分M1至導電屏蔽膜710連續地增 加。在一些實施例中，末端擴大部分E2的厚度T22’從主要部分M2至導電屏蔽膜710連續地增加。在一些實施例中，末端擴大部分E3的厚度T32’從主要部分M3至導電屏蔽膜710連續地增加。
由於末端擴大部分E1、E2和E3的厚度T12’、T22’和T32’透過機械性單切製程擴大，也擴大了側壁S1、S2和S3的面積。因此，依據一些實施例，減少了接地線GL1、GL3和GL3與導電屏蔽膜710之間的接觸電阻。依據一些實施例，如第1M-1圖和第1O-1圖所示，末端擴大部分E1或E3包含扇形(或梯形)的剖面輪廓。
依據一些實施例，提供晶片封裝結構及其形成方法。這些方法(用於形成晶片封裝結構)形成包含介電結構和接地線於其中的重佈線結構，且接地線包含主要部分和連接至主要部分的末端擴大部分。末端擴大部分較主要部分厚。介電結構不覆蓋末端擴大部分的第一側壁。這些方法形成晶片結構於重佈線結構上方，並形成導電屏蔽膜於晶片結構和第一側壁上方，以電性連接至接地線。因此，導電屏蔽膜能夠透過接地線接地。由於末端擴大部分較主要部分厚，因此擴大了接地線與導電屏蔽膜之間的接觸面積。因此，減少了接地線與導電屏蔽膜之間的接觸電組。
依據一些實施例，提供晶片封裝結構。晶片封裝結構包含重佈線結構，重佈線結構包含介電結構和在介電結構中的接地線。接地線包含主要部分和連接至主要部分且從介電 結構橫向露出的末端擴大部分。晶片封裝結構包含晶片結構位於重佈線結構上方。晶片封裝結構包含導電屏蔽膜設置於晶片結構和末端擴大部分的第一側壁上方。導電屏蔽膜電性連接至接地線，末端擴大部分的厚度從主要部分增加至導電屏蔽膜。
在一些其他實施例中，其中導電屏蔽膜直接接觸末端擴大部分的第一側壁。
在一些其他實施例中，其中介電結構具有第二側壁，且上述晶片封裝結構更包含模塑化合物層位於重佈線結構上方並圍繞晶片結構，其中模塑化合物層具有第三側壁，且第一側壁、第二側壁和第三側壁大致共平面。
在一些其他實施例中，其中導電屏蔽膜順應性地覆蓋第一側壁、第二側壁和第三側壁。
在一些其他實施例中，其中晶片結構具有第一頂表面，導電屏蔽膜覆蓋第一頂表面，且導電屏蔽膜覆蓋第一頂表面的第一厚度大於導電屏蔽膜覆蓋第一側壁的第二厚度。
在一些其他實施例中，其中重佈線結構具有第二頂表面和相對於第二頂表面的底表面，晶片結構位於第二頂表面上方，且導電屏蔽膜更覆蓋底表面的一部份。
在一些其他實施例中，其中導電屏蔽膜覆蓋第一側壁的第二厚度大於導電屏蔽膜覆蓋底表面的第三厚度。
在一些其他實施例中，其中末端擴大部分的厚度從主要部分到導電屏蔽膜連續地增加。
在一些其他實施例中，其中重佈線結構具有頂表 面和相對於頂表面的底表面，晶片結構位於頂表面上方，且上述晶片封裝結構更包含導電凸塊位於底表面上方，其中導電屏蔽膜和接地線電性連接至導電凸塊。
依據一些實施例，提供晶片封裝結構。晶片封裝結構包含重佈線結構，重佈線結構包含介電結構和在介電結構中的接地線。接地線包含主要部分和連接至主要部分且從介電結構橫向露出的末端擴大部分。末端擴大部分的最大厚度大於主要部分的最大厚度。末端擴大部分定義第一側壁，且介電結構不覆蓋第一側壁的至少一部份。晶片封裝結構包含晶片結構位於重佈線結構上方。晶片封裝結構包含導電屏蔽膜設置於晶片結構上方，且導電屏蔽膜透過末端擴大部分電性連接至接地線。
在一些其他實施例中，其中導電屏蔽膜直接接觸末端擴大部分的第一側壁。
在一些其他實施例中，其中接地線透過介電結構與晶片結構電性絕緣。
在一些其他實施例中，其中末端擴大部分包含扇形或梯形的剖面輪廓。
在一些其他實施例中，其中末端擴大部分的線寬大於主要部分的線寬。
在一些其他實施例中，其中介電結構具有第二側壁，且上述晶片封裝結構更包含模塑化合物層位於重佈線結構上方並圍繞晶片結構，其中模塑化合物層具有第三側壁，第一 側壁、第二側壁和第三側壁大致共平面，且末端擴大部分延伸進入模塑化合物層。
依據一些實施例，提供晶片封裝結構的形成方法。此方法包含提供第一晶片結構、第二晶片結構和圍繞第一晶片結構和第二晶片結構的模塑化合物層。此方法包含形成重佈線結構於第一晶片結構、第二晶片結構和模塑化合物層上方。重佈線結構包含介電結構和在介電結構中的接地線。此方法包含實施機械性單切製程於第一晶片結構與第二晶片結構之間以切割穿透模塑化合物層、介電結構和接地線，以形成第一晶片封裝結構和第二晶片封裝結構並在接地線中產生從第一和第二晶片封裝結構之單切側壁分別暴露出的末端擴大部分。此方法包含分別形成第一導電屏蔽膜和第二導電屏蔽膜於第一晶片封裝結構和第二晶片封裝結構上方。第一和第二導電屏蔽膜分別電性連接至從第一和第二晶片封裝結構之各自的單切側壁暴露出的末端擴大部分。
在一些其他實施例中，上述方法更包含在機械性單切製程之前，形成第一導電凸塊和第二導電凸塊於重佈線結構上方，其中接地線電性連接至第一導電凸塊和第二導電凸塊，且在機械性單切製程之後，從第一晶片封裝結構的單切側壁暴露出的末端擴大部分電性連接至第一導電凸塊，從第二晶片封裝結構的單切側壁暴露出的末端擴大部分電性連接至第二導電凸塊，且從第一晶片封裝結構的單切側壁暴露出的末端擴大部分以及第一導電凸塊與從第二晶片封裝結構的單切側 壁暴露出的末端擴大部分以及第二導電凸塊電性絕緣。
在一些其他實施例中，其中第一導電屏蔽膜和第二導電屏蔽膜的形成包含提供托盤，托盤包含基底、第一支架結構和第二支架結構，其中第一支架結構和第二支架結構位於基底上方，第一支架結構具有第一開口，且第二支架結構具有第二開口。分別設置第一晶片封裝結構和第二晶片封裝結構於第一支架結構和第二支架結構上方，其中第一導電凸塊在第一開口中，且第二導電凸塊在第二開口中。形成導電屏蔽材料層於第一晶片封裝結構、第二晶片封裝結構和托盤上方，以及移除托盤。
在一些其他實施例中，其中第一支架結構的寬度小於第一晶片封裝結構的寬度。
在一些其他實施例中，其中接地線的材料的延展性大於介電結構的材料的延展性。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明進行各種改變、置換或修改。
130:緩衝層
250、350:模塑化合物層
260:重佈線結構
267:接墊
272:導電凸塊
274、276:接地凸塊
400、800:晶片封裝結構
401:頂表面
402:側壁
403:底表面
410:底部填充層
710:導電屏蔽膜
C:晶片結構
D:介電結構
GL1、GL2、GL3、GL4:接地線
GP1、GP2:接地墊
R:區域
T1、T2、T3:厚度

Claims (9)

  1. 一種晶片封裝結構，包括：一重佈線結構，包括一介電結構和在該介電結構中的一接地線，其中該接地線包括一主要部分和連接至該主要部分且從該介電結構橫向露出的一末端擴大部分；一晶片結構，位於該重佈線結構上方；以及一導電屏蔽膜，設置於該晶片結構和該末端擴大部分的一第一側壁上方，其中該導電屏蔽膜電性連接至該接地線，其中該重佈線結構具有一頂表面和相對於該頂表面的一底表面，該晶片結構位於該頂表面上方，且該導電屏蔽膜覆蓋該底表面的一部分，且其中該末端擴大部分的一厚度從該主要部分增加至該導電屏蔽膜，且該末端擴大部分的該厚度從該主要部分到該導電屏蔽膜連續地增加。
  2. 如申請專利範圍第1項所述之晶片封裝結構，其中該導電屏蔽膜覆蓋該晶片結構的一頂表面，且該導電屏蔽膜覆蓋該晶片結構的該頂表面的一第一厚度大於該導電屏蔽膜覆蓋該第一側壁的一第二厚度。
  3. 如申請專利範圍第1項所述之晶片封裝結構，其中該導電屏蔽膜覆蓋該第一側壁的一第二厚度大於該導電屏蔽膜覆蓋該重佈線結構的該底表面的一第三厚度。
  4. 一種晶片封裝結構，包括：一重佈線結構，包括一介電結構和在該介電結構中的一接地線，其中該接地線包括一主要部分和連接至該主要部分且從該介電結構橫向露出的一末端擴大部分，其中該末端 擴大部分的一最大厚度大於該主要部分的一最大厚度，其中該末端擴大部分定義一第一側壁，且其中該介電結構不覆蓋該第一側壁的至少一部分；一晶片結構，位於該重佈線結構上方；一導電屏蔽膜，設置於該晶片結構上方並透過該末端擴大部分電性連接至該接地線，其中該末端擴大部分的厚度從該主要部分到該導電屏蔽膜連續地增加；以及一晶片封裝體，位於該導電屏蔽膜與該晶片結構之間，其中該重佈線結構包括在該介電結構中的一第二接地線，該第二接地線包括一第二主要部分和連接至該第二主要部分的一第二末端擴大部分，且該接地線的該末端擴大部分直接接觸該第二接地線的該第二末端擴大部分。
  5. 一種晶片封裝結構，包括：一重佈線結構，包括一介電結構和在該介電結構中的一第一接地線和一第二接地線，其中該第一接地線包括一第一主要部分和連接至該第一主要部分且從該介電結構橫向露出的一第一末端擴大部分，其中該第二接地線包括一第二主要部分和連接至該第二主要部分且從該介電結構橫向露出的一第二末端擴大部分，且其中該第一末端擴大部分直接接觸該第二末端擴大部分；一晶片結構，位於該重佈線結構上方；以及一導電屏蔽膜，設置於該晶片結構、該第一末端擴大部分的一第一側壁和該第二末端擴大部分的一第二側壁上方，其中該導電屏蔽膜電性連接至該第一接地線和該第二接地 線，其中該第一末端擴大部分的一厚度從該第一主要部分增加至該導電屏蔽膜，且該第二末端擴大部分的一厚度從該第二主要部分增加至該導電屏蔽膜，其中該第一末端擴大部分的該厚度從該第一主要部分到該導電屏蔽膜連續地增加。
  6. 一種晶片封裝結構的形成方法，包括：沉積一第一晶片結構和一第二晶片結構於一承載基板上方；形成一模塑化合物層圍繞該第一晶片結構和該第二晶片結構；形成一介電結構於該模塑化合物層上方，且形成一第一接地線於該介電結構中；以及切割該第一接地線以形成該第一接地線的一第一末端擴大部分，其中該第一末端擴大部分具有一逐漸增加的厚度。
  7. 如申請專利範圍第6項所述之晶片封裝結構的形成方法，其中該介電結構具有一頂表面和相對於該頂表面的一底表面，該第一晶片結構位於該頂表面上方，且該第一導電屏蔽膜延伸以覆蓋該底表面的一部分。
  8. 一種晶片封裝結構的形成方法，包括：設置一第一晶片結構和一第二晶片結構於一承載基板上方；形成一模塑化合物層圍繞該第一晶片結構和該第二晶片結構； 形成一介電結構和一接地線於該第一晶片結構、該第二晶片結構和該模塑化合物層上方，其中該接地線位於該介電結構中；以及切割通過該模塑化合物層、該介電結構和該接地線以形成一第一晶片封裝結構和一第二晶片封裝結構，且在該第一晶片封裝結構中產生該接地線的一第一末端擴大部分，其中該第一末端擴大部分的一側壁暴露出該介電結構的一側壁。
  9. 一種晶片封裝結構的形成方法，包括：提供一第一晶片結構、一第二晶片結構和圍繞該第一晶片結構和該第二晶片結構的一模塑化合物層；形成一重佈線結構於該第一晶片結構、該第二晶片結構和該模塑化合物層上方，其中該重佈線結構包括一介電結構和在該介電結構中的一接地線；實施一機械性單切製程於該第一晶片結構與該第二晶片結構之間以切割穿透該模塑化合物層、該介電結構和該接地線，以形成一第一晶片封裝結構和一第二晶片封裝結構，並在該接地線中產生從該第一晶片封裝結構和該第二晶片封裝結構的單切側壁分別暴露出的末端擴大部分；以及分別形成一第一導電屏蔽膜和一第二導電屏蔽膜於該第一晶片封裝結構和該第二晶片封裝結構上方，其中該第一導電屏蔽膜和該第二導電屏蔽膜分別電性連接至從該第一晶片封裝結構和該第二晶片封裝結構各自的單切側壁暴露出的末端擴大部分。
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