TWI708345B - 半導體裝置及形成半導體裝置的方法 - Google Patents

半導體裝置及形成半導體裝置的方法 Download PDF

Info

Publication number
TWI708345B
TWI708345B TW105134977A TW105134977A TWI708345B TW I708345 B TWI708345 B TW I708345B TW 105134977 A TW105134977 A TW 105134977A TW 105134977 A TW105134977 A TW 105134977A TW I708345 B TWI708345 B TW I708345B
Authority
TW
Taiwan
Prior art keywords
die
substrate
hole
molding material
perforation
Prior art date
Application number
TW105134977A
Other languages
English (en)
Other versions
TW201715676A (zh
Inventor
陳偉銘
胡憲斌
侯上勇
魏文信
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201715676A publication Critical patent/TW201715676A/zh
Application granted granted Critical
Publication of TWI708345B publication Critical patent/TWI708345B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1141—Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
    • H01L2224/11424—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92124—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

提供一種半導體裝置以及一種形成所述裝置的方法。所述 半導體裝置包含具有第一多個接觸接墊的第一晶粒以及具有第二多個接觸接墊的第二晶粒。基板以與所述第一晶粒以及所述第二晶粒呈面對面定向的方式接合至所述第一多個接觸接墊中的第一接觸接墊以及所述第二多個接觸接墊中的第一接觸接墊。第一穿孔延伸穿過所述基板。模製材料插入於所述第一晶粒、所述第二晶粒與所述基板之間，所述模製材料沿著所述第一晶粒、所述第二晶粒以及所述基板的側壁延伸。第二穿孔定位於第一多個接觸接墊中的第二接觸接墊上方，所述第二穿孔延伸穿過模製材料。

Description

半導體裝置及形成半導體裝置的方法
本發明實施例是有關於一種積體電路結構。
隨著半導體技術演進，半導體晶片/晶粒變得愈來愈小。同時，較多功能需要整合於半導體晶粒中。因此，半導體晶粒需要具有封裝於較小區域中的愈來愈大數目個I/O接墊，且I/O接墊的密度隨時間推移而快速升高。結果，半導體晶粒的封裝變得較困難，此不利地影響封裝的良率。
習知封裝技術可劃分成兩種類別。在第一類別中，封裝晶圓上的晶粒，隨後進行鋸割。此封裝技術具有一些有利特徵，諸如較大輸送量以及較低成本。另外，需要較少底部填充料或模製化合物。然而，此封裝技術亦遭受缺點。如前述，晶粒的大小正變得愈來愈小，且各別封裝可僅為扇入型封裝，其中每一晶粒的I/O接墊限於直接在各別晶粒的表面上方的區。隨著晶粒的區域受限，I/O接墊的數目歸因於I/O接墊的間距限制而受到限制。若接墊的間距減小，則可出現焊橋。另外，在固定的球尺寸要求下，焊球必須具有一定大小，此舉又限制可封裝於晶粒的表面上 的焊球的數目。
在另一類別的封裝中，自晶圓鋸割晶粒，隨後封裝晶粒，且僅封裝「已知良好晶粒」。此封裝技術的有利特徵為形成扇出型封裝的可能性，此意謂可將晶粒上的I/O接墊重佈線至比晶粒大的區域，且因此可增加封裝於晶粒的表面上的I/O接墊的數目。
在一些實施例中，提供一種製造半導體裝置的方法。所述方法包含將第一晶粒以及第二晶粒定位於載體基板上。將第一基板接合至第一晶粒以及第二晶粒，使得第一基板連接成與第一晶粒以及第二晶粒面對面連接。第一基板包括第一基板穿孔。沿著第一晶粒、第二晶粒以及基板的側壁形成模製材料。模製材料覆蓋第一基板。形成模製材料之後，於第一晶粒上方的模製材料中形成開口。在開口上方形成第一穿孔，使得第一穿孔穿過模製材料延伸至第一晶粒。形成所述第一穿孔之後，進行研磨製程以露出第一穿孔與第一基板穿孔，第一穿孔、模製材料、第一基板與第一基板穿孔的表面在研磨製程後齊平。在第一穿孔上方形成第一外部連接件，第一外部連接件直接接觸第一穿孔，第一外部連接件包括第一焊料部。在第一基板穿孔上方形成第二外部連接件，第二外部連接件直接接觸第一基板穿孔，第二外部連接件包括第二焊料部。
在一些實施例中，將第一晶粒、第二晶粒以及第三晶粒定位於載體基板上。將第一基板接合至第一晶粒與第二晶粒上， 第一基板連接成與第一晶粒以及第二晶粒面對面連接，第一基板包括第一基板穿孔。將第二基板接合至第二晶粒與第三晶粒上，第二基板連接成與第二晶粒以及第三晶粒面對面連接，第二基板包括第二基板穿孔。沿著第一晶粒、第二晶粒、第三晶粒、第一基板以及第二基板的側壁形成模製材料，模製材料覆蓋第一基板與第二基板。在第一晶粒上方形成第一穿孔，使得第一穿孔穿過模製材料而延伸至第一晶粒。在第三晶粒上方形成第二穿孔，使得第二穿孔穿過模製材料而延伸至第三晶粒。在形成第一穿孔與第二穿孔後，進行研磨製程以露出第一穿孔、第二穿孔、第一基板穿孔與第二基板穿孔的表面。
在一些實施例中，提供一種半導體裝置。所述半導體裝置包含具有第一多個接觸接墊的第一晶粒以及具有第二多個接觸接墊的第二晶粒。基板以與第一晶粒以及第二晶粒呈面對面定向的方式接合至第一多個接觸接墊中的第一接觸接墊以及第二多個接觸接墊中的第一接觸接墊。第一穿孔延伸穿過基板。模製材料插入於第一晶粒、第二晶粒與基板之間，模製材料沿著第一晶粒、第二晶粒以及基板的側壁延伸。第二穿孔定位於第一多個接觸接墊中的第二接觸接墊上方，第二穿孔延伸穿過模製材料。
100:載體基板
102:釋放層
200:積體電路晶粒
202:接點
300:基板
302、600:穿孔
304:連接件
400:模製材料
500:開口
700:第一模製材料
800:連接件
800A:第一導電柱
800B:焊蓋
1000:第二模製材料
為了更完全地理解實施例以及其優勢，現參考結合附圖進行的以下描述，其中： 圖1至圖12為根據一些例示性實施例的穿孔(Through Via，TV)封裝的製造的中間階段的橫截面圖。
圖13為根據一些例示性實施例的穿孔(TV)封裝的橫截面。
圖14為根據一些例示性實施例的穿孔(TV)封裝的橫截面。
以下揭露內容提供用於實施所提供標的物的不同特徵的許多不同實施例或實例。下文描述組件以及配置的特定實例以簡化本發明。當然，此等組件以及配置僅僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵以及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複參考標號以及/或字母。此重複是出於簡單性以及清晰性的目的，且本身並不指示所論述的各種實施例以及/或組態之間的關係。
另外，諸如「在……之下」、「在……下方」、「下部」、「在……上方」、「上部」以及類似者的空間相對術語在本文中為易於描述而使用，以描述如諸圖中所說明的一個元件或特徵與另一元件或特徵的關係。除諸圖中所描繪的定向之外，空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定 向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據各種例示性實施例提供包含穿孔的堆疊式積體電路封裝以及形成所述堆疊式積體電路封裝的方法。說明形成封裝的中間階段並論述實施例的變體。
圖1至圖12說明根據一些實施例的形成半導體封裝的中間步驟的橫截面圖。在一些實施例中，可以減少的成本以及增加的可靠性形成本文中所描述的半導體封裝。舉例而言，在一些例示性實施例中，基板與兩個積體電路晶粒面對面連接，且基板經定位以使得其至少部分地上覆於兩積體電路晶粒。在一些實施例中，基板以及積體電路晶粒的定向以及位置允許基板與積體電路晶粒之間以及當中的較短連接，此舉可增加可靠性以及電效能。又，在一些實施例中，基板可允許細小間距金屬連接。因而，基板可實現較小空間且使用較少材料的連接，此舉可降低製造成本。
首先參看圖1，繪示上面形成有釋放層102的載體基板100。通常，載體基板100在後續處理步驟期間提供臨時機械以及結構性支撐。載體基板100可包含任何合適材料，諸如矽晶圓、玻璃或氧化矽一類的矽類材料，或諸如氧化鋁、陶瓷材料、此等材料中的任一者的組合的其他材料，或其類似者。在一些實施例中，載體基板100為平坦的以便適應進一步處理。
釋放層102為形成於載體基板100上方的可允許較容易移除載體基板100的可選層。如下文更詳細地解釋，各種層以及裝置將置放於載體基板100上方，其後可移除載體基板100。可選釋放層102有助於移除載體基板100，從而減少對形成於載體基板 100上方的結構的損害。釋放層102可由聚合物類材料形成。在一些實施例中，釋放層102為當被加熱時失去其黏著特性的環氧樹脂類熱釋放材料，諸如光熱轉換(light-to-heat-conversion；LTHC)釋放塗層。在其他實施例中，釋放層102可為在暴露於紫外線(ultra-violet；UV)光時失去其黏著特性的UV黏膠。可將釋放層102施配為液體且加以固化。在其他實施例中，釋放層102可為疊層至載體基板100上的疊層膜。可利用其他釋放層。
參看圖2，兩個積體電路晶粒200根據一些實施例接合至釋放層102的背面。在一些實施例中，積體電路晶粒200可由諸如晶粒貼合膜(die-attach film；DAF)的黏著層(未圖示)黏附至釋放層102。黏著層的厚度可介於約5μm至約50μm的範圍內，諸如約10μm。積體電路晶粒200可如圖2中所說明為兩個晶粒200，或在一些實施例中，可貼合單一晶粒或多於兩個晶粒。積體電路晶粒200可包含適於特定設計的任何晶粒。舉例而言，積體電路晶粒可包含靜態隨機存取記憶體(SRAM)晶片或動態隨機存取記憶體(DRAM)晶片、處理器、記憶體晶片、邏輯晶片、類比晶片、數位晶片、中央處理單元(CPU)、圖形處理單元(GPU)、或其組合或其類似者。積體電路晶粒200可貼合至釋放層102上的合適位置以用於特定設計或應用。在貼合至釋放層102之前，可根據所適用的製造製程來處理積體電路晶粒200以在積體電路晶粒200中形成積體電路(未圖示)。積體電路晶粒在積體電路晶粒200的背離載體基板100的表面上包括接點202。接點202允許積體電路晶粒200連接至彼此以及/或連接至其他外部裝置、組件或其類似者。如下文將詳細地描述，穿孔(TV)將形成為上覆於 某些接點202，且基板將接合至某些其他接點202。可以某種方式設計接點202在積體電路晶粒200的頂表面上的置放以使得其定位於穿孔的規劃位置或基板的規劃位置下面。
參看圖3，基板300置放於積體電路晶粒200上方以使得其與積體電路晶粒200面對面連接，且經定位以使得其至少部分地與每一積體電路晶粒重疊。基板300可允許積體電路晶粒200、基板300內部的裝置(若存在)以及封裝外部的裝置以及組件或其類似者之間以及當中的電連接。取決於結構的特定設計以及應用，基板300可含有一或多個金屬連接層、一或多個主動裝置、一或多個積體電路晶粒、一或多個被動裝置、此等裝置的組合或其類似者。基板300還可含有一或多個穿孔(TV)302，其可允許至基板300的外部電連接以及經由基板300中的金屬連接至接點202的電連接。
在一些實施例中，基板300可消除一或多個重佈線層的需要，所述層大體上提供不同於現存積體電路晶粒、穿孔或其類似者的圖案的導電圖案。舉例而言，基板300可提供會另外提供於一或多個重佈線層中的金屬連接。在一些實施例中，基板300提供消耗封裝中的較少空間且可降低製造成本的具有更細小間距的此等連接。舉例而言，在一些實施例中，基板300可包含具有約0.1μm至約20μm(諸如約0.4μm)的間距的金屬連接。
基板300經定位以使得其與積體電路晶粒200面對面連接。在一些實施例中，基板300亦經定位以使得其部分地上覆於兩個鄰近積體電路晶粒200。此組態允許基板300與積體電路晶粒200之間以及當中的金屬連接之間有較短距離。較短距離可有助於 增加金屬連接的可靠性。
可使用已知方法預形成基板300。舉例而言，可提供具有合適材料的基板300。取決於特定設計，基板300可包括一或多個主動裝置。層間介電(interlayer dielectric；ILD)可藉由化學氣相沈積、濺鍍或適於形成ILD的任何其他方法形成於基板300以及主動裝置(若存在)上方。可藉由施加並顯現合適光阻層且接著蝕刻ILD以及下伏的基板300以在基板300中形成開口來形成穿孔302。此階段的開口經形成以至少比ILD中的主動裝置更遠地延伸至基板300中，並延伸至至少大於成品基板300的最終所要高度的深度。開口可形成為具有約5μm與約20μm之間的直徑，諸如約12μm。
一旦開口已形成，開口可填充有障壁層以及導電材料以形成穿孔302。障壁層可包括諸如氮化鈦的導電材料，但可替代性地利用諸如氮化鉭、鈦、介電質或其類似者的其他材料。可使用化學氣相沈積(chemical vapor deposition；CVD)製程形成障壁層，諸如電漿增強型化學氣相沈積(plasma-enhanced chemical vapor deposition；PECVD)。然而，可替代性地使用諸如濺鍍或金屬有機化學氣相沈積(metal organic chemical vapor deposition；MOCVD)的其他替代性製程。障壁層經形成以便成型為用於穿孔302的開口的底層形狀。
導電材料可包括銅，但可替代性地利用諸如鋁、合金、經摻雜多晶矽、其組合以及其類似者的其他合適材料。導電材料可藉由沈積晶種層且接著將銅電鍍至晶種層上形成，從而填充以及過量填充用於穿孔302的開口。一旦已填充用於穿孔302的開 口，經由諸如化學機械拋光(chemical mechanical polishing；CMP)的研磨製程移除用於穿孔302的開口外的過量障壁層以及過量導電材料，但可使用任何合適移除製程。最後，薄化基板300的背面以暴露穿孔302。可藉由諸如CMP的研磨製程執行薄化，但可替代性地使用諸如蝕刻的其他合適製程。
在薄化基板300之後，可執行清洗蝕刻。此清洗蝕刻意欲在CMP之後清洗並拋光基板300。另外，此清洗蝕刻亦有助於釋放研磨基板300的CMP製程期間可能已形成的應力。清洗蝕刻可使用HNO3，但可替代性地使用其他合適蝕刻劑。
本文描述的用於形成基板300的方法僅欲作為實例。可使用形成基板300的任何合適方法，包含相同或不同方法或其類似者。
基板300可包括適於特定設計的任何材料。基板300大體上包括的材料類似於用於形成積體電路晶粒200的材料，諸如矽。雖然基板300可由其他材料形成，但咸信使用矽基板可減少應力，此是因為矽基板與通常用於積體電路晶粒200的矽之間的熱膨脹係數(coefficient of thermal expansion；CTE)失配低於由不同材料形成的基板。
在一些實施例中，基板300的大小小於積體電路晶粒200的大小。舉例而言，在一些實施例中，基板300可具有約10μm至約100μm的高度，諸如約50μm。
基板300使用連接件304接合至積體電路200上的接點202。連接件304可為微凸塊、焊球、金屬柱、受控塌陷晶粒連接(controlled collapse chip connection；C4)凸塊、化學鍍鎳鈀浸金 技術(electroless nickel-eleetroless palladium-immersion gold technique；ENEPIG)形成式凸塊、其組合(例如，具有貼合至其的焊球的金屬柱)或其類似者。連接件304可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似者或其組合。在一些實施例中，作為實例，連接件304包括共晶材料，且可包括焊料凸塊或焊球。舉例而言，焊料材料可為鉛系以及無鉛焊料，諸如鉛系焊料Pb-Sn組成物；無鉛焊料包含InSb；錫、銀以及銅(SAC)組成物；以及具有共同熔點且在電應用中形成導電焊料連接的其他共晶材料。對於無鉛焊料，作為實例，可使用具有變化組成的SAC焊料，諸如SAC 105(Sn 98.5%、Ag 1.0%、Cu 0.5%)、SAC 305以及SAC 405。諸如焊球的無鉛連接件亦可自SnCu化合物形成，而無需使用銀(Ag)。替代性地，無鉛焊料連接件可包含錫以及銀(Sn-Ag)，而無需使用銅。連接件304可形成柵格，諸如球柵陣列封裝(ball grid array；BGA)。在一些實施例中，可執行回焊製程，從而在一些實施例中給予連接件304部分球面的形狀。替代性地，連接件304可包括其他形狀。連接件304還可包括(例如)非球面導電連接件。
接下來，參看圖4，沿著積體電路晶粒200以及基板300的側壁形成模製材料400。根據一些實施例，模製材料400填充積體電路晶粒200、基板300與連接件304之間的空間。模製材料400支撐積體電路晶粒200以及基板300並減少連接件304的裂解。模製材料400可包含模製底部填充料、模製化合物、環氧樹脂或樹脂。
接下來，執行研磨步驟以薄化模製材料400，直至暴露穿 孔302。圖4中繪示所得結構。歸因於研磨，穿孔302的頂部末端實質上與模製材料400的頂表面齊平(共面)。由於研磨，諸如金屬粒子的殘留物可產生並保留於頂表面上。因此，在研磨之後，可(例如)經由濕式蝕刻執行清洗以使得移除殘留物。
參看圖5，多個開口500產生於模製材料400中。如下文將更詳細地論述，穿孔將形成於開口500中以實現至積體電路晶粒200上的接點202的外部電連接。開口500可藉由任何合適方法形成，諸如雷射鑽孔、蝕刻或其類似者。開口500的直徑取決於將形成於開口500中的規劃穿孔的所要直徑。在一些實施例中，開口500的直徑可為約50μm至約300μm，諸如約100μm。如可自圖5看出，開口500的高度由基板300的高度判定。在一些實施例中，開口500的高度可為約50μm至約300μm，諸如約100μm。
參看圖6，穿孔600形成於開口500中。穿孔600可(例如)藉由在模製材料400上方形成導電晶種層(未圖示)而形成。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。晶種層可由銅、鈦、鎳、金或其組合或其類似者製成。在一些實施例中，晶種層包括鈦層以及鈦層上方的銅層。可使用(例如)物理氣相沈積(physical vapor deposition；PVD)、CVD、原子層沈積(atomic layer deposition；ALD)、其組合或其類似者形成晶種層。
接下來，可使用(例如)化學鍍製程或電化學鍍製程用導電材料填充開口500，藉此產生穿孔600。金屬特徵穿孔600可包括銅、鋁、鎢、鎳、焊料或其合金。穿孔600的俯視圖形狀可為矩形、正方形、環形或其類似者。接下來，可執行蝕刻步驟或 研磨步驟以移除上覆於模製材料400的晶種層的暴露部分以及上覆於開口500的任何過量導電材料。可使用任何合適蝕刻或研磨製程。圖6中描繪所得結構。
在一些實施例中，當晶種層由類似或相同於穿孔600的材料形成時，晶種層可與穿孔600合併而其間不存在可區別界面。在一些實施例中，晶種層與穿孔600之間存在可區別界面。
替代性地，在一些實施例中，形成模製材料之前，穿孔600可在沿著基板300的側壁形成。舉例而言，在將基板300接合至積體電路晶粒200之前，可沿著積體電路晶粒200的側壁形成第一模製材料700，如圖7中所描繪。第一模製材料700填充積體電路晶粒200之間的間隙且可接觸釋放層102。第一模製材料700可包含模製化合物、模製底部填充料、環氧樹脂或樹脂。第一模製材料700的頂表面高於金屬接點202的頂部末端。
接下來，執行研磨步驟以薄化第一模製材料700，直至暴露金屬接點202。圖8中繪示所得結構。歸因於研磨，金屬接點202的頂部末端實質上與第一模製材料700的頂表面齊平(共面)。由於研磨，諸如金屬粒子的金屬殘留物可產生並保留於頂表面上。因此，在研磨之後，可(例如)經由濕式蝕刻執行清洗以使得移除金屬殘留物。
參看圖9，穿孔600形成於金屬接點202上方。在一些實施例中，可沈積並圖案化諸如圖案化光阻層的罩幕層，其中罩幕層中的開口暴露穿孔600的所要位置。可使用(例如)化學鍍製程或電化學鍍製程用導電材料填充開口，藉此產生穿孔600。電鍍製程可單向填充圖案化光阻層中的開口(例如，自金屬接點202 朝上)。單向填充可允許較均勻地填充此等開口。替代性地，晶種層可形成於圖案化光阻層中的開口的側壁上，且可多向填充此等開口。穿孔600可包括銅、鋁、鎢、鎳、焊料或其合金。穿孔600的俯視圖可為矩形、正方形、環形或其類似者。一旦已填充用於穿孔600的開口，經由諸如化學機械拋光(CMP)的研磨製程移除用於穿孔600的開口外的過量晶種層(若存在)以及過量導電材料，但可使用任何合適移除製程。最後，可藉由可接受灰化或剝離製程移除光阻層，諸如使用氧電漿或其類似者。
替代性地，亦可以藉由線接合製程(諸如銅線接合製程)置放的金屬線柱來實現穿孔600。使用線接合製程可消除沈積並圖案化罩幕層以及進行電鍍以形成穿孔600的需要。
參看圖9，用連接件304來使用相同或類似於上文所描述方法的方法將基板300接合至金屬接點202。接下來，參看圖10，沿著基板300以及穿孔600的側壁形成第二模製材料1000。第二模製材料1000填充穿孔600與基板300之間的間隙，且可接觸第一模製材料700或金屬接點202。第二模製材料1000可包含模製化合物、模製底部填充料、環氧樹脂或樹脂。第二模製材料1000的頂表面高於穿孔600以及穿孔302的頂部末端。
接下來，執行研磨步驟以薄化第二模製材料1000，直至暴露穿孔600以及穿孔302。圖11中繪示所得結構。歸因於研磨，穿孔600以及穿孔302的頂部末端實質上與第二模製材料1000的頂表面齊平(共面)。由於研磨，諸如金屬粒子的金屬殘留物可產生並保留於頂表面上。因此，在研磨之後，可(例如)經由濕式蝕刻執行清洗以使得移除金屬殘留物。
接下來，參看圖12，連接件800形成於穿孔600以及穿孔302上方。在一些實施例中，連接件800各自包括第一導電柱800A以及形成於第一導電柱800A上的焊蓋(或焊球)800B。
可使用任何合適方法形成連接件800。舉例而言，可使用類似於上文所描述的彼等方法的方法將晶種層(未圖示)沈積於第二模製材料1000上方。在一些實施例中，晶種層為金屬層，其可為包括單層或由不同材料形成的多個子層的複合層。晶種層可由銅、鈦、鎳、金或其組合或其類似者製成。在一些實施例中，晶種層包括鈦層以及鈦層上方的銅層。可使用(例如)物理氣相沈積(physical vapor deposition；PVD)、CVD、原子層沈積(atomic layer deposition；ALD)、其組合或其類似者形成晶種層。
接下來，光阻層可沈積於模製材料400上方並經圖案化以暴露穿孔600以及穿孔302。光阻層可藉由旋轉塗佈或其類似者形成，且可暴露於光以用於使用可接受的微影製程進行圖案化。接下來，導電柱800A可藉由在光阻層的開口中以及晶種層上形成導電材料而形成。導電材料可藉由鍍覆形成，諸如電鍍或化學鍍，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或其類似者，其可具有比(例如)焊料高的回焊溫度。第一導電柱800A的寬度對應於光阻層中的開口的寬度且可介於約20μm至約200μm的範圍內，諸如約100μm。導電柱800A的高度可介於約20μm至約150μm的範圍內，諸如約40μm，其中高度是垂直於模製材料400的頂側而量測。
焊蓋800B可使用諸如電鍍或化學鍍的鍍覆、網板印刷或其類似者形成於導電柱800A上以及光阻層的開口中。焊蓋800B 可為任何可接受可低溫回焊導電材料，諸如無鉛焊料。焊蓋800B的寬度對應於光阻層中的開口以及導電柱800A的寬度，且可介於約20μm至約200μm的範圍內，諸如約100μm。焊蓋800B的厚度可介於約5μm至約50μm的範圍內，諸如約20μm，其中厚度垂直於模製材料400的頂側。連接件800(例如，導電柱800A以及焊蓋800B)的高度介於約25μm至約200μm的範圍內，諸如約60μm。在形成焊蓋800B之後，可藉由可接受的灰化或剝離製程移除光阻層，諸如使用氧電漿或其類似者。
接下來，在完成處理之後，移除載體基板100。亦移除釋放層102。若已產生多於一個封裝，則將晶圓單一化成個別封裝。圖13中繪示所得結構。
其他實施例是可能的。舉例而言，圖14說明含有三個積體電路晶粒200以及兩個基板300的封裝。基板300以及積體電路晶粒200處於面對面定向且經由連接件304連接。每一基板300經定位以使得其與兩個積體電路晶粒200部分地重疊。連接件800提供電連接至封裝的外部。圖14中描繪的實施例可使用相同或類似於如本文中所描述方法的方法形成。
在一些實施例中，可在減少的成本以及增加的可靠性來形成本文中所描述的半導體封裝。舉例而言，在一些例示性實施例中，基板與兩個積體電路晶粒面對面連接，且基板經定位以使得其至少部分地上覆於兩積體電路晶粒。基板以及積體電路晶粒的定向以及位置允許基板與積體電路晶粒之間以及當中的較短連接，在一些實施例中此舉可增加可靠性。又，在一些實施例中，基板可允許細小間距金屬連接。因而，基板可實現較小空間且使 用較少材料的電連接，此舉可降低製造成本。
在一些實施例中，提供一種製造半導體裝置的方法。所述方法包含將第一晶粒以及第二晶粒定位於載體基板上。第一基板接合至第一晶粒以及第二晶粒，使得第一基板連接成與第一晶粒以及第二晶粒面對面連接。沿著第一晶粒、第二晶粒以及基板的側壁形成模製材料。形成所述模製材料之後，於所述第一晶粒上方的所述模製材料中形成開口。在第一晶粒上方形成第一穿孔，使得第一穿孔穿過模製材料延伸至第一晶粒。
在一些實施例中，提供一種半導體裝置。所述半導體裝置包含具有第一多個接觸接墊的第一晶粒以及具有第二多個接觸接墊的第二晶粒。基板以與第一晶粒以及第二晶粒呈面對面定向的方式接合至第一多個接觸接墊中的第一接觸接墊以及第二多個接觸接墊中的第一接觸接墊。第一穿孔延伸穿過基板。模製材料插入於第一晶粒、第二晶粒與基板之間，模製材料沿著第一晶粒、第二晶粒以及基板的側壁延伸。第二穿孔定位於第一多個接觸接墊中的第二接觸接墊上方，第二穿孔延伸穿過模製材料。
在一些實施例中，提供一種半導體裝置。所述半導體裝置包含第一晶粒以及第一晶粒近旁的第二晶粒。插入層連接至第一晶粒以及第二晶粒，插入層以插入層上的接觸接墊在面向第一晶粒以及第二晶粒的插入層的表面上的方式定向。插入層經定位以使得其與第一晶粒以及第二晶粒中的每一者部分地重疊。模製材料插入於第一晶粒、第二晶粒與插入層之間，模製材料沿著第一晶粒、第二晶粒以及插入層的側壁延伸。第一穿孔定位於第一晶粒的接觸接墊上方，第一穿孔在第一晶粒的接觸接墊與安置於 模製材料上方的外部連接件之間延伸。
在一些實施例中，在所述第一穿孔上方形成第一柱連接件；在所述基板中的穿孔上方形成第二柱連接件；以及移除所述載體基板。在所述第一柱連接件以及所述第二柱連接件中的每一者上方形成焊蓋。所述基板包括具有約0.1μm至約20μm的間距的金屬連接。使用微凸塊連接件將所述基板接合至所述第一晶粒以及所述第二晶粒。使用雷射鑽孔在所述模製材料中產生開口，其中所述第一穿孔形成於所述開口中。在所述第一晶粒近旁將第三晶粒定位於所述載體基板上；將第二基板接合至所述第一晶粒以及所述第三晶粒，所述第二基板與所述第一晶粒以及所述第三晶粒面對面連接；在所述第三晶粒上方形成所述模製材料；以及在所述第三晶粒上方形成第二穿孔，使得所述第二穿孔穿過所述模製材料延伸至所述第三晶粒。第三穿孔定位於所述第二多個接觸接墊中的第二接觸墊片上方，且所述第三穿孔延伸穿過所述模製材料。第一柱連接件，其安置於所述基板上方且連接至所述第一穿孔；第二柱連接件，其安置於所述模製材料上方且連接至所述第二穿孔。所述第一柱連接件以及所述第二柱連接件中的每一者上方的焊蓋。所述基板經定位以便部分地上覆於所述第一晶粒以及所述第二晶粒中的每一者。所述基板以所述基板的中心點上覆於所述第一晶粒與所述第二晶粒之間的區域的方式定位。第二插入層連接至所述第三晶粒以及所述第一晶粒，所述第二插入層以接觸接墊在所述第二插入層的面向所述第一晶粒以及所述第三晶粒的表面上的方式定向，且所述第二插入層經定位以使得其與所述第一晶粒以及所述第三晶粒中的每一者部分地重疊。第二穿 孔自所述第三晶粒的所述接觸接墊穿過所述模製材料延伸至安置於所述模製材料上方的柱連接件。插入層穿孔延伸穿過所述插入層。所述插入層的表面與所述模製材料的表面共面。第二柱連接件連接至所述第一穿孔的第一柱連接件以及連接至插入層穿孔。
在一些實施例中，將第一晶粒、第二晶粒以及第三晶粒定位於載體基板上；將第一基板接合至所述第一晶粒與所述第二晶粒上，所述第一基板連接成與所述第一晶粒以及所述第二晶粒面對面連接，所述第一基板包括第一基板穿孔；將第二基板接合至所述第二晶粒與所述第三晶粒上，所述第二基板連接成與所述第二晶粒以及所述第三晶粒面對面連接，所述第二基板包括第二基板穿孔；沿著所述第一晶粒、所述第二晶粒、所述第三晶粒、所述第一基板以及所述第二基板的側壁形成模製材料，所述模製材料覆蓋所述第一基板與所述第二基板；在所述第一晶粒上方形成第一穿孔，使得所述第一穿孔穿過所述模製材料而延伸至所述第一晶粒；在所述第三晶粒上方形成第二穿孔，使得所述第二穿孔穿過所述模製材料而延伸至所述第三晶粒；以及在形成所述第一穿孔與所述第二穿孔後，進行研磨製程以露出所述第一穿孔、所述第二穿孔、所述第一基板穿孔與所述第二基板穿孔的表面。使用雷射鑽孔在所述模製材料中產生第一開口以及第二開口，其中所述第一穿孔形成在所述第一開口中且所述第二穿孔形成在所述第二開口中。將所述第一穿孔形成在所述第一晶粒上方且將所述第二穿孔形成在所述第三晶粒上方；以及沿著所述第一穿孔及所述第二穿孔的側壁形成所述模製材料。在所述模製材料上方形成第一連接件，所述第一連接件接觸所述第一基板穿孔；在所述 模製材料上方形成第二連接件，所述第二連接件接觸所述第二基板穿孔；以及在所述模製材料上方形成第三連接件，所述第三連接件接觸所述第一穿孔。所述第一連接件包括所述第一基板穿孔上的銅導電柱以及所述銅導電柱上的焊料連接件。更形成第三穿孔，所述第三穿孔穿過所述第一基板與所述第二基板之間的所述模製材料。更在所述模製材料上方形成第四連接件，所述第四連接件接觸所述第三穿孔。
在一些實施例中，提供第一晶粒與第二晶粒；將第一基板結合至第一晶粒與第二晶粒，所述第一基板包括多個連接件，所述多個連接件在所述第一基板的面向所述所述第一晶粒與所述第二晶粒的第一表面上，所述第一基板使用所述多個連接件與所述第一晶粒以及所述第二晶粒面對面連接，所述第一基板具有多個基板穿孔，所述多個基板穿孔自所述第一基板的所述第一表面穿過所述基板而延伸到所述第一基板的第二表面，所述第二表面相對於所述第二表面；沿著所述第一晶粒、所述第二晶粒與所述第一基板的側壁形成模製材料，所述模製材料覆蓋所述第一基板；在所述第一晶粒上方形成第一穿孔，使得所述第一穿孔穿過所述模製材料延伸到所述第一晶粒；形成所述第一穿孔後，進行研磨製程以露出所述第一穿孔、所述第一基板的所述第二表面、所述模製材料以及所述多個基板穿孔；在所述模製材料上形成第一連接件，所述第一連接件直接接觸所述第一穿孔；以及在所述模製材料上形成第二連接件，所述第二連接件直接接觸所述多個基板穿孔的一個。所述第一連接件與所述第二連接件的每一者包括銅導電柱與焊蓋。所述第一穿孔的形成包括：使用雷射鑽孔在 所述模製材料中產生第一開口，其中所述第一穿孔形成於所述第一開口中。使用微凸塊連接件將所述第一基板接合至所述第一晶粒與所述第二晶粒。提供第三晶粒；將第二基板結合至所述第一晶粒與所述第三晶粒，所述第二基板與所述第一晶粒以及所述第三晶粒面對面連接；在所述第三晶粒上方形成所述模製材料；以及在所述第三晶粒上方形成第二穿孔，使得所述第二穿孔穿過所述模製材料而延伸至所述第三晶粒。所述第一基板的所述第二表面與所述第一穿孔及所述多個基板穿孔的表面共平面。所述模製材料環繞所述多個連接件的每一者。
儘管已詳細描述實施例以及其優勢，但應理解，在不背離由所附申請專利範圍定義的實施例的精神以及範疇的情況下，可在本文中進行各種改變、替代以及更改。此外，本申請案的範疇並不意欲限於說明書中所描述的製程、機器、產品、物質組成、構件、方法以及步驟的特定實施例。如一般技術者將易於自本發明瞭解，可根據本發明而利用執行與本文中所描述的對應實施例實質上相同的功能或實現與所述對應實施例實質上相同的結果的目前現存或稍後待開發的製程、機器、產品、物質組成、構件、方法或步驟。因此，所附申請專利範圍意欲在其範疇中包含此等製程、機器、產品、物質組成、構件、方法或步驟。另外，每一申請專利範圍構成單獨實施例，且各種申請專利範圍與實施例的組合在本發明的範疇內。
100:載體基板
200:積體電路晶粒/積體電路
300:基板
302:穿孔
304:連接件
400:模製材料

Claims (10)

  1. 一種形成半導體裝置的方法，所述方法包括：將第一晶粒以及第二晶粒定位於載體基板上；將第一基板接合至所述第一晶粒以及所述第二晶粒，所述第一基板連接成與所述第一晶粒以及所述第二晶粒面對面連接，且所述第一基板包括第一基板穿孔；沿著所述第一晶粒、所述第二晶粒以及所述基板的側壁形成模製材料，且所述模製材料覆蓋所述第一基板；形成所述模製材料之後，於所述第一晶粒上方的所述模製材料中形成開口；在所述開口中形成第一穿孔，使得所述第一穿孔穿過所述模製材料延伸至所述第一晶粒；形成所述第一穿孔之後，進行研磨製程以露出所述第一穿孔與所述第一基板穿孔，所述第一穿孔、所述模製材料、所述第一基板與所述第一基板穿孔的表面在所述研磨製程後齊平；在所述第一穿孔上方形成第一外部連接件，所述第一外部連接件直接接觸所述第一穿孔，所述第一外部連接件包括第一焊料部；以及在所述第一基板穿孔上方形成第二外部連接件，所述第二外部連接件直接接觸所述第一基板穿孔，所述第二外部連接件包括第二焊料部。
  2. 如申請專利範圍第1項所述之形成半導體裝置的方法，更包括：移除所述載體基板，其中所述第一外部連接件更包括第一導 電柱連接件，所述第一導電柱連接件實體接觸所述第一穿孔，所述第一焊料部接觸所述第一導電柱連接件；且其中所述第二外部連接件更包括第二導電柱連接件，所述第二導電柱連接件實體接觸所述所述第一基板穿孔，所述第二焊料部接觸所述第二導電柱連接件。
  3. 如申請專利範圍第1項所述之形成半導體裝置的方法，其中所述開口的形成包括：使用雷射鑽孔在所述模製材料中產生所述開口。
  4. 如申請專利範圍第1項所述之形成半導體裝置的方法，更包括：於所述載體基板上將第三晶粒定位在所述第一晶粒旁；將第二基板接合至所述第一晶粒以及所述第三晶粒，所述第二基板與所述第一晶粒以及所述第三晶粒面對面連接，所述第二基板包括第二基板穿孔；沿著所述第三晶粒的側壁形成所述模製材料，所述模製材料覆蓋所述第二基板；以及在所述第三晶粒上方形成第二穿孔，使得所述第二穿孔穿過所述模製材料延伸至所述第三晶粒。
  5. 一種形成半導體裝置的方法，包括：將第一晶粒、第二晶粒以及第三晶粒定位於載體基板上；將第一基板接合至所述第一晶粒與所述第二晶粒上，所述第一基板連接成與所述第一晶粒以及所述第二晶粒面對面連接，所述第一基板包括第一基板穿孔；將第二基板接合至所述第二晶粒與所述第三晶粒上，所述第 二基板連接成與所述第二晶粒以及所述第三晶粒面對面連接，所述第二基板包括第二基板穿孔；沿著所述第一晶粒、所述第二晶粒、所述第三晶粒、所述第一基板以及所述第二基板的側壁形成模製材料，所述模製材料覆蓋所述第一基板與所述第二基板；在所述第一晶粒上方形成第一穿孔，使得所述第一穿孔穿過所述模製材料而延伸至所述第一晶粒；在所述第三晶粒上方形成第二穿孔，使得所述第二穿孔穿過所述模製材料而延伸至所述第三晶粒；以及在形成所述第一穿孔與所述第二穿孔後，進行研磨製程以露出所述第一穿孔、所述第二穿孔、所述第一基板穿孔與所述第二基板穿孔的表面。
  6. 如申請專利範圍第5項所述之形成半導體裝置的方法，其中所述第一穿孔及所述第二穿孔的形成包括：使用雷射鑽孔在所述模製材料中產生第一開口以及第二開口，其中所述第一穿孔形成在所述第一開口中且所述第二穿孔形成在所述第二開口中。
  7. 如申請專利範圍第5項所述之形成半導體裝置的方法，更包括：在所述模製材料上方形成第一連接件，所述第一連接件接觸所述第一基板穿孔；在所述模製材料上方形成第二連接件，所述第二連接件接觸所述第二基板穿孔；以及在所述模製材料上方形成第三連接件，所述第三連接件接觸 所述第一穿孔。
  8. 如申請專利範圍第7項所述之形成半導體裝置的方法，其中所述第一連接件包括所述第一基板穿孔上的銅導電柱以及所述銅導電柱上的焊料連接件。
  9. 一種半導體裝置，包括：第一晶粒，具有第一多個接觸接墊；第二晶粒，具有第二多個接觸接墊；基板，以與所述第一晶粒以及所述第二晶粒呈面對面定向的方式接合至所述第一多個接觸接墊中的第一接觸接墊以及所述第二多個接觸接墊中的第一接觸接墊；第一穿孔，延伸穿過所述基板；模製材料，插入於所述第一晶粒、所述第二晶粒與所述基板之間，所述模製材料沿著所述第一晶粒、所述第二晶粒以及所述基板的側壁延伸；以及第二穿孔，定位於所述第一多個接觸接墊中的第二接觸接墊上方，所述第二穿孔延伸穿過模製材料，其中所述第一穿孔、所述第二穿孔與所述模製材料的表面齊平。
  10. 如申請專利範圍第9項所述之半導體裝置，更包括第三穿孔，定位於所述第二多個接觸接墊中的第二接觸接墊上方，且所述第三穿孔延伸穿過所述模製材料。
TW105134977A 2015-10-30 2016-10-28 半導體裝置及形成半導體裝置的方法 TWI708345B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/928,844 2015-10-30
US14/928,844 US10163856B2 (en) 2015-10-30 2015-10-30 Stacked integrated circuit structure and method of forming

Publications (2)

Publication Number Publication Date
TW201715676A TW201715676A (zh) 2017-05-01
TWI708345B true TWI708345B (zh) 2020-10-21

Family

ID=58635179

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105134977A TWI708345B (zh) 2015-10-30 2016-10-28 半導體裝置及形成半導體裝置的方法

Country Status (3)

Country Link
US (5) US10163856B2 (zh)
CN (1) CN106653617A (zh)
TW (1) TWI708345B (zh)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9524959B1 (en) * 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
WO2017111836A1 (en) * 2015-12-26 2017-06-29 Intel IP Corporation Package stacking using chip to wafer bonding
US10366968B2 (en) * 2016-09-30 2019-07-30 Intel IP Corporation Interconnect structure for a microelectronic device
US10833052B2 (en) 2016-10-06 2020-11-10 Micron Technology, Inc. Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
US20180166419A1 (en) * 2016-12-12 2018-06-14 Nanya Technology Corporation Semiconductor package
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10510721B2 (en) * 2017-08-11 2019-12-17 Advanced Micro Devices, Inc. Molded chip combination
CN110998835A (zh) * 2017-09-13 2020-04-10 英特尔公司 有源硅桥
US11177201B2 (en) 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
DE102018102086A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-packages und verfahren zu deren herstellung
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
KR102495582B1 (ko) 2018-02-08 2023-02-06 삼성전자주식회사 평탄화된 보호막을 갖는 반도체 소자 및 그 제조방법
CN110197793A (zh) * 2018-02-24 2019-09-03 华为技术有限公司 一种芯片及封装方法
US10622321B2 (en) * 2018-05-30 2020-04-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures and methods of forming the same
US10700051B2 (en) * 2018-06-04 2020-06-30 Intel Corporation Multi-chip packaging
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US10504835B1 (en) * 2018-07-16 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure, semiconductor chip and method of fabricating the same
US11769735B2 (en) 2019-02-12 2023-09-26 Intel Corporation Chiplet first architecture for die tiling applications
US11088100B2 (en) * 2019-02-21 2021-08-10 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US10658258B1 (en) * 2019-02-21 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package and method of forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
TWI715257B (zh) * 2019-10-22 2021-01-01 欣興電子股份有限公司 晶片封裝結構及其製作方法
CN112768422B (zh) * 2019-11-06 2024-03-22 欣兴电子股份有限公司 芯片封装结构及其制作方法
US11257763B2 (en) * 2019-12-03 2022-02-22 Advanced Semiconductor Engineering, Inc. Electronic device package and method for manufacturing the same
KR20210110008A (ko) 2020-02-28 2021-09-07 삼성전자주식회사 반도체 패키지
DE102020119971B4 (de) 2020-03-30 2022-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterstruktur mit Chip-on-Wafer-Struktur mit Chiplet-Interposer und Verfahren zum Bilden derselben
US11380611B2 (en) 2020-03-30 2022-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Chip-on-wafer structure with chiplet interposer
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11996371B2 (en) 2021-02-12 2024-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplet interposer
KR20220151989A (ko) 2021-05-07 2022-11-15 삼성전자주식회사 반도체 패키지

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100019368A1 (en) * 2008-07-25 2010-01-28 Samsung Electronics Co., Ltd. Semiconductor chip package, stacked package comprising semiconductor chips and methods of fabricating chip and stacked packages
US20120211885A1 (en) * 2011-02-17 2012-08-23 Choi Yunseok Semiconductor package having through silicon via (tsv) interposer and method of manufacturing the semiconductor package
TW201330200A (zh) * 2011-12-28 2013-07-16 Broadcom Corp 具有無半導體通孔的超薄仲介層的半導體封裝件
US20140175673A1 (en) * 2012-12-20 2014-06-26 Kilsoo Kim Semiconductor package
US20150070863A1 (en) * 2013-09-06 2015-03-12 Qualcomm Incorporated Low package parasitic inductance using a thru-substrate interposer
TW201533882A (zh) * 2014-02-21 2015-09-01 Chipmos Technologies Inc 覆晶堆疊封裝

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
US7973413B2 (en) 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
US8227902B2 (en) 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US8064224B2 (en) * 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US8021907B2 (en) * 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
US8278152B2 (en) 2008-09-08 2012-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding process for CMOS image sensor
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US8158456B2 (en) 2008-12-05 2012-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming stacked dies
US8183579B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. LED flip-chip package structure with dummy bumps
US8183578B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Double flip-chip LED package components
US8426961B2 (en) 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US8581418B2 (en) 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US20140131854A1 (en) 2012-11-13 2014-05-15 Lsi Corporation Multi-chip module connection by way of bridging blocks
US9190380B2 (en) * 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9642259B2 (en) * 2013-10-30 2017-05-02 Qualcomm Incorporated Embedded bridge structure in a substrate
US9275955B2 (en) * 2013-12-18 2016-03-01 Intel Corporation Integrated circuit package with embedded bridge
US9595496B2 (en) * 2014-11-07 2017-03-14 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer
US10008439B2 (en) * 2015-07-09 2018-06-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Thin recon interposer package without TSV for fine input/output pitch fan-out
US9368450B1 (en) * 2015-08-21 2016-06-14 Qualcomm Incorporated Integrated device package comprising bridge in litho-etchable layer
US9761533B2 (en) * 2015-10-16 2017-09-12 Xilinx, Inc. Interposer-less stack die interconnect

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100019368A1 (en) * 2008-07-25 2010-01-28 Samsung Electronics Co., Ltd. Semiconductor chip package, stacked package comprising semiconductor chips and methods of fabricating chip and stacked packages
US20120211885A1 (en) * 2011-02-17 2012-08-23 Choi Yunseok Semiconductor package having through silicon via (tsv) interposer and method of manufacturing the semiconductor package
TW201330200A (zh) * 2011-12-28 2013-07-16 Broadcom Corp 具有無半導體通孔的超薄仲介層的半導體封裝件
US20140175673A1 (en) * 2012-12-20 2014-06-26 Kilsoo Kim Semiconductor package
US20150070863A1 (en) * 2013-09-06 2015-03-12 Qualcomm Incorporated Low package parasitic inductance using a thru-substrate interposer
TW201533882A (zh) * 2014-02-21 2015-09-01 Chipmos Technologies Inc 覆晶堆疊封裝

Also Published As

Publication number Publication date
US10985137B2 (en) 2021-04-20
US20170125379A1 (en) 2017-05-04
US20190115320A1 (en) 2019-04-18
US10163856B2 (en) 2018-12-25
US10964667B2 (en) 2021-03-30
TW201715676A (zh) 2017-05-01
US20210242173A1 (en) 2021-08-05
CN106653617A (zh) 2017-05-10
US20220246581A1 (en) 2022-08-04
US20200035647A1 (en) 2020-01-30

Similar Documents

Publication Publication Date Title
TWI708345B (zh) 半導體裝置及形成半導體裝置的方法
US11276656B2 (en) Integrated fan-out structure and method of forming
US11721559B2 (en) Integrated circuit package pad and methods of forming
US11967563B2 (en) Fan-out package having a main die and a dummy die
TWI702688B (zh) 整合扇出結構及其形成方法
TWI597810B (zh) 封裝
TW201715674A (zh) 半導體元件的形成方法
TW201818520A (zh) 半導體封裝及其製作方法
TWI673848B (zh) 積體電路封裝及其形成方法
TW202213686A (zh) 具有中介物之半導體封裝