TWI715257B - 晶片封裝結構及其製作方法 - Google Patents

晶片封裝結構及其製作方法 Download PDF

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TWI715257B
TWI715257B TW108138039A TW108138039A TWI715257B TW I715257 B TWI715257 B TW I715257B TW 108138039 A TW108138039 A TW 108138039A TW 108138039 A TW108138039 A TW 108138039A TW I715257 B TWI715257 B TW I715257B
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Taiwan
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pad
substrate
chips
micro bumps
chip
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TW108138039A
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TW202117985A (zh
Inventor
林溥如
柯正達
譚瑞敏
曾子章
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欣興電子股份有限公司
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Priority to TW108138039A priority Critical patent/TWI715257B/zh
Priority to US16/687,557 priority patent/US11362057B2/en
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Publication of TWI715257B publication Critical patent/TWI715257B/zh
Publication of TW202117985A publication Critical patent/TW202117985A/zh

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Abstract

一種晶片封裝結構，包括基板、至少二個晶片、多個第一接墊、多個第一微凸塊以及橋接元件。基板具有第一表面以及與第一表面相對的第二表面。二個晶片配置於基板的第一表面，且彼此水平相鄰。各晶片具有主動表面。第一接墊配置於各晶片的主動表面。第一微凸塊配置於第一接墊上且尺寸皆相同。橋接元件配置於第一微凸塊上，以使其中一晶片透過第一接墊、第一微凸塊以及橋接元件電性連接至另一晶片。

Description

晶片封裝結構及其製作方法
本發明是有關於一種晶片封裝結構及其製作方法，且特別是有關於一種具有橋接元件的晶片封裝結構及其製作方法。
目前，在多個晶片互連的封裝結構中，嵌入式多晶片互連橋接(embedded multi-die interconnect bridge，EMIB)技術是將晶片設置在線路載板上，並利用內埋於線路載板的內埋式的橋接元件來連接不同的晶片。由於晶片需同時連接橋接元件以及線路載板，且晶片連接至橋接元件的微凸塊(micro bump)的尺寸與晶片連接至路載板的微凸塊的尺寸不同，因而使得晶片組裝時的良率不高。
本發明提供一種晶片封裝結構及其製作方法，可改善多晶片封裝的良率問題，且具有高密度連接的效果。
本發明的晶片封裝結構包括基板、至少二個晶片、多個 第一接墊、多個第一微凸塊以及橋接元件。基板具有第一表面以及與第一表面相對的第二表面。二個晶片配置於基板的第一表面，且彼此水平相鄰。各晶片具有主動表面。第一接墊配置於各晶片的主動表面。第一微凸塊配置於第一接墊上，且第一微凸塊的尺寸皆相同。橋接元件配置於第一微凸塊上，以使其中一晶片透過第一接墊、第一微凸塊以及橋接元件電性連接至另一晶片。
在本發明的一實施例中，上述的橋接元件與基板分別位於晶片的相對兩側。
在本發明的一實施例中，上述其中一晶片的主動表面與另一晶片的主動表面齊平。
在本發明的一實施例中，上述的橋接元件包括至少一介電層、至少二個圖案化線路層以及至少一第一導電孔。圖案化線路層與介電層依序疊置於第一微凸塊上。第一導電孔貫穿介電層。其中一圖案化線路層透過第一導電孔與另一圖案化線路層電性連接。
在本發明的一實施例中，上述的圖案化線路層的線寬為2微米至5微米，且圖案化線路層的線距為2微米至5微米。
在本發明的一實施例中，上述的晶片封裝結構更包括多個第二接墊、多個第三接墊以及多個導線。第二接墊配置於基板的第一表面，且位於晶片的外圍。第三接墊配置於各晶片的主動表面，且位於第一接墊的外圍。導線連接第二接墊與第三接墊，以使晶片電性連接至基板。
在本發明的一實施例中，上述的晶片封裝結構更包括多個銅柱以及多個第二微凸塊。銅柱配置於基板的第一表面，且位於晶片的外圍。第二微凸塊配置於銅柱上，以使橋接元件透過第二微凸塊以及銅柱電性連接至基板。
在本發明的一實施例中，上述的晶片封裝結構更包括連接結構以及多個第二微凸塊。連接結構配置於基板上，且位於晶片的外圍。連接結構包括第二接墊、絕緣材料層、第三接墊以及第二導電孔。第二接墊配置於基板的第一表面。絕緣材料層配置於第二接墊上。第三接墊配置於絕緣材料層上。第二導電孔貫穿絕緣材料層，以電性連接第二接墊與第三接墊。第二微凸塊配置於連接結構上，以使橋接元件透過第二微凸塊以及連接結構電性連接至基板。
在本發明的一實施例中，上述的晶片封裝結構更包括連接結構以及多個第二微凸塊。連接結構配置於基板上，且位於晶片的外圍。連接結構包括第二接墊、導電件、第三接墊、絕緣材料層、第四接墊以及第二導電孔。第二接墊配置於基板的第一表面。導電件配置於第二接墊上。第三接墊配置於導電件上。絕緣材料層配置於第三接墊上。第四接墊配置於絕緣材料層上。第二導電孔貫穿絕緣材料層，以電性連接第三接墊與第四接墊。第二微凸塊配置於連接結構上，以使橋接元件透過第二微凸塊以及連接結構電性連接至基板。
本發明的晶片封裝結構的製作方法包括以下步驟。首 先，提供一基板。基板具有第一表面以及與第一表面相對的第二表面。接著，配置至少二個晶片於基板的第一表面。二個晶片彼此水平相鄰，且各晶片具有一主動表面。然後，形成多個第一接墊於各晶片的主動表面。而後，形成多個第一微凸塊於第一接墊上。第一微凸塊的尺寸皆相同。最後，配置橋接元件於第一微凸塊上，以使其中一晶片透過第一接墊、第一微凸塊以及橋接元件電性連接至另一晶片。
在本發明的一實施例中，上述配置橋接元件於第一微凸塊上的步驟包括以下步驟。首先，提供玻璃基板。接著，形成離型層於玻璃基板上。然後，形成橋接元件於離型層上。最後，移除離型層以及玻璃基板，以將橋接元件配置於第一微凸塊上。
在本發明的一實施例中，上述的晶片封裝結構的製作方法更包括以下步驟。形成多個第二接墊於基板的第一表面，以使第二接墊位於晶片的外圍。形成多個第三接墊於各晶片的主動表面，以使第三接墊位於第一接墊的外圍。形成多個導線，以連接第二接墊與第三接墊，以使晶片電性連接至基板。
在本發明的一實施例中，上述的晶片封裝結構的製作方法更包括以下步驟。形成多個銅柱於基板的第一表面，以使銅柱位於晶片的外圍。形成多個第二微凸塊於銅柱上，以使橋接元件透過第二微凸塊以及銅柱電性連接至基板。
在本發明的一實施例中，上述的晶片封裝結構的製作方法更包括以下步驟。首先，形成連接結構於基板上，以使連接結 構位於晶片的外圍。連接結構包括第二接墊、絕緣材料層、第三接墊以及第二導電孔。第二接墊配置於基板的第一表面。絕緣材料層配置於第二接墊上。第三接墊配置於絕緣材料層上。第二導電孔貫穿絕緣材料層，以電性連接第二接墊與第三接墊。接著，形成多個第二微凸塊於連接結構上，以使橋接元件透過第二微凸塊以及連接結構電性連接至基板。
在本發明的一實施例中，上述的晶片封裝結構的製作方法更包括以下步驟。首先，形成連接結構於基板上，以使連接結構位於晶片的外圍。連接結構包括第二接墊、導電件、第三接墊、絕緣材料層、第四接墊以及第二導電孔。第二接墊配置於基板的第一表面。導電件配置於第二接墊上。第三接墊配置於導電件上。絕緣材料層配置於第三接墊上。第四接墊配置於絕緣材料層上。第二導電孔貫穿絕緣材料層，以電性連接第三接墊與第四接墊。接著，形成多個第二微凸塊於連接結構上，以使橋接元件透過第二微凸塊以及連接結構電性連接至基板。
基於上述，在本實施例的晶片封裝結構及其製作方法中，由於彼此水平相鄰的晶片皆是透過第一接墊以及第一微凸塊組裝至橋接元件，且第一微凸塊的尺寸皆相同，因而在進行多晶片組裝時，可改善多晶片封裝的良率問題。
100、100a、100b、100c:晶片封裝結構
110:基板
111:第一表面
112:第二表面
113、114:第二接墊
120、121:晶片
120a、121a:主動表面
130、131:第一接墊
132、133:第三接墊
140、141:導線
150、151:第一微凸塊
152、153:第二微凸塊
160:橋接元件
161、161a:介電層
162、162a:圖案化線路層
163:第一導電孔
170:玻璃基板
171:離型層
173:接墊
174:連接端子
180、181:銅柱
190、191、192、193:連接結構
190a、191a、192a、193a:絕緣材料層
190b、191b、192b、193b:第三接墊
190c、191c、192c、193c:第二導電孔
192d、193d:導電件
192e、193e:第四接墊
圖1A至圖1D繪示為本發明一實施例的晶片封裝結構的製作方法的剖面示意圖。
圖2繪示為本發明另一實施例的晶片封裝結構的剖面示意圖。
圖3繪示為本發明另一實施例的晶片封裝結構的剖面示意圖。
圖4繪示為本發明另一實施例的晶片封裝結構的剖面示意圖。
圖1A至圖1D繪示為本發明一實施例的晶片封裝結構的製作方法的剖面示意圖。
請參照圖1A，在本實施例中，首先，提供一基板110。基板110具有第一表面111以及與第一表面111相對的第二表面112。在本實施例中，基板110可以是有機基板、無機基板、陶瓷基板、電路板、載板、金屬基板，但不以此為限。
請繼續參照圖1A，接著，配置至少二個晶片120、121於基板110的第一表面111。晶片120與晶片121彼此水平相鄰配置。晶片120具有主動表面120a，且晶片121具有主動表面121a。在一些實施例中，其中一晶片120的主動表面120a與另一晶片121的主動表面121a齊平。在一些實施例中，可利用晶片接合膜(die attach film，DAF)將晶片120、121固定於基板110上。雖然本實 施例示意地繪示為2個晶片，但本發明並不對晶片的數量加以限制，只要使晶片的數量為2個或2個以上即可。
然後，請參照圖1B，形成多個第一接墊130、131於各晶片120、121的主動表面120a、121a(一般而言第一接墊會在晶片製作完成時即完成)。在本實施例中，第一接墊130位於晶片120的主動表面120a，且第一接墊131位於晶片121的主動表面121a。在一些實施例中，第一接墊130接觸晶片120的主動表面120a，且第一接墊131接觸晶片121的主動表面121a。
接著，請繼續參照圖1B，形成多個第二接墊113、114於基板110的第一表面111(一般而言第二接墊會在基板形成時即完成)，形成多個第三接墊132、133於各晶片120、121的主動表面120a、121a(一般而言第三接墊會在晶片製作完成時即完成)，並形成多個導線140、141以連接第二接墊113、114與第三接墊132、133。在本實施例中，第二接墊113以及第二接墊114配置於基板110的第一表面111，且皆位於晶片120、121的外圍。第三接墊132以及第三接墊133分別配置於各晶片120、121的主動表面120a、121a，且皆位於第一接墊130、131的外圍。晶片120可透過第三接墊132、導線140以及第二接墊113電性連接至基板110。晶片121可透過第三接墊133、導線141以及第二接墊114電性連接至基板110。
而後，形成多個第一微凸塊150、151於第一接墊130、131上(第一微凸塊亦可在晶片製作完成時即完成)。在本實施例 中，第一微凸塊150位於第一接墊130上，且第一微凸塊151位於第一接墊131上。第一微凸塊150接觸第一接墊130，且第一微凸塊151接觸第一接墊131。在本實施例中，第一微凸塊150的尺寸與第一微凸塊151的尺寸相同。第一微凸塊150、151的大小例如是10微米至80微米，但不以此為限。
然後，請參照圖1C，配置橋接元件160於第一微凸塊150、151上，以使其中一晶片120可透過第一接墊130、131、第一微凸塊150、151以及橋接元件160電性連接至另一晶片121。詳細來說，在本實施例中，上述配置橋接元件160於第一微凸塊150、151上的步驟包括以下步驟：首先，提供玻璃基板170。接著，形成離型層171於玻璃基板170上。然後，形成橋接元件160於離型層171上，以使橋接元件160與玻璃基板170分別位於離型層171的相對兩側。在本實施例中，橋接元件160包括至少一介電層161、161a、至少二個圖案化線路層162、162a以及至少一第一導電孔163。圖案化線路層162、162a與介電層161、161a依序疊置於第一微凸塊150、151上。第一導電孔163貫穿介電層161，以使其中一圖案化線路層162透過第一導電孔163與另一圖案化線路層162a電性連接。最後，將橋接元件160、離型層171以及玻璃基板170一同配置於第一微凸塊150、151上。在本實施例中，橋接元件160與基板110分別位於晶片120、121的相對兩側。
在本實施例中，由於玻璃基板170具有高度平整性與強 度，因而可於玻璃基板170上製作出超微細線路，並具有高密度連接的效果。在本實施例中，圖案化線路層162、162a的線寬例如是2微米至5微米，且圖案化線路層162、162a的線距例如是2微米至5微米，但不以此為限。
在本實施例的晶片封裝結構的製作方法中，雖然是在形成導線140、141以連接第二接墊113、114與第三接墊132、133，之後，才將橋接元件160配置於第一微凸塊150、151上，但本發明並不對此兩步驟的先後順序加以限制。也就是說，在一些實施例中，也可以先將橋接元件160配置於第一微凸塊150、151上之後，再形成導線140、141。
接著，請參照圖1D，移除離型層171以及玻璃基板170，並於基板110的第二表面112上形成接墊173以及連接端子174。在一些實施例中，連接端子174例如是錫球，可用於球柵陣列封裝(ball grid array，BGA)，但不以此為限。此時，已製作完成本實施例的晶片封裝結構100。
簡言之，本實施例的晶片封裝結構100包括基板110、至少二個晶片120、121、多個第一接墊130、131、多個第一微凸塊150、151以及橋接元件160。基板110具有第一表面111以及與第一表面111相對的第二表面112。二個晶片120、121配置於基板110的第一表面111，且彼此水平相鄰。各晶片120、121具有主動表面120a、121a。第一接墊130、131配置於各晶片120、121的主動表面120a、121a。第一微凸塊150、151配置於第一接墊 130、131上。橋接元件160配置於第一微凸塊150、151上，以使其中一晶片120可透過第一接墊130、131、第一微凸塊150、151以及橋接元件160電性連接至另一晶片121。
此外，在本實施例的晶片封裝結構100及其製作方法中，由於彼此水平相鄰的晶片120、121皆是透過第一接墊130、131以及第一微凸塊150、151組裝至橋接元件160，且第一微凸塊150、151的尺寸皆相同，因而在進行多晶片120、121組裝時，可改善多晶片120、121封裝的良率問題。接著，由於橋接元件160包括細線路的圖案化線路層162、162a，因而使得本實施例的晶片封裝結構100具有高密度連接的效果。
以下將列舉其他實施例以作為說明。在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖2繪示為本發明另一實施例的晶片封裝結構的剖面示意圖。請同時參照圖1D與圖2，本實施例的晶片封裝結構100a與圖1D中的晶片封裝結構100相似，惟二者主要差異之處在於：本實施例的晶片封裝結構100a更包括多個銅柱180、181以及多個第二微凸塊152、153，但不包括第二接墊113、114、第三接墊132、133以及導線140、141。
具體來說，請參照圖2，在本實施例中，銅柱180、181 配置於基板110的第一表面111，且銅柱180、181位於晶片120以及晶片121的外圍。第二微凸塊152配置於銅柱180上，且第二微凸塊153配置於銅柱181上。藉此，使橋接元件160可透過第二微凸塊152、153以及銅柱180、181電性連接至基板110。也就是說，相較於圖1D是以第三接墊132、133、導線140、141以及第二接墊113、114電性連接晶片120、121與基板110，本實施例的晶片封裝結構100a則是以第一接墊130、131、第一微凸塊150、151、橋接元件160、第二微凸塊152、153以及銅柱180、181電性連接晶片120、121與基板110。在一些實施例中，銅柱180的頂表面180a與第一接墊130面向第一微凸塊150的表面齊平，且銅柱181的頂表面181a與第一接墊131面向第一微凸塊151的表面齊平。在一些實施例中，第二微凸塊152、153的尺寸與第一微凸塊150、151的尺寸相同。在一些實施例中，銅柱180、181接觸基板110的第一表面111。
圖3繪示為本發明另一實施例的晶片封裝結構的剖面示意圖。請同時參照圖2與圖3，本實施例的晶片封裝結構100b與圖2中的晶片封裝結構100a相似，惟二者主要差異之處在於：本實施例的晶片封裝結構100b以連接結構190、191取代圖2中的銅柱180、181。
具體來說，請參照圖3，在本實施例中，連接結構190、191配置於基板110的第一表面111上，且位於晶片120、121的外圍。連接結構190、191包括第二接墊113、114、絕緣材料層 190a、191a、第三接墊190b、191b以及第二導電孔190c、191c。第二接墊113、114配置於基板110的第一表面111。絕緣材料層190a、191a配置於第二接墊113、114上，且覆蓋第二接墊113、114以及部分第一表面111。第三接墊190b、191b配置於絕緣材料層190a、191a上。第二導電孔190c、191c貫穿絕緣材料層190a、191a，以電性連接第二接墊113、114與第三接墊190b、191b。第二微凸塊152、153配置於連接結構190、191上，以使橋接元件160可透過第二微凸塊152、153以及連接結構190、191電性連接至基板110。在一些實施例中，第二接墊113、114接觸基板110的第一表面111。在一些實施例中，絕緣材料層190a、191a的材料例如是ABF、Polyimide、Epoxy、Silicone，但不以此為限。在一些實施例中，可在形成連接結構於基板110的第一表面111上並於連接結構中形成一開口之後，才將晶片120、121配置於基板110的第一表面111上並使晶片120、121位於所述開孔中。
圖4繪示為本發明另一實施例的晶片封裝結構的剖面示意圖。請同時參照圖2與圖4，本實施例的晶片封裝結構100c與圖2中的晶片封裝結構100a相似，惟二者主要差異之處在於：本實施例的晶片封裝結構100c以連接結構192、193取代圖2中的銅柱180、181。
具體來說，請參照圖4，在本實施例中，連接結構192、193配置於基板110的第一表面111上，且位於晶片120、121的外圍。連接結構192、193包括第二接墊113、114、導電件192d、 193d、第三接墊192b、193b、絕緣材料層192a、193a、第四接墊192e、193e以及第二導電孔192c、193c。第二接墊113、114配置於基板110的第一表面111。導電件192d、193d配置於第二接墊113、114上。第三接墊192b、193b配置於導電件192d、193d上。絕緣材料層192a、193a配置於第三接墊192b、193b上。第四接墊192e、193e配置於絕緣材料層192a、193a上。第二導電孔192c、193c貫穿絕緣材料層192a、193a，以電性連接第三接墊192b、193b與第四接墊192e、193e。第二微凸塊152、153配置於連接結構192、193上，以使橋接元件160透過第二微凸塊152、153以及連接結構192、193電性連接至基板110。在一些實施例中，第二接墊113、114接觸基板110的第一表面111。在一些實施例中，導電件192d、193d材質例如是金、銀、錫、銅或其他合金材料，但不以此為限。在本實施例中，連接結構192是以雙層板為例，在其他實施例中也可以是三層板或三層板以上，但不以此為限。
綜上所述，在本實施例的晶片封裝結構及其製作方法中，由於彼此水平相鄰的晶片皆是透過第一接墊以及第一微凸塊組裝至橋接元件，且第一微凸塊的尺寸皆相同，因而在進行多晶片組裝時，可改善多晶片封裝的良率問題。接著，由於橋接元件包括細線路的圖案化線路層，因而使得本實施例的晶片封裝結構具有高密度連接的效果。
100:晶片封裝結構
110:基板
111:第一表面
112:第二表面
113、114:第二接墊
120、121:晶片
120a、121a:主動表面
130、131:第一接墊
132、133:第三接墊
140、141:導線
150、151:第一微凸塊
160:橋接元件
161、161a:介電層
162、162a:圖案化線路層
163:第一導電孔
173:接墊
174:連接端子

Claims (16)

  1. 一種晶片封裝結構，包括：一基板，具有一第一表面以及與該第一表面相對的一第二表面；至少二個晶片，配置於該基板的第一表面，該些晶片彼此水平相鄰，且各該晶片具有一主動表面；多個第一接墊，配置於各該晶片的該主動表面；多個第一微凸塊，配置於該些第一接墊上，且該些第一微凸塊的尺寸皆相同；一橋接元件，配置於該些第一微凸塊上，以使其中一該晶片透過該些第一接墊、該些第一微凸塊以及該橋接元件電性連接至另一該晶片；多個連接件，配置於該基板的該第一表面上，其中該些連接件位於該些晶片的外圍且圍繞該些晶片；以及多個第二微凸塊，配置於該些連接件上，以使該橋接元件透過該些第二微凸塊以及該些連接件電性連接至該基板，其中該些第一微凸塊的尺寸與該些第二微凸塊的尺寸相同。
  2. 如申請專利範圍第1項所述的晶片封裝結構，其中該橋接元件與該基板分別位於該些晶片的相對兩側。
  3. 如申請專利範圍第1項所述的晶片封裝結構，其中該些晶片的其中一該晶片的該主動表面與另一該晶片的該主動表面齊平。
  4. 如申請專利範圍第1項所述的晶片封裝結構，其中該橋接元件包括至少一介電層、至少二個圖案化線路層以及至少一第一導電孔，該圖案化線路層與該介電層依序疊置於該些第一微凸塊上，該第一導電孔貫穿該介電層，且其中一該圖案化線路層透過該第一導電孔與另一該圖案化線路層電性連接。
  5. 如申請專利範圍第4項所述的晶片封裝結構，其中該些圖案化線路層的線寬為2微米至5微米，且該些圖案化線路層的線距為2微米至5微米。
  6. 如申請專利範圍第1項所述的晶片封裝結構，其中該些連接件包括：多個銅柱，配置於該基板的第一表面，且位於該些晶片的外圍。
  7. 如申請專利範圍第1項所述的晶片封裝結構，其中該些連接件包括：一連接結構，配置於該基板上，且位於該些晶片的外圍，其中該連接結構包括：一第二接墊，配置於該基板的第一表面；一絕緣材料層，配置於該第二接墊上；一第三接墊，配置於該絕緣材料層上；以及一第二導電孔，貫穿該絕緣材料層，以電性連接該第二接墊與該第三接墊。
  8. 如申請專利範圍第1項所述的晶片封裝結構，其中該些連接件包括：一連接結構，配置於該基板上，且位於該些晶片的外圍，其中該連接結構包括：一第二接墊，配置於該基板的第一表面；一導電件，配置於該第二接墊上；一第三接墊，配置於該導電件上；一絕緣材料層，配置於該第三接墊上；一第四接墊，配置於該絕緣材料層上；以及一第二導電孔，貫穿該絕緣材料層，以電性連接該第三接墊與該第四接墊。
  9. 一種晶片封裝結構的製作方法，包括：提供一基板，且該基板具有一第一表面以及與該第一表面相對的一第二表面；配置至少二個晶片於該基板的第一表面，其中該些晶片彼此水平相鄰，且各該晶片具有一主動表面；形成多個第一接墊於各該晶片的該主動表面；形成多個第一微凸塊於該些第一接墊上，且該些第一微凸塊的尺寸皆相同；配置一橋接元件於該些第一微凸塊上，以使其中一該晶片透過該些第一接墊、該些第一微凸塊以及該橋接元件電性連接至另一該晶片； 形成多個連接件於該基板的該第一表面，以使該些連接件位於該些晶片的外圍且圍繞該些晶片；以及形成多個第二微凸塊於該些連接件上，以使該橋接元件透過該些第二微凸塊以及該些連接件電性連接至該基板，其中該些第一微凸塊的尺寸與該些第二微凸塊的尺寸相同。
  10. 如申請專利範圍第9項所述的晶片封裝結構的製作方法，其中配置該橋接元件於該些第一微凸塊上的步驟包括：提供一玻璃基板；形成一離型層於該玻璃基板上；形成該橋接元件於該離型層上；以及移除該離型層以及該玻璃基板，以將該橋接元件配置於該些第一微凸塊上。
  11. 如申請專利範圍第9項所述的晶片封裝結構的製作方法，其中該橋接元件與該基板分別位於該些晶片的相對兩側。
  12. 如申請專利範圍第9項所述的晶片封裝結構的製作方法，其中該些晶片的其中一該晶片的該主動表面與另一該晶片的該主動表面齊平。
  13. 如申請專利範圍第9項所述的晶片封裝結構的製作方法，其中該橋接元件包括至少一介電層、至少二個圖案化線路層以及至少一第一導電孔，該圖案化線路層與該介電層依序疊置於該些第一微凸塊上，該第一導電孔貫穿該介電層，且其中一該圖案化線路層透過該第一導電孔與另一該圖案化線路層電性連接。
  14. 如申請專利範圍第9項所述的晶片封裝結構的製作方法，其中形成該些連接件的方法包括：形成多個銅柱於該基板的第一表面，以使該些銅柱位於該些晶片的外圍。
  15. 如申請專利範圍第9項所述的晶片封裝結構的製作方法，其中形成該些連接件的方法包括：形成一連接結構於該基板上，以使該連接結構位於該些晶片的外圍，其中該連接結構包括：一第二接墊，配置於該基板的第一表面；一絕緣材料層，配置於該第二接墊上；一第三接墊，配置於該絕緣材料層上；以及一第二導電孔，貫穿該絕緣材料層，以電性連接該第二接墊與該第三接墊。
  16. 如申請專利範圍第9項所述的晶片封裝結構的製作方法，其中形成該些連接件的方法包括：形成一連接結構於該基板上，以使該連接結構位於該些晶片的外圍，其中該連接結構包括：一第二接墊，配置於該基板的第一表面；一導電件，配置於該第二接墊上；一第三接墊，配置於該導電件上；一絕緣材料層，配置於該第三接墊上；一第四接墊，配置於該絕緣材料層上；以及 一第二導電孔，貫穿該絕緣材料層，以電性連接該第三接墊與該第四接墊。
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