TWI597810B - 封裝 - Google Patents

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Publication number
TWI597810B
TWI597810B TW105103989A TW105103989A TWI597810B TW I597810 B TWI597810 B TW I597810B TW 105103989 A TW105103989 A TW 105103989A TW 105103989 A TW105103989 A TW 105103989A TW I597810 B TWI597810 B TW I597810B
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TW
Taiwan
Prior art keywords
corner
package
opening
lateral dimension
perforation
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Application number
TW105103989A
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English (en)
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TW201703215A (zh
Inventor
陳憲偉
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台灣積體電路製造股份有限公司
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Publication of TW201703215A publication Critical patent/TW201703215A/zh
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Publication of TWI597810B publication Critical patent/TWI597810B/zh

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Description

封裝
本揭露關於封裝，更特別關於封裝中不同位置的開口其橫向尺寸與比例。
隨著半導體技術進步，半導體晶片越來越小。在此同時，越來越多功能需整合至半導體晶粒中。綜上所述，半導體晶粒需包含更多I/O墊封裝至更小的面積中，且I/O墊密度隨著時間快速增加。如此一來，封裝半導體晶粒變得更困難，此不利於封裝良率。
習知封裝技術可分為兩類。第一類在切割晶圓上的晶粒前，先封裝晶粒。這種封裝技術的好處在於產量較大且成本較低。此外，這種封裝技術需要的底填物或成型化合物較少。然而，這種封裝技術具有某些缺點。由於晶粒的尺寸越來越小，且對應封裝只能是扇入型封裝，因此每一晶粒之I/O墊只能侷限於直接位於個別晶粒表面上的區域中。由於晶粒的面積有限，I/O墊的數目受限於I/O墊之間的必要間距。若I/O墊的間距縮的太小，可能發生焊料橋接。此外，在焊球尺寸固定的需求下，焊球必需具有一定的尺寸，此亦限制封裝至晶粒表面上的焊球數目。
在另一類封裝中，先自晶圓切割成晶粒後，再封裝晶粒。此類封裝技術的優點在於可形成扇出式封裝，即晶粒 上的I/O墊可重新佈線至比晶粒還大的面積上，因此封裝至晶粒表面上的I/O墊數目可因此增加。此類封裝技術的另一優點為只封裝良品晶粒(KGD)，而缺陷的晶粒將被丟棄。如此一來，不需浪費成本與精力在缺陷的晶粒上。
本揭露一實施例提供之封裝包括：裝置晶粒；成型材料，包覆裝置晶粒於其中；表面介電層，位於封裝的表面。角落的開口位於表面介電層中。角落的開口與封裝的角落相鄰。內部的開口位於表面介電層中。內部的開口比角落的開口遠離封裝的角落。角落的開口其第一橫向尺寸大於內部的開口其第二橫向尺寸。
本揭露一實施例提供之封裝包括：第一封裝與接合至第一封裝的第二封裝。第一封裝包括：裝置晶粒；成型材料，包覆裝置晶粒於其中；表面介電層，位於第一封裝的表面；以及角落的開口與內部的開口，位於表面介電層中。角落的開口與第一封裝的角落相鄰並具有第一橫向尺寸。內部的開口比角落的開口遠離第一封裝的角落，且內部的開口具有第二橫向尺寸。第二封裝包括：第一導電結構，具有第三橫向尺寸；第二導電結構，具有第四橫向尺寸。第一橫向尺寸與第三橫向尺寸之第一比例，大於第二橫向尺寸與第四橫向尺寸之第二比例。角落的焊料區接合至第一導電結構、延伸至角落的開口、並接觸第一導電結構。內部的焊料區接合至第二導電結構、延伸至內部的開口、並接觸第二導電結構。
本揭露一實施例提供之封裝包括：裝置晶粒；成 型材料，包覆裝置晶粒於其中；以及第一穿孔與第二穿孔，貫穿成型材料。第一穿孔其第一橫向尺寸大於第二穿孔其第二橫向尺寸。
EN1‧‧‧邊界
W1、W2、W3、W3A、W3B、W4、W5‧‧‧橫向尺寸
20、62‧‧‧載板
22‧‧‧離型層
24、28、46、52、56‧‧‧介電層
26、50、54‧‧‧RDL
30、48、58、66、66A、66A1、66A2、66B‧‧‧開口
32、32A、32B‧‧‧穿孔
36、204‧‧‧裝置晶粒
36A、100A‧‧‧角落
38‧‧‧金屬柱
40‧‧‧頂介電層
42‧‧‧鈍化層
44‧‧‧成型材料
45‧‧‧DAF
60‧‧‧電連接物
64‧‧‧黏合層
68、70、70A、70B、206‧‧‧焊料區
100、100’、200‧‧‧封裝
202‧‧‧封裝基板
208‧‧‧金屬墊
300‧‧‧流程
302、304、306、308、310、312、314、316‧‧‧步驟
第1至10、11A至11B、12至13、與14A圖係某些實施例中，封裝於製作過程中的中間階段剖視圖。
第14B圖係某些實施例中，封裝的上視圖。
第15A圖係另一實施例中，封裝的剖視圖。
第15B至15C圖係某些實施例中，封裝的上視圖。
第16圖係某些實施例中，形成封裝的流程圖。
下述內容提供的不同實施例可實施本揭露的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本揭露。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本揭露之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖 示中的方向。
多個實施例提供積體扇出式封裝，且下述內容討論這些實施例的變化。在圖式與實施例中，相同標號將用以標示類似單元。
第1至10、11A至11B、12至13、與14A圖係實施例中，封裝於製作過程中的中間階段剖視圖，其對應第16圖之流程300。在後續內容中，將搭配第16圖中的製程步驟說明第1至10、11A至11B、12至13、與14A圖。
如第1圖所示，離型層22形成於載板20上。載板20可為玻璃載板、陶瓷載板、或類似物。載板20可具有圓形的上視形狀，且可具有矽晶圓的尺寸。舉例來說，載板20可具有8吋直徑、12吋直徑、或類似尺寸。離型層22之組成可為高分子為主的材料如光熱轉換(LTHC)材料，其可與載板20一起自後續步驟形成之上方結構移除。在本揭露某些實施例中，離型層22之組成為環氧化合物為主的熱離型材料。在其他實施例中，離型層22之組成為紫外線(UV)膠。離型層22可以液態方式施加後固化。在其他實施例中，離型層22為壓合至載板20上的壓合膜。離型層22之上表面齊平，且具有高度共平面性。
介電層24形成於離型層22上。在本揭露某些實施例中，介電層24之組成為高分子，其可為光敏材料如聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)、或類似物，並可由光微影製程輕易地圖案化。在其他實施例中，介電層24之組成為氮化物如氮化矽，氧化物如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、或硼掺雜之磷矽酸鹽玻璃(BPSG)，或類似 物。
如第2圖所示，RDL(重新佈線)26係形成於介電層24上。此步驟亦圖示於第16圖中的流程其步驟302。RDL 26亦稱作背側RDL，因為其位於裝置晶粒36之背側上(見第5圖)。形成RDL 26之步驟可包含形成晶種層(未圖示)於介電層24上、形成圖案化的遮罩(未圖示)如光阻於晶種層上、以及接著鍍製金屬於露出的晶種層上。接著移除圖案化的遮罩與其覆蓋的部份晶種層，以保留RDL 26如第2圖所示。在本揭露某些實施例中，晶種層包含鈦層與鈦層上的銅層。舉例來說，晶種層的形成方法可為物理氣相沉積(PVD)。舉例來說，鍍製金屬的步驟可採用無電鍍製法。
如第3圖所示，形成介電層28於RDL 26上。介電層28之下表面可接觸RDL 26與介電層24之上表面。在本揭露某些實施例中，介電層28之組成為高分子，其可為光敏材料如PBO、聚醯亞胺、BCB、或類似物。在其他實施例中，介電層28之組成為氮化物如氮化矽，氧化物如氧化矽、PSG、BSG、或BPSG，或類似物。接著圖案化介電層28以形成開口30於其中。因此，介電層28中的開口30將露出某些部份的RDL 26。
如第4圖所示，形成金屬柱。在下述內容中，金屬柱將貫穿後續形成的成型材料，因此其又稱作穿孔32(如32A與32B)。在本揭露某些實施例中，穿孔32的形成方法為鍍製法。此步驟亦圖示於第16圖中的流程其步驟304。穿孔32用以使穿孔32之相反兩側上的結構電性內耦接。鍍製穿孔32之步驟可包含毯覆性地形成晶種層(未圖示)於介電層28上，且晶種層 延伸至開口30中。接著形成光阻(未圖示)並圖案化光阻，並鍍製穿孔32於光阻中的開口所露出的部份晶種層上。接著移除光阻與其覆蓋的部份晶種層。穿孔32之材料可包含銅、鋁、或類似物。穿孔32可為棒狀。穿孔32之上視形狀可為圓形、矩形、方形、六角形、或類似形狀。在本揭露某些實施例中，穿孔32排列成環(第4圖中的結構其上視圖)以包圍一區域，且此區域係用以放置裝置晶粒36(見第5圖)。穿孔32A與32B之上視形狀可為圓形、六角形、橢圓形、方形、或類似形狀。
在下述內容中，穿孔32A將稱作角落的穿孔，而穿孔32B將稱作內部的穿孔。在本揭露某些實施例中，穿孔32A與穿孔32B具有相同的上視形狀與上視尺寸。在本揭露其他實施例中，穿孔32A與穿孔32B具有不同的上視形狀及/或上視尺寸。
如第5圖所示，放置裝置晶粒36。此步驟亦圖示於第16圖中的流程其步驟306。裝置晶粒36經由DAF(晶粒貼附膜)45黏合至介電層28，且DAF 45為黏合膜。裝置晶粒36可為邏輯裝置晶粒，其包含邏輯電晶體於其中。在某些實施例中，裝置晶粒36係設計以用於可攜設備之晶粒，比如電源管理積體電路(PMIC)晶粒、無線電收發器(TRX)晶粒、或類似晶粒。雖然圖式中只放置一個裝置晶粒36，但可依需要放置更多裝置晶粒於介電層28上。
在某些實施例中，可先形成金屬柱38(如銅柱)作為裝置晶粒36的頂部，其中金屬柱38電性耦接至裝置晶粒36中的積體電路裝置如電晶體(未圖示)。在本揭露某些實施例中， 高分子填入相鄰之金屬柱38之間的間隙，以形成頂介電層40。頂介電層40亦可位於鈍化層42之頂部上並與其接觸。在本揭露某些實施例中，頂介電層40之組成可為PBO。鈍化層42之組成可為氮化矽、氮氧化矽、氧化矽、或上述之多層結構。
接著可將成型材料44成型於裝置晶粒36上。成型材料44將填入相鄰之穿孔32之間的間隙，並填入穿孔32與裝置晶粒36之間的間隙。成型材料44可包含成型化合物、成型底填物、環氧化合物、及/或樹脂。成型材料44之上表面高於金屬柱38之頂端。
在後續步驟中，進行平坦化製程如化學機械拋光(CMP)步驟或研磨步驟以薄化成型材料44，直到露出穿孔32與金屬柱38。此步驟亦圖示於第16圖中的流程其步驟308。由於研磨步驟，穿孔32之頂端與金屬柱38之上表面實質上齊平(共平面)，並與成型材料44之上表面實質上共平面。
第6至10圖係前側的RDL與個別的介電層之形成步驟。此步驟亦圖示於第16圖中的流程其步驟310。如第6圖所示，形成介電層46。在本揭露某些實施例中，介電層46之組成為高分子如PBO、聚醯亞胺、或類似物。在其他實施例中，介電層46之組成為氮化矽、氧化矽、或類似物。開口48形成於介電層46中，以露出穿孔32與金屬柱38。開口48之形成方法可為光微影製程。
接著如第7圖所示，形成RDL 50以連接至金屬柱38與穿孔32。RDL 50亦可使金屬柱38與穿孔32內連線。RDL 50包含介電層46上的金屬線路，以及延伸至介電層46中的通孔。 RDL 50中的通孔連接至穿孔32與金屬柱38。在本揭露某些實施例中，RDL 50之形成方法為鍍製製程，其中每一RDL 50包含晶種層(未圖示)，以及晶種層上的鍍製金屬化材料。晶種層與鍍製材料的組成可相同或不同。
如第8圖所示之某些實施例，形成介電層52於第7圖中的結構上。接著形成RDL 54於介電層52中，如第9圖所示。在本揭露某些實施例中，形成RDL 54的方法包含毯覆性地形成銅晶種層。接著形成遮罩層於毯覆性的銅晶種層上並圖案化遮罩層，再進行鍍製步驟以形成RDL 54。之後移除遮罩層，並進行蝕刻步驟移除RDL 54未覆蓋的部份銅晶種層。RDL 54之組成可為金屬或合金，其包含鋁、銅、鎢、及/或上述之合金。
第8與9圖顯示某些實施例形成RDL 54的步驟。其他實施例可具有超過一組的RDL 54，端視個別封裝的布線需求而定。這些實施例中的介電層52可包含高分子如PBO、聚醯亞胺、BCB、或類似物。在其他實施例中，介電層52之組成可包含非有機的介電材料如氧化矽、氮化矽、碳化矽、氮氧化矽、或類似物。
第10與11A圖顯示某些實施例形成介電層56與電連接物60的步驟。此步驟亦圖示於第16圖中的流程其步驟312。如第10圖所示，形成介電層56。舉例來說，介電層56可為PBO、聚醯亞胺、或BCB。形成開口58於介電層56中，以露出下方之金屬墊，且金屬墊係部份的RDL 54。接著形成電連接物60，如第11A圖所示。在某些實施例中，可形成UBM(凸塊下金屬化物，未圖示)延伸至開口58中。電連接物60之形成方 法可包含將焊球置於UBM其露出部份上，並使焊球再流動。在其他實施例中，電連接物60之形成方法包含鍍製形成焊料區於RDL 54中露出的金屬墊上，接著使焊料區再流動。電連接物60亦可包含金屬柱，或金屬柱與焊料蓋，且其形成方法亦可為鍍製法。在說明書中，包含介電層24之結構與上方結構之組合可稱作封裝100，其為複合晶圓。
在其他實施例中，封裝100之剖視圖如第11B圖所示。在這些實施例中，省略第2與3圖之製程步驟。如此一來，第11B圖中不具有背側的RDL。自介電層24形成穿孔32。成型材料44與DAF 45亦貼合至介電層24。
第12、13、與14A圖係形成封裝的其餘製程，且這些製程係由第11B圖所示之結構繼續進行。首先，封裝100自第11B圖之載板20分開，且分開方法可為以紫外光或雷射照射離型層22，使離型層22因UV光或雷射產生的熱分解。分開步驟後的結構如第12圖所示。接著以黏合層64黏合封裝100與載板62，其中電連接物60可朝向或接觸黏合層64。在本揭露某些實施例中，可在分離載板20之前，先貼合載板62與封裝100。
如第12圖所示，移除某些部份的介電層24，以露出穿孔32。如此一來，形成開口66於介電層24中。此步驟亦圖示於第16圖中的流程其步驟314。開口66之形成方法可為雷射燃燒。另一方面，當介電層24之組成為光敏材料如PBO或聚醯亞胺時，開口66之形成方法亦可為蝕刻。開口66包含角落的穿孔32A上之角落的開口66A，以及內部的穿孔32B上之內部的開口66B。
第13圖顯示某些實施例中，焊料區68(有時稱作預焊料區)之形成步驟。舉例來說，可將焊料漿料印刷於開口66中，以形成焊料區68。在其他實施例中，並無預焊料區形成於開口66中。接著可將封裝100(複合晶圓)切割成多個封裝100’，各自具有結構如第13圖所示。
第13圖所示之封裝200又稱作頂部封裝。如第14A圖所示，封裝200接合至封裝100’。此步驟亦圖示於第16圖中的流程其步驟316。在本揭露某些實施例中，封裝200包含封裝基板202，且裝置晶粒204接合至封裝基板202。將裝置晶粒204接合至封裝基板202的方法可為打線接合、覆晶接合、或類似方法。第13圖所示之焊料區206與焊料區68再流動後形成焊料區70，以接合封裝200與封裝100’。在某些實施例中，在接合封裝200後，可將底填物(未圖示)填入封裝100’與封裝200之間的間隙。
第14B圖係第14A圖所示之封裝的上視圖，其中上視圖沿著第13圖之開口66的高度，即第14A圖中的焊料區70所在處。如第14B圖所示，開口66包含角落的開口66A(如66A1)，其最靠近封裝100之角落100A。最靠近每一角落100A之角落的開口66A其數目可為1、2、或3，端視焊料區70承受的應力而定。開口66亦包含角落的開口66A2，其最靠近裝置晶粒36之角落36A。其餘非角落的開口66A之開口66，即內部的開口66B。
在本揭露某些實施例中，角落的開口66A之面積與橫向尺寸W1大於內部的開口66B之面積與橫向尺寸W2。在說明書中，開口66之最大橫向尺寸標示為W1、W2、W3、W4、 與W5，如第14A與14B圖所示。當個別結構之上視形狀為圓形時，橫向尺寸W1至W5即直徑。角落的焊料區70A(見第14A圖)與下方之角落的穿孔32A之間的界面面積，大於內部的焊料區70B與下方之內部的穿孔32B之間的界面面積。由於角落的焊料區70A比內部的焊料區70B承受更高的應力，角落的焊料區70A與角落的穿孔32A之間更容易發生碎裂。藉由使角落的焊料區70A與角落的穿孔32A之間的界面面積，大於內部的焊料區70B與內部的穿孔32B之間的界面面積，可降低角落的焊料區70A所承受的應力，並改善個別封裝的可靠度。
如第14B圖所示，橫向尺寸W1/橫向尺寸W2的比例介於約1.1至約1.5之間。此外如第14A圖所示，焊料區70接觸封裝200中的金屬墊208之接觸區域具有橫向尺寸W3，即露出的金屬墊208之橫向尺寸。在某些實施例中，橫向尺寸W2/橫向尺寸W3的比例小於或等於0.8，且可介於約0.7至0.8之間。橫向尺寸W1/橫向尺寸W3的比例大於橫向尺寸W2/橫向尺寸W3的比例。舉例來說，橫向尺寸W1/橫向尺寸W3的比例可大於0.8，且可介於約0.9至1.3之間。在某些實施例中，封裝200上的所有橫向尺寸W3可相同。
為確保在形成開口66(見第12圖)時不會露出成型材料44，需在開口66的所有側邊保留邊界EN1。當個別開口66對準下方穿孔32時，開口其每一側的邊界EN1的範圍界於約10μm至約30μm之間。在角落的開口66A大於內部的開口66B之實施例中，角落的穿孔32A其橫向尺寸W1大於內部的穿孔32A之橫向尺寸W2，以確保角落的開口66A具有足夠的邊界。舉例 來說，橫向尺寸W5可為2×EN1+(0.7~0.8)×W3B，而橫向尺寸W4可為2×EN1+(0.9~1.3)×W3A。穿孔32A之橫向尺寸W1亦可大於橫向尺寸W2，使角落的開口66A具有足夠的邊界EN1。
如第14B圖所示，角落的開口66A2中的焊料區所承受的應力，大於內部的開口66B中內部的焊料區70B所承受的應力。此外，角落的開口66A2中的焊料區所承受的應力，可小於角落的開口66A1中的焊料區所承受的應力。綜上所述，角落的開口66A2之橫向尺寸W1大於內部的開口66B之橫向尺寸W2，且可小於角落的開口66A1之橫向尺寸(亦標示為W1)。
在其他實施例中，角落的開口66A之橫向尺寸W1設計為與內部的開口66B之橫向尺寸W2相同。另一方面，對應角落的開口66A之金屬墊208的橫向尺寸W3A(見第14A圖)，縮小至小於對應內部的開口66B之金屬墊208的橫向尺寸W3B。如此一來，橫向尺寸W1/橫向尺寸W3A的比例仍大於橫向尺寸W2/橫向尺寸W3B的比例。在橫向尺寸W1大於橫向尺寸W2的這些實施例中，橫向尺寸W1/橫向尺寸W3的比例與橫向尺寸W2/橫向尺寸W3的比例可為相同範圍。藉由縮小橫向尺寸W3A，角落的焊料區70A所承受的應力可重新分佈，且某些角落的焊料區70A所承受的某些應力，將由其與穿孔32A之間的界面重新分佈至其與金屬墊208之間的界面，進而減少焊料區70A碎裂的問題。
如第14A圖所示，本揭露的某些實施例其焊料區70A的焊料體積，與焊料區70B的焊料體積相同。在本揭露其他實施例中，焊料區70A的焊料體積大於焊料區70B的焊料體 積，比如橫向尺寸W1大於橫向尺寸W2。
第15A圖係本揭露其他實施例的封裝。除了特別說明的部份以外，這些實施例的構件材料與形成方法基本上與前述類似，並採用與第12、13、與14A圖中相同的標號標示類似單元。關於第15A圖中構件之形成製程與材料的細節可參考第12、13、與14A圖中的實施例。此實施例之製程延續第11A圖中的結構，其與第11B圖之差別在於第11A圖中的結構包含介電層28、RDL 26、與介電層28中的通孔。
如第15A圖所示，焊料區70A與70B分別位於角落的開口66A與內部的開口66B中，可用以接合封裝200與封裝100’。第15B圖係角落的開口66A與內部的開口66B之上視圖，基本上與第14B圖相同。第15C圖係其他實施例中，角落的開口66A與內部的開口66B之上視圖。在這些實施例中，開口66分佈如全陣列。如此一來，第15C圖所示之實施例將不具有第14B圖中的角落開口66A2。
在本揭露某些實施例中，第13、14A、與14B圖中的實施例所考慮的橫向尺寸W1、W2、W3、W4、與W5、橫向尺寸W1/橫向尺寸W3的比例、橫向尺寸W2/橫向尺寸W3的比例、與邊界EN1同樣適用於第15A、15B、與15C圖所示之實施例，在此不贅述。
本揭露之實施例的優點如下。藉由調整橫向尺寸、面積、及/或橫向尺寸W1/橫向尺寸W3的比例與橫向尺寸W2/橫向尺寸W3的比例，可將施加於角落的焊料區之高應力重新分佈，以強化封裝其脆弱的部份，進而改良封裝的可靠性。
在本揭露某些實施例中，封裝包括：裝置晶粒；成型材料，包覆裝置晶粒於其中；表面介電層，位於封裝的表面。角落的開口位於表面介電層中。角落的開口與封裝的角落相鄰。內部的開口位於表面介電層中。內部的開口比角落的開口遠離封裝的角落。角落的開口其第一橫向尺寸大於內部的開口其第二橫向尺寸。
在本揭露其他實施例中，封裝包括：第一封裝與接合至第一封裝的第二封裝。第一封裝包括：裝置晶粒；成型材料，包覆裝置晶粒於其中；表面介電層，位於第一封裝的表面；以及角落的開口與內部的開口，位於表面介電層中。角落的開口與第一封裝的角落相鄰並具有第一橫向尺寸。內部的開口比角落的開口遠離第一封裝的角落，且內部的開口具有第二橫向尺寸。第二封裝包括：第一導電結構，具有第三橫向尺寸；第二導電結構，具有第四橫向尺寸。第一橫向尺寸與第三橫向尺寸之第一比例，大於第二橫向尺寸與第四橫向尺寸之第二比例。角落的焊料區接合至第一導電結構、延伸至角落的開口、並接觸第一導電結構。內部的焊料區接合至第二導電結構、延伸至內部的開口、並接觸第二導電結構。
在本揭露其他實施例中，封裝包括：裝置晶粒；成型材料，包覆裝置晶粒於其中；以及第一穿孔與第二穿孔，貫穿成型材料。第一穿孔其第一橫向尺寸大於第二穿孔其第二橫向尺寸。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本揭露。本技術領域中具有通常知識者應理解可採 用本揭露作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本揭露精神與範疇，並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
EN1‧‧‧邊界
W1、W2、W3、W3A、W3B、W4、W5‧‧‧橫向尺寸
24、46、52、56‧‧‧介電層
32、32A、32B‧‧‧穿孔
36‧‧‧裝置晶粒
38‧‧‧金屬柱
40‧‧‧頂介電層
42‧‧‧鈍化層
44‧‧‧成型材料
45‧‧‧DAF
60‧‧‧電連接物
66、66A、66B‧‧‧開口
70、70A、70B‧‧‧焊料區
100’、200‧‧‧封裝
208‧‧‧金屬墊

Claims (14)

  1. 一種封裝，包括：一第一封裝，包括：一裝置晶粒；一成型材料，包覆該裝置晶粒於其中；一表面介電層，位於該第一封裝的表面；一角落的開口，位於該表面介電層中，其中該角落的開口與該第一封裝的角落相鄰；一內部的開口，位於該表面介電層中，其中該內部的開口比該角落的開口遠離該第一封裝的角落，且該角落的開口其第一橫向尺寸大於該內部的開口其第二橫向尺寸；一角落的焊料區，延伸至該角落的開口中；以及一內部的焊料區，延伸至該內部的開口中。
  2. 如申請專利範圍第1項所述之封裝，更包括一第二封裝，且該第二封裝包括：一第一導電結構，接合至該角落的焊料區；以及一第二導電結構，接合至該內部的焊料區；其中該第一橫向尺寸與該第一導電結構的橫向尺寸之第一比例，大於該第二橫向尺寸與該第二導電結構的橫向尺寸之第二比例。
  3. 如申請專利範圍第1項所述之封裝，其中該第一封裝更包括：一角落的穿孔，貫穿該成型材料，其中該角落的穿孔接觸該角落的焊料區；以及一內部的穿孔，貫穿該成型材料，其中該內部的穿孔接觸 該內部的焊料區。
  4. 如申請專利範圍第1項所述之封裝，更包括：一角落的穿孔，貫穿該成型材料，其中該角落的開口露出該角落的穿孔之上表面；以及一內部的穿孔，貫穿該成型材料，其中該內部的開口露出該內部的穿孔之上表面，且該角落的穿孔之橫向尺寸大於該內部的穿孔之橫向尺寸。
  5. 如申請專利範圍第1項所述之封裝，其中該角落的開口之第一面積大於該內部的開口之第二面積。
  6. 如申請專利範圍第1項所述之封裝，更包括一額外之角落的開口於該表面介電層中，其中該額外之角落的開口比位於該表面介電層中的其他開口更靠近該裝置晶粒的角落，且該額外之角落的開口其第三橫向尺寸大於該內部的開口其第二橫向尺寸。
  7. 一種封裝，包括：一第一封裝，包括：一裝置晶粒；一成型材料，包覆該裝置晶粒於其中；一表面介電層，位於該第一封裝的表面；一角落的開口，位於該表面介電層中，其中該角落的開口與該第一封裝的角落相鄰並具有一第一橫向尺寸；一內部的開口，位於該表面介電層中，其中該內部的開口比該角落的開口遠離該第一封裝的角落，且該內部的開口具有一第二橫向尺寸；以及 一第二封裝，包括：一第一導電結構，具有一第三橫向尺寸；一第二導電結構，具有一第四橫向尺寸，其中該第一橫向尺寸與該第三橫向尺寸之第一比例，大於該第二橫向尺寸與該第四橫向尺寸之第二比例；一角落的焊料區，接合至該第一導電結構、延伸至該角落的開口、並接觸該第一導電結構；以及一內部的焊料區，接合至該第二導電結構、延伸至該內部的開口、並接觸該第二導電結構。
  8. 如申請專利範圍第7項所述之封裝，其中該角落的開口其第一面積大於該內部的開口其第二面積。
  9. 如申請專利範圍第7項所述之封裝，其中該第一比例介於約0.9至約1.3之間，而該第二比例介於約0.7至約0.8之間。
  10. 如申請專利範圍第7項所述之封裝，更包括：一角落的穿孔，貫穿該成型材料，其中該角落的開口露出該角落的穿孔之上表面；以及一內部的穿孔，貫穿該成型材料，其中該內部的開口露出該內部的穿孔之上表面，且其中該角落的穿孔其橫向尺寸大於該內部的穿孔其橫向尺寸。
  11. 一種封裝，包括：一裝置晶粒；一成型材料，包覆該裝置晶粒於其中；以及一第一穿孔與一第二穿孔，貫穿該成型材料，其中該第一穿孔其第一橫向尺寸大於該第二穿孔其第二橫向尺寸。
  12. 如申請專利範圍第11項所述之封裝，其中該第一橫向尺寸與該第二橫向尺寸之比例大於約1.1。
  13. 如申請專利範圍第11項所述之封裝，其中該第一穿孔係與該封裝之角落相鄰之角落的穿孔，而該第二穿孔係比該角落的穿孔遠離該封裝之角落的內部的穿孔。
  14. 如申請專利範圍第11項所述之封裝，其中該第一穿孔係與該裝置晶粒之角落相鄰之角落的穿孔，而該第二穿孔係比該角落的穿孔遠離該裝置晶粒之角落的內部的穿孔。
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