CN114765162A - 具有锥形金属涂层侧壁的半导体装置 - Google Patents

具有锥形金属涂层侧壁的半导体装置 Download PDF

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Publication number
CN114765162A
CN114765162A CN202111624115.4A CN202111624115A CN114765162A CN 114765162 A CN114765162 A CN 114765162A CN 202111624115 A CN202111624115 A CN 202111624115A CN 114765162 A CN114765162 A CN 114765162A
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China
Prior art keywords
sidewall
metal coating
semiconductor
bottom side
semiconductor device
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CN202111624115.4A
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English (en)
Inventor
野口友子
升本睦
青屋建吾
松浦正光
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN114765162A publication Critical patent/CN114765162A/zh
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Abstract

一种半导体装置包含具有顶侧(102a)表面、底侧(102b)表面及介于所述顶侧表面与所述底侧表面之间的侧壁表面(102c)的半导体裸片(102)，所述顶侧(102a)表面包括在其中包含电路(180)的具有连接到所述电路中的节点的接合垫(103)的半导体材料。包含底侧金属层的金属涂层(108)在所述底侧表面上方，连续延伸到所述侧壁表面上的侧壁金属层。所述侧壁金属层界定相对于从由所述底侧金属层界定的底平面投影的法线成从10°到60°的角度的侧壁平面(108a)。

Description

具有锥形金属涂层侧壁的半导体装置
技术领域
本公开涉及半导体装置，更具体来说，涉及用于保护半导体装置上的电路使其免于暴露于电磁辐射(例如红外线辐射(IR))的结构。
背景技术
在半导体装置组装制造期间，在从晶片单切之后，半导体芯片(通常被称为“裸片”或“半导体裸片”)通常被安装到引线框架上且经线接合、夹持或以其它方式耦合(例如，倒装芯片安装)到引线框架的引线。接着，引线框架组合件上的此半导体裸片通常被覆盖在模塑化合物(例如，包括环氧树脂)中以保护半导体装置使其免受潜在破坏热、物理创伤、湿气及其它可能有害因素影响。完成的组合件通常被称为半导体封装，或更简单地被称为封装。
存在其它类型的封装，例如芯片规模封装(CSP)，其可被视为未封装半导体裸片，这是因为CSP通常不包含覆盖半导体裸片的模塑化合物。实情是，在许多此类CSP中，导电端子(例如，焊料球)形成在半导体裸片的有源顶侧表面上的接合垫上，且接着将裸片倒装到应用上，例如到印刷电路板(PCB)的金属垫上。因此，裸片的非有源底侧表面及非有源侧壁表面暴露于环境。半导体裸片的这些非有源表面可为裸片的有源(顶侧)区域及其它电连接提供一些部分屏蔽使其免受有害影响。与常规封装相比，此类CSP(例如，晶片级CSP(WL-CSP或WCSP))可因其小尺寸及降低的制造成本而受到青睐。
然而，一些未封装裸片(例如CSP)在被保护免受某些波长范围的电磁辐射影响(例如被保护免受环境光中存在的IR影响)的应用环境中操作最佳，这是因为裸片的半导体材料可能无法充分阻挡某些范围的电磁辐射的传输。例如，可期望屏蔽半导体裸片使其免受开始IR的具有大于700nm的波长的电磁辐射(红光)影响，其中IR的短波长部分被称为近IR，其延伸到约2μm，尽管通常在光学件中定义的IR在波长上从近红外延伸到约1mm。由于此IR由常见的IC衬底材料(例如硅)透射，所以IR能够从裸片表面穿透衬底到达半导体(pn)结。此穿透电磁辐射将能量赋予到pn结中，这会引起不想要的载流子产生，且因此在半导体裸片的电路中引起电流流动(这可被称为漂移电流)，这可导致使其性能受影响的裸片(通常被称为光敏裸片)。
通过将半导体裸片放置在阻挡光透射的额外外壳内，通常足以保护半导体裸片免受IR及其它电磁辐射影响。然而，一些电子系统需要未封装半导体裸片来在以下条件下操作，例如当半导体裸片安装在PCB上时，这使裸片暴露于包含IR的环境电磁辐射以及也可安装在PCB上的其它可能光源。例如，此类电子系统可包括蜂窝电话、寻呼机及个人数字助理(PDA)，其通常可包含例如发光二极管(LED)或背光的IR源。应屏蔽此未封装半导体裸片使其免受这些IR源影响以便在这些环境中适当地操作。常规地，将有机材料(例如，环氧树脂)层施覆到未封装半导体裸片(例如，WCSP)的侧壁表面及底表面以尝试阻挡IR的透射到达半导体裸片的电路。
发明内容
提供本发明内容以依简化形式介绍所公开概念的简要选择，下文在包含所提供图示的具体实施方式中进一步描述这些概念。本发明内容不希望限制所主张标的物的范围。
所主张方面包含一种半导体装置，其包括具有顶侧表面、底侧表面及介于所述顶侧表面与所述底侧表面之间的侧壁表面的半导体裸片，所述顶侧表面包括在其中包含电路的具有连接到所述电路中的节点的接合垫的半导体材料。金属涂层包含在所述底侧表面上方连续延伸到所述侧壁表面上的侧壁金属层的底侧金属层。所述侧壁金属层界定相对于从由所述底侧金属层界定的底平面投影的法线成从10°到60°的角度的侧壁平面。
所主张方面还包含组装方法，其包括形成具有锥形侧壁(通常各自位于不同平面中的四个侧壁)的半导体裸片的所公开晶片切割工艺，其中每一侧壁表面包含锥形切割(例如，例如通过锥形刀片)，其中所述切割工艺从所述晶片的所述底侧开始。或者，可在所述半导体裸片中的单切者上方形成模塑化合物，其中所述模塑化合物可经配置以提供所述锥形侧壁，其中所述金属涂层形成于所述模塑化合物的顶部上，且因此呈现所述模塑化合物的锥形侧壁的锥形。
附图说明
现将参考附图，其不一定按比例绘制，其中：
图1A到D是根据实例的从通过实例展示为具有多个CSP的CSP晶片的晶片开始的连续横截面视图，所述多个CSP各自包括在对应于用于形成具有锥形侧壁与在底侧及侧壁表面上的金属涂层的未封装半导体裸片的实例方法的各个步骤之后的半导体裸片。图1A展示具有介于CSP之间的切割道的CSP晶片，其中CSP晶片顶(有源)侧朝下安装在切割带上。图1B展示在通过实例展示为使用锥形角刀片的机械锯切的晶片切割之后的结果。可见在邻近裸片之间的切割提供约60°的角度。图1C展示在沉积涂布裸片的底侧表面以及侧壁表面的毯覆金属涂层之后的结果。图1D展示在通常包括在邻近CSP之间使金属涂层机械地断裂的晶片的单切之后的单个单切CSP。
图2A到2E是根据实例的从通过实例展示具有在对应于用于使用阶梯切割形成具有锥形侧壁的未封装半导体裸片的实例方法的各个步骤之后的多个CSP的晶片开始的连续横截面视图，其中金属涂层在底侧表面及侧壁表面上。
图3A到3E是根据实例的实例模塑封装工艺流程的连续横截面视图，其中在各个步骤之后，在引线框架上存在半导体裸片。
图4A到4D是根据实例的利用使用衬底BGA的单个切割的实例模塑封装工艺流程的连续横截面视图，其中在衬底BGA上存在半导体裸片。
图5A到5E是根据实例的利用使用衬底BGA的阶梯切割，其中在第二切割之后形成金属涂层的实例模塑封装工艺流程的连续横截面视图，其中在衬底BGA上存在半导体裸片。
图6A到6E是根据实例的利用使用衬底BGA的阶梯切割，在第二切割之前具有金属涂层的实例模塑封装工艺流程的连续横截面视图，其中在衬底BGA上存在半导体裸片。
图7A描绘具有所公开金属涂层的实例半导体封装的横截面视图。图7B描绘具有所公开金属涂层的半导体封装的剖面图。图7C描绘具有所公开金属涂层的半导体封装的自上而下视图。图7D描绘具有所公开金属涂层的半导体封装的透视图。
图8A到8D展示分别具有图7A到7D中展示的所公开金属涂层的半导体封装，其现在金属涂层下方具有经添加电介质层。
图9是根据实例的安装在引线框架上的包含所揭示CSP且包含囊封模塑化合物的倒装芯片封装的横截面视图，所述CSP具有锥形侧壁及在侧壁表面上的金属涂层。
图10A是根据实例的线接合封装的横截面视图，其包含倒装芯片安装在引线框架上的CSP，包含提供锥形的囊封模塑化合物及通过形成于锥形模塑化合物上方(包含在侧壁表面的顶部上及底侧表面上)而呈锥形的金属涂层。
图10B是根据实例的线接合封装的横截面视图，其包含安装在引线框架的裸片垫上的CSP，包含提供锥形的囊封模塑化合物及通过在模塑化合物上方(在侧壁表面及底侧表面上方)而呈锥形的金属涂层。
具体实施方式
参考图示描述实例，其中相同元件符号用于指定类似或等效元件。动作或事件的所说明顺序不应被视为限制性，这是因为一些动作或事件可以不同顺序发生及/或与其它动作或事件同时发生。此外，根据本公开实施方法论可能不需要一些所说明动作或事件。
此外，如本文中使用的无进一步限定的术语“耦合到”或“与…耦合”(及类似者)希望描述间接或直接电连接。因此，如果第一装置“耦合”到第二装置，那么连接可为通过其中在路径中仅存在寄生现象的直接电连接，或通过经由包含其它装置及连接的中介物件的间接电连接。针对间接耦合，中介物件通常不修改信号的信息但可调整其电流电平、电压电平及/或功率电平。
所公开方面认识到用于在半导体裸片之间的切割道中切穿晶片的厚度以产生个别(经模拟)半导体裸片的常规晶片单切工艺(例如，使用机械锯或用于激光钻孔的激光器)导致具有四个基本上笔直侧壁表面的半导体裸片。如本文中使用的笔直表面意指侧壁相对于由半导体裸片的顶侧(有源)表面界定的平面及由底侧表面界定的平面形成90°角。邻近半导体裸片之间的晶片的切割道中的切割区域通常是窄的，例如5μm到100μm宽。因此，针对常规晶片，在单切(其通常遵循晶片背研磨工艺)时的厚度为约100μm(当背研磨时)到800μm(当未背研磨时)，使得在切割区域中存在高纵横比体积，例如，约60的纵横比。
针对包含将金属涂层沉积在晶片单切之后同时仍固定到粘着剂层(例如，到切割带或其它晶片固定设备)的未封装半导体裸片上的步骤的组装工艺，因此，存在在邻近半导体裸片之间具有基本上笔直侧壁以填充的高纵横比体积。笔直侧壁使得已知沉积系统(例如，溅镀系统)实际上不可能在半导体裸片的侧壁表面沿其整个长度均匀地涂布金属涂层。薄金属涂层或根本没有涂层可存在于带上与半导体裸片的侧壁表面界面处及附近，这是因为其为距离由溅镀沉积系统提供的溅镀材料最远的表面区域。
因此，由所公开方面认识到的问题是在对于可为光敏的半导体裸片的晶片切割之后最接近带的侧壁表面附近的半导体裸片的侧壁表面上的不良金属涂层覆盖范围，其中半导体裸片包含在将晶片切割(单切)成个别裸片之后施覆在其上的金属涂层。在晶片在于带上顶(有源)侧朝下时被切割的情况中，正是邻近顶侧表面的侧壁表面可具有相对薄的金属涂层，或可能根本没有金属涂层。由于上述高纵横比体积无法通过已知金属涂层沉积工艺(例如，沉积技术，例如溅镀或喷涂工艺)适当地填充，所以在光敏未封装半导体裸片的情况中，半导体裸片的侧壁上的此常规不良金属涂层阶梯覆盖范围可促使使用相对高成本的IR保护封装或其它布置(例如，金属罐、金属膏涂层、模塑环氧树脂涂层)。
在提供IR保护封装中涉及的额外步骤导致更高成本的封装，且还导致更复杂的组装工艺流程。此高纵横比金属涂层填充问题通过所公开方面解决，所述方面提供一种半导体装置，其包含包含于至少侧壁表面上的耐光的金属涂层，其中金属涂层界定相对于从由底侧金属层界定的底平面投影的法线成一个角度的侧壁平面。一个所公开方面包括一种半导体装置，其包含具有顶侧表面、底侧表面及介于所述顶侧表面与所述底侧表面之间的侧壁表面的半导体裸片，所述顶侧表面包括在其中包含电路的具有连接到所述电路中的节点的接合垫的半导体材料。金属涂层包含在所述底侧表面上方连续延伸到所述侧壁表面上的侧壁金属层的底侧金属层。
所述侧壁金属层界定相对于从由所述底侧金属层界定的底平面投影的法线成从10°到60°的角度的侧壁平面。下文描述的图1D展示此角度为θ。关于如本文中定义的θ，常规笔直(垂直)侧壁针对其θ将成0°。小于10°的θ在本文中被认为使得已知沉积系统(例如，溅镀系统)实际上不可能在半导体裸片的侧壁表面沿其整个长度均匀地涂布金属涂层。90°的θ将导致切割区域成为整个裸片，且大于60°的θ虽然实现侧壁上的金属涂层的经改进厚度均匀性，但将导致切割区域浪费太多面积(相对于电路，这将需要切割区域由电路设计师设计成专用于切割道中)以致经济上不合理。成从10°到60°的角度的所公开锥形侧壁可任选地提供于整个侧壁区域上方。
因此，所公开方面解决可能对倒装芯片裸片或CSP造成更严重问题的问题，其中电磁辐射(尤其是IR)可通过通常包括硅的裸片的衬底透射，使得IR可到达结区域，从而导致载流子产生。因此，此载流子产生可影响有源电路的操作。所公开方面通过通常在底侧表面上方且在侧壁表面上方添加金属涂层而帮助防止包含IR的电磁辐射入射在裸片的底侧表面及侧壁表面上的影响。所公开方面虽然通常是相对于CSP(例如，WCSP)描述，但通常适用于任何类型的封装、裸的裸片或具有/不具有模塑囊封的裸片。所公开方面可通常适用于具有光学敏感性(例如对电磁频谱的IR、mmWave或微波范围中的电磁辐射的敏感性)的任何IC装置。当提供模塑化合物时，锥形金属涂层可在模塑化合物下方或可在模塑化合物上方。
图1A到D是从通过实例展示具有多个半导体裸片102的CSP晶片110开始的连续横截面视图，其中切割道111被展示为介于被展示为CSP 100的裸片之间。CSP 100包括在对应于用于形成未封装半导体裸片的实例方法的各个步骤之后展示的半导体裸片102，所述半导体裸片102具有锥形侧壁及在底侧表面102b及被展示为102c的侧壁表面上的金属涂层108。
CSP 100每一者包含顶侧结构，所述顶侧结构包括被展示为在钝化层109的顶部上的电介质层1 113的第一电介质层，所述钝化层109具有暴露半导体裸片102的接合垫103的孔隙。例如包括铜的重布层(RDL)107在电介质层1 113上方，其中RDL 107通过电介质层1113中的孔隙与接合垫103进行电接触。被展示为电介质层2 114的任选第二电介质层在RDL107上方。还存在与RDL 107进行电接触的凸块下金属化(UBM)118的层，且在UBM 118上存在焊料球104。虽然未展示，但除了包括所展示的顶部结构的RDL外，CSP 100还可利用不同顶部结构，例如两个或两个以上RDL以及其它布置(例如，垫上球(BOP)以及活性铜上BOP(BOP-COA))。
半导体裸片102包含顶侧表面102a及底侧表面102b，以其顶侧表面102a面向下的方式安装到切割带135上。焊料球104通过RDL 107电耦合到接合垫103，所述接合垫103电耦合到半导体裸片102的电路180的节点，其中可见在CSP晶片110被放置于切割带135上之后，在下文描述的图1B中展示的焊料球104粘附到切割带135。切割带135的替代例通常可包含可用作用于粘附晶片或裸片的粘附系统的任何材料，例如粘性带或紫外线(UV)带。
电路180包括电路元件(包含晶体管，及通常二极管、电阻器、电容器等)，所述电路元件可任选地形成于例如包括硅的块体衬底材料上的外延层中，其中电路180包含耦合到接合垫103的节点，其中电路180经一起配置以通常实现至少一个电路功能。实例电路功能包含模拟(例如，放大器或功率转换器)、射频(RF)、数字或非易失性存储器功能。
图1B展示当在切割带135上时切割CSP晶片110(通过实例展示为使用锥形角(锥形)刀片145进行机械锯切)之后的结果。或者，针对切割步骤，通常可使用其它工艺，例如等离子蚀刻、激光及湿式化学蚀刻，或通常能够在半导体裸片102的侧壁102c上形成锥形形状的任何其它方法。
切割在图1A中展示的切割道111中，因此，介于半导体裸片102之间，其中可见切割是为开口自身提供约60°的角度的开口的V形切割。在随后描述的晶片单切之后，这导致每一CSP的侧壁表面102c界定一个平面，所述平面相对于由底侧表面102b界定的平面形成约30°的角度。图1C展示在沉积金属涂层108作为涂布半导体裸片102的底侧表面102b以及侧壁表面102c的毯覆层之后的结果。
金属涂层108可包括各种不同金属。例如，金属涂层108包括选自铝、铜、金、钛、镍、银、钯及锡的至少一个金属。通过所公开倾斜侧壁表面102c实现，可见金属涂层108的厚度遍及各处大致上均匀。金属涂层108大体上在侧壁表面102c中的每一者的整个区域上方且在底侧表面102b的整个区域上方，包含相对于底侧表面上的金属涂层108的平均厚度，侧壁表面与顶侧表面的界面的至少80％的厚度。
图1D展示在以下操作之后的现被展示为CSP 190的单个单切CSP：通常通过在半导体裸片102中的邻近者之间的切割道中机械地断裂穿过金属涂层108而单切CSP晶片110，且接着通过通常拾取CSP 190中的经单切者而从切割带135移除。机械地断裂可通过由金属涂层108的机械弱点实现的拾取过程实施，所述金属涂层108如上文描述般通常为薄层，这实现(例如，使用拾取过程)在切割道位置中使金属涂层108机械地断裂。还可使用其它晶片单切工艺。
由于金属涂层108的厚度可为薄的(例如具有1nm到5μm(例如50nm到500nm)的平均厚度)，所以到半导体裸片102的粘着通常足够强以防止金属涂层108在切割带135移除过程期间断裂或开裂。可见金属涂层108均匀地涂布CSP 190的底侧表面102b以及侧壁表面102c。可见CSP 190的侧壁表面102c上的金属涂层108界定被展示为108a的侧壁平面，所述侧壁平面被展示为相对于平行于从由底侧表面102b(其在本文中被称为底侧金属层)上的金属涂层108界定的底平面投影的法线的法线119成从10°到60°的角度(展示为(θ))。侧壁表面102c的数目可为4，且与底侧表面102b的界面每一者可为相对于从顶侧表面102a或底侧表面102b向下绘制的法线投影成至少25°的角度的线性表面。
金属涂层108在图1D中被展示为在CSP 190的底侧表面102b上具有均匀厚度，其中相同均匀厚度针对朝向CSP 190的顶侧(有源)表面102a的大部分距离延伸到侧壁表面102c。可见金属涂层108沿着侧壁表面102c在与顶侧表面102a的界面附近的厚度稍微更薄，例如与CSP 190的其它表面上的金属涂层108厚度相比，约5％到10％更薄(随着切割角增加，相对变薄较少)。侧壁表面102c的其中金属涂层108通常机械地断裂以完成单切的区域也证实被展示为凹凸不平边缘108r的凹凸不平(不均匀)边缘图案。
图2A到2E是从通过实例展示具有在对应于用于使用阶梯切割形成具有锥形侧壁的未封装半导体裸片的实例方法的各个步骤之后的多个CSP 100的CSP晶片110开始的连续横截面视图，其中金属涂层108形成于底侧表面及侧壁表面上。图2A展示在顶侧朝下安装在切割带135上之后的CSP晶片100。图2B展示通过锥形刀片145进行的第一阶梯切割，其中切割大约在CSP晶片110的厚度的中间停止。图2C展示通过笔直形状的刀片148进行的第二阶梯切割，其被展示为切穿晶片的剩余厚度，包含切割到带135中。侧壁表面针对锥形部分被展示为102c1且针对笔直侧壁部分被展为102c2。图2D展示在于半导体裸片102的底侧表面102b及侧壁表面102c1、102c2上形成金属涂层108之后的处理中CSP晶片110。图2E展示在提供单切的裸片拾取步骤之后的单个CSP 200，如上文描述，所述单切可通过使用拾取过程在邻近半导体裸片102之间使金属涂层108机械地断裂以提供CSP 200而完成。
图3A到3E是实例模塑封装工艺流程的连续横截面视图，其中在各个步骤之后，在引线框架410上存在半导体裸片102，其中多个引线框架410被一起展示为引线框架片。半导体裸片102不需要是CSP。图3A展示可被视为模塑条带(或模塑面板)之物，其包含引线框架片，所述引线框架片包含多个引线框架410，每一引线框架410包含引线411，其中多个半导体裸片102被展示为通过接合线428线接合到一些引线框架410，且一些半导体裸片102由焊料球429倒装芯片安装到其它引线框架410上，其全部在模塑化合物427内。每一半导体裸片102与其引线框架及接合线或焊料球一起附着到引线框架的引线411，其中其模塑化合物427可被视为模塑封装。
图3B展示在使用锥形刀片145的第一阶梯切割之后的结果，所述第一阶梯切割大约在模塑化合物427的厚度的中间停止。模塑化合物427的锥形侧壁部分被展示为427a。图3C展示在模塑化合物427上方(包含在锥形侧壁部分427a上方)形成金属涂层108之后的结果。图3D展示在被展示为切割到切割带135中以提供裸片单切的第二阶梯切割笔直形状的刀片148之后的结果。图3E展示单个半导体装置，其针对线接合封装被展示为350且针对倒装芯片封装被展示为380，两者均在裸片拾取步骤之后。
图4A到4D是利用使用在其底侧上具有BGA的衬底(衬底BGA)458的单个切割，其中BGA被单独展示为459的实例模塑封装工艺流程的连续横截面视图，其中在衬底BGA 458的顶侧上存在半导体裸片102。虽然未展示，但在此工艺流程及本公开中的别处，衬底BGA 458通常包含多个层，包含由邻近金属层之间的填充通孔使连接从BGA459的顶表面延伸到焊料球104而提供的导电垂直连接。半导体裸片102不需要是CSP。
图4A展示安装可被称为模塑条带之物之后的结果，所述模塑条带在衬底BGA 458上的模塑化合物427内包含多个半导体裸片102，所述衬底BGA 458在其顶侧上具有金属垫458a及在底侧(其被展示为在切割带135上)上包含多个焊料球104的BGA 459。模塑条带被展示为用于包含接合线428的线接合布置(其中半导体裸片102的底侧被展示为通过裸片粘接材料436附着到衬底BGA 458)及使用包含在半导体裸片102的接合垫103上方的电接触衬底BGA 458的顶侧上的金属垫458a的焊料球429实施的倒装芯片布置两者。
图4B展示在使用锥形刀片145切穿模塑化合物427之后的结果，所述锥形刀片145继续直到切割到带135中。模塑化合物427的锥形侧壁被展示为427a。图4C展示包含在模塑化合物427上方沉积金属涂层108之后的结果，其中在锥形部分427上方的金属涂层108呈现图4C中展示的锥形侧壁部分427a的锥形。图4D展示在提供封装单切的封装拾取步骤(其如所述可在邻近封装之间使金属涂层108断裂)之后的单个模塑封装，所述单个模塑封装针对线接合封装被展示为450且针对倒装芯片封装被展示为480。
图5A到5E是利用包含具有BGA 459的衬底BGA 458的阶梯切割(2个切割)，其中金属涂层108在第二切割之后被施覆的实例模塑封装工艺流程的连续横截面视图，其中存在包括模塑化合物427内的多个半导体裸片102的模塑条带，其中模塑条带在衬底BGA 458上。图5A展示在于衬底BGA 458(其底表面在切割带135上)的顶表面上安装模塑条带之后的结果。模塑条带再次被展示为用于具有使用展示为436的裸片粘接材料的接合线428的线接合布置及使用在半导体裸片102的接合垫103上的接触衬底BGA458的顶表面上的金属垫458a的焊料球429的倒装芯片布置两者。
图5B展示在用于使用锥形刀片145切穿模塑化合物427的第一阶梯切割之后的结果，所述锥形刀片145继续直到切割到模塑化合物427中达半导体裸片102的厚度的约一半的深度。模塑化合物的锥形侧壁被展示为427a。图5C展示在使用笔直形状的刀片148的第二阶梯切割之后的结果，所述笔直形状的刀片148切穿模塑化合物427的剩余厚度以提供在现被展示为427a1的锥形侧壁部分下方的笔直侧壁部分427a2，且继续直到完全切穿衬底BGA458的厚度，包含切割到切割带135的顶部中。图5D展示在图5C中展示的结构上方沉积金属涂层108之后的结果。图5E展示在提供封装单切的封装拾取步骤(其如上文描述可在封装之间使金属涂层108断裂)之后的单个模塑封装，所述单个模塑封装针对线接合封装被展示为550且针对倒装芯片封装被展示为580。
图6A到6E是利用使用衬底BGA 458的阶梯切割，其中金属涂层108在第二切割之前施覆的实例模塑封装工艺流程的连续横截面视图，其中存在包含模塑化合物427内的多个半导体裸片102的模塑条带，其中半导体裸片102的接合垫连接到包含BGA 459的衬底BGA458的顶表面上的金属垫458a。图6A展示在带135上的衬底BGA 458上安装模塑条带之后的结果，其中模塑条带被展示为包含具有接合线428的线接合布置及具有在半导体裸片102的接合垫103上的焊料球429的倒装芯片布置两者。图6B展示在用于使用锥形刀片145切穿模塑化合物427的第一阶梯切割之后的结果，所述锥形刀片145继续直到切割到模塑化合物427的厚度的大致一半中，其中锥形侧壁被展示为427a。图6C展示在于图6B中展示的结构上沉积金属涂层108之后的结果。
图6D展示在使用笔直形状的刀片148的第二阶梯切割之后的结果，所述笔直形状的刀片切穿模塑化合物427的剩余厚度且继续切割直到到达带135的顶部中。模塑化合物的锥形侧壁部分现被展示为427a1，且笔直侧壁部分现被展示为427a2。图6E展示在提供封装单切(其如上文描述可在封装之间使金属涂层108断裂)的封装拾取步骤之后的单个模塑线接合封装，所述单个模塑线接合封装针对模塑倒装芯片封装被展示为650及680。
图7A描绘具有所公开金属涂层108的半导体封装700的横截面视图。具体来说，图7A描绘半导体封装700。所展示半导体封装700是CSP。例如，半导体封装700可为WCSP。还可使用其它类型的CSP。例如，半导体封装700包括半导体裸片102，所述半导体裸片102可包括任何适合半导体材料，例如硅。在一些实例中，半导体裸片102包括易受光透射及因此光穿透(例如，IR穿透)影响的半导体材料，例如硅。半导体裸片102的底表面102b是包括形成于其上及其中其毗连被展示为106的混杂(miscellaneous)层的电路180的有源表面。
取决于半导体封装700的应用及特定配置，混杂层106可包括各种材料及子层中的任何者以促进半导体裸片102的图1A中展示的接合垫103与被展示为焊料球104的导电端子之间的电连接。例如，混杂层106可包括电介质，包含聚酰亚胺、金属迹线、钝化层、涂层等。混杂层106的特定组合物在本文中未详细描述，这是因为其可取决于特定应用而变动且因为其与本文中描述的公开特征不直接相关。然而，一般来说，混杂层106的组合物是开放式的且不限于子层的任何特定数目、类型或配置。
半导体封装700包括被展示为焊料球104的前述导电端子。虽然图7A仅描绘被展示为焊料球104的两个说明性端子，但一般来说，可使用任何数目个导电端子。端子可通常具有任何适合尺寸，且虽然被展示为球形，但端子不一定是球形的。端子经由混杂层106(例如，经由混杂层106中的金属迹线)或使用到半导体裸片102的顶表面102a的有源区域的直接连接耦合到裸片102的顶表面102a。
半导体裸片102包括多个表面(例如，六个表面)。半导体裸片102的多个表面中的每一者位于不同平面中。例如，半导体裸片102的毗连混杂层106的底表面102b位于第一平面中，半导体裸片102的与底表面相对的顶表面位于不同于第一平面的第二平面中，且半导体裸片102的四个横向侧中的每一者位于不同于半导体裸片102的其它五个平面的单独平面中。
在一些实例中，半导体封装700包括覆盖裸片102的六个表面中的五个的金属涂层108。在一些实例中，金属涂层108不覆盖半导体裸片102的顶表面102a，但其覆盖半导体裸片102的剩余五个表面(例如，半导体裸片102的非有源表面)。在其中半导体裸片102具有不同于六的数目个表面的实例中，可以说金属涂层108覆盖全部表面，惟半导体裸片102的有源表面除外。本讨论的剩余部分假定半导体裸片102具有六个表面，其中顶表面102a是半导体裸片102的有源表面。
在一些实例中，金属涂层108完全覆盖五个表面中的每一者(排除顶表面102a)，使得在金属涂层108覆盖范围中不存在间隙。在一些实例中，金属涂层108覆盖五个表面中的每一者的大部分(即，多于50％)。在一些实例中，金属涂层108完全覆盖至少一个表面且覆盖至少一个其它表面的大部分。在一些实例中，金属涂层108至少部分覆盖五个表面中的每一者。在一些实例中，金属涂层108以完全覆盖、大部分覆盖及/或部分覆盖的不同组合覆盖五个表面，且全部此类组合被审慎考虑且包含在本公开的范围中。在一些实例中，金属涂层108覆盖少于五个表面但至少一个表面。
在一些实例中，金属涂层108具有750埃
Figure BDA0003439368280000111
的大约厚度，例如
Figure BDA0003439368280000112
到
Figure BDA0003439368280000113
厚。在一些实例中，金属涂层108包括铝、铜、金、钛、镍、银、钯或锡。在一些实例中，金属涂层108包括合金，例如钨钛合金或不锈钢。各种技术可用于定位金属涂层108，包含金属油墨印刷、溅镀、沉积、化学镀、喷涂技术及电镀，如下文描述。
图7B描绘根据各种实例的封装700的剖面图。如展示，金属涂层108覆盖半导体裸片102的横向侧表面(其中半导体裸片102在图7B中非明确可见)。图7B的视图代表半导体封装700的四个横向侧的视图。
图7C描绘根据各种实例的半导体封装700的自上而下视图。如展示，半导体封装700的顶表面包含金属涂层108。图7D描绘根据各种实例的半导体封装700的透视图。如描绘，半导体封装700的底表面102b及封装700的四个横向侧包含金属涂层108。半导体裸片102的有源顶表面102a经由混杂层106耦合到被展示为焊料球104的导电端子，其中混杂层106从图7D的视图的角度不可见。
图8A描绘根据各种实例的具有电介质层210及现被展示为208的金属涂层的半导体封装800的横截面视图。在图8A到8D中，半导体裸片现被展示为202且混杂层被展示为206。具体来说，图8A描绘包括CSP(例如，WCSP)的半导体封装800。半导体封装800包括半导体裸片202、导电端子204及混杂层206。在至少一些实例中，下文描述，半导体裸片202、导电端子204及混杂层206分别与图7A到7D的半导体裸片102、导电端子104及混杂层106类似或基本上相同。因此，在至少一些实例中，上文相对于图7A到7D针对元件102、104及106提供的描述也适用于图8A到8D中展示的元件202、204及206。如上文提及，电介质层210用作电隔离器(电介质)，但通常不为半导体裸片202提供免受电磁辐射(例如IR)影响的任何显著保护。
图9是安装到包括被展示为411的引线的引线框架410上的包含所公开CSP，包含模塑化合物427的倒装芯片封装900的横截面视图，所述CSP包括具有锥形侧壁表面102c及在侧壁表面102c上的金属涂层108的半导体裸片102。倒装芯片封装900被展示为无引线封装(例如，QFN封装)，其中在引线411上存在焊料球104。
在其它所公开方面(包含如上文相对于图4A到D、5A到E及6A到E公开)中，正是模塑化合物427具有锥形侧壁而非半导体裸片102的侧壁表面。图10A是包含包括半导体裸片102的CSP的倒装芯片封装1000的横截面视图，其中使用于封装1000的金属涂层108能够为锥形的锥形侧壁现由包含锥形侧壁部分427a1及笔直侧壁部分427a2的模塑化合物427提供。半导体裸片102经倒装芯片安装到具有引线411与引线411上的焊料球104的引线框架410上。具有锥形侧壁的所公开金属涂层108通过在呈现其锥形的锥形侧壁部分427a1上方而呈锥形。半导体裸片102的侧壁表面(其非锥形)现被展示为102c’，其中金属涂层108也再次在底侧表面102b上。
图10B是线接合封装1050的横截面视图，其包含包括半导体裸片102的所公开CSP，所述半导体裸片102上具有再次部分呈锥形以提供锥形侧壁部分427a1的模塑化合物427，其中半导体裸片102通过裸片粘接材料569安装在裸片垫512上。金属涂层108在模塑化合物427上方(包含在锥形侧壁部分427a1上方)以在半导体裸片102的侧壁表面102c’及底侧表面102b上方提供锥形。
所公开方面可集成到各种组装流程中以形成各种不同未封装半导体裸片且还形成作为封装衬底的包含引线框架的半导体封装及相关产品。未封装半导体裸片或半导体封装可包括单个半导体裸片或多个半导体裸片，例如包括多个堆叠半导体裸片或横向定位半导体裸片的配置。可使用各种封装衬底。半导体裸片可包含其中的各种元件及/或其上的层，包含阻挡层、电介质层、装置结构、有源元件及无源元件，包含源极区域、漏极区域、位线、基极、发射极、集电极、导线、导电通孔等。再者，半导体裸片可由各种工艺形成，包含双极、绝缘栅极双极晶体管(IGBT)、CMOS、BiCMOS及MEMS。
本公开所涉及的领域的技术人员将了解，所公开方面的许多变动在本发明的范围内是可行的，且可对上述方面进行进一步添加、删除、取代及修改而不脱离本公开的范围。

Claims (30)

1.一种半导体装置，其包括
半导体裸片，其具有顶侧表面、底侧表面及介于所述顶侧表面与所述底侧表面之间的侧壁表面，所述顶侧表面包括在其中包含电路的具有连接到所述电路中的节点的接合垫的半导体材料，及
金属涂层，其包含在所述底侧表面上方连续延伸到所述侧壁表面上的侧壁金属层的底侧金属层，
其中所述侧壁金属层界定相对于从由所述底侧金属层界定的底平面投影的法线成从10°到60°的角度的侧壁平面。
2.根据权利要求1所述的半导体装置，其进一步包括封装，所述封装包含在所述半导体装置周围的模塑化合物及包含引线的引线框架，其中所述接合垫电耦合到所述引线。
3.根据权利要求2所述的半导体装置，其中所述侧壁表面是锥形的以提供至少10°的所述角度，且其中所述金属涂层直接在所述底侧表面上且直接在所述侧壁表面上，且其中所述模塑化合物在所述金属涂层上。
4.根据权利要求2所述的半导体装置，其中所述模塑化合物是锥形的以提供至少10°的所述角度，且其中所述金属涂层在所述模塑化合物上。
5.根据权利要求2所述的半导体装置，其中所述顶侧表面经倒装芯片附着到所述引线。
6.根据权利要求4所述的半导体装置，其中所述引线框架进一步包括裸片垫，其中所述底侧表面在所述裸片垫上，所述半导体装置进一步包括介于所述接合垫与所述引线之间的接合线。
7.根据权利要求1所述的半导体装置，其中所述半导体装置包括芯片规模封装CSP，所述CSP包含电接触所述接合垫的至少一个重布层，在所述重布层上包含焊料球。
8.根据权利要求1所述的半导体装置，其中所述金属涂层包括铝、铜、金、钛、镍、银、钯及锡中的至少一者。
9.根据权利要求6所述的半导体装置，其中所述金属涂层具有1nm到5μm的平均厚度，且其中在邻近所述顶侧表面的端上的所述侧壁表面具有证实机械破裂的边缘。
10.根据权利要求1所述的半导体装置，其中所述金属涂层在所述侧壁表面中的全部的整个区域上方，且在所述底侧表面的整个区域上方，包含相对于所述底侧表面上的所述金属涂层的平均厚度，所述侧壁表面与所述顶侧表面的界面的至少80％的厚度。
11.根据权利要求1所述的半导体装置，其进一步包括封装，所述封装包含在所述半导体装置周围的模塑化合物，其中所述模塑化合物具有锥形的侧壁及衬底球栅阵列BGA，其中所述接合垫电耦合到所述衬底BGA上的接合特征。
12.根据权利要求1所述的半导体装置，其进一步包括电介质层，所述电介质层介于所述金属涂层与所述底侧表面之间，且介于所述金属涂层与所述侧壁表面之间。
13.一种形成半导体封装的方法，所述方法包括：
切穿包含多个半导体裸片的半导体组合件，所述多个半导体裸片每一者包含顶侧表面及底侧表面，所述顶侧表面包括在其中包含电路的具有连接到所述电路中的节点的接合垫的半导体材料，所述切割形成界定相对于所述底侧表面成从10°到60°的角度的侧壁平面的侧壁表面，及
形成金属涂层，所述金属涂层包含在所述底侧表面上方连续延伸到所述侧壁表面上方的侧壁金属层的底侧金属层，
其中所述侧壁金属层包含具有从10°到60°的所述角度的所述侧壁平面。
14.根据权利要求13所述的方法，其中所述半导体组合件包括晶片，且所述方法进一步包括：
安装具有介于所述半导体裸片之间的切割道的所述晶片，使得所述半导体裸片的所述顶侧表面在经配置用于固定所述晶片的粘附系统上面向下；
其中所述切割包括从所述底侧表面开始切穿所述切割道以形成介于所述顶侧表面与所述底侧表面之间的所述切割侧壁表面，及
在介于所述半导体裸片中的邻近者之间的位置中分离所述金属涂层以形成所述半导体裸片的多个单切者。
15.根据权利要求14所述的方法，其中所述分离包括裸片拾取，所述裸片拾取包括从所述粘附系统移除所述半导体组合件中的个别者。
16.根据权利要求13所述的方法，其中所述半导体组合件包括各自使用电连接到引线的所述接合垫或所述引线安装在具有所述引线的引线框架面板的引线框架上的所述多个半导体裸片，所述方法进一步包括形成模塑化合物以囊封所述多个半导体裸片，且其中所述切割包括切割所述模塑化合物以提供界定具有相对于所述底侧表面的至少10°的所述角度的所述侧壁平面的所述切割侧壁表面。
17.根据权利要求14所述的方法，其中所述粘附系统包括切割带。
18.根据权利要求13所述的方法，其中使用具有锥形远端的刀片以用于所述切割。
19.根据权利要求13所述的方法，其中所述形成所述金属涂层包括溅镀沉积工艺或喷涂工艺。
20.根据权利要求13所述的方法，其中所述切割包括利用具有尖端的锥形刀片，其中所述切割提供切穿所述半导体组合件的整个厚度。
21.根据权利要求13所述的方法，其中所述切割包括第一切割步骤及第二切割步骤，第一切割步骤利用锥形刀片切割到所述半导体组合件的中间，接着利用笔直形状的刀片完成所述切割。
22.根据权利要求13所述的方法，其中所述金属涂层包括铝、铜、金、钛、镍、银、钯及锡中的至少一者。
23.根据权利要求13所述的方法，其中所述金属涂层具有1nm到5μm的平均厚度。
24.根据权利要求13所述的方法，其中所述金属涂层覆盖所述侧壁表面中的全部的整个区域及所述底侧表面的整个区域。
25.根据权利要求13所述的方法，其中所述侧壁表面的数目是4个，且与所述底侧表面的界面每一者是相对于从所述顶表面向下绘制的法线投影成25°到60°的角度的线性表面。
26.根据权利要求13所述的方法，其中所述方法进一步包括在形成所述金属涂层之前，在所述底侧表面上且在所述侧壁表面上形成电介质层。
27.根据权利要求13所述的方法，其进一步包括在所述多个半导体裸片周围形成模塑化合物。
28.根据权利要求27所述的方法，其中所述形成所述模塑化合物在所述金属涂层的所述形成之后发生。
29.根据权利要求27所述的方法，其中所述形成所述模塑化合物在所述金属涂层的所述形成之前发生，使得所述金属涂层在所述模塑化合物上。
30.根据权利要求27所述的方法，其进一步包括在所述模塑化合物的所述形成之前，将所述半导体裸片安装在具有引线的引线框架上，且将所述接合垫电连接到所述引线。
CN202111624115.4A 2020-12-31 2021-12-28 具有锥形金属涂层侧壁的半导体装置 Pending CN114765162A (zh)

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