CN107887346B - 集成扇出型封装件 - Google Patents

集成扇出型封装件 Download PDF

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Publication number
CN107887346B
CN107887346B CN201611112499.0A CN201611112499A CN107887346B CN 107887346 B CN107887346 B CN 107887346B CN 201611112499 A CN201611112499 A CN 201611112499A CN 107887346 B CN107887346 B CN 107887346B
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integrated circuit
die attach
circuit assembly
integrated
attach film
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CN107887346A (zh
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邱铭彦
张兢夫
黄信杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供一种集成扇出型封装件，所述集成扇出型封装件包括管芯贴合膜、集成电路组件、绝缘包封体及重布线路结构。所述集成电路组件配置于所述管芯贴合膜上且包括多个导电端子。所述管芯贴合膜包括升高的边缘，所述升高的边缘朝所述集成电路组件的侧壁凸起。所述绝缘包封体包覆所述升高的边缘及所述集成电路组件。所述重布线路结构配置于所述集成电路组件及所述绝缘包封体上，且所述重布线路结构电连接至所述集成电路组件的所述导电端子。还提供一种制作集成扇出型封装件的方法。

Description

集成扇出型封装件
技术领域
本发明的实施例涉及一种集成扇出型封装件。
背景技术
由于各种电子组件(即，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速增长。在很大程度上，集成密度的此种提高来自于最小特征大小的重复减小，此使得更多较小的组件能够集成到给定区域中。这些较小的电子组件也需要与先前的封装件相比利用较小区域的较小的封装件。半导体组件的某些较小类型的封装件包括方形扁平封装件(quad flat package，QFP)、引脚栅阵列(pin grid array，PGA) 封装件、球栅阵列(ball grid array，BGA)封装件等等。
当前，集成扇出型封装件因其紧凑性而正变得日渐流行。对于未来的封装件来说，集成扇出型封装件所提供的提高的可布线性(routability)及可靠性(reliability)是关键因素。
发明内容
本发明的实施例提供一种集成扇出型封装件，所述集成扇出型封装件包括管芯贴合膜、集成电路组件、绝缘包封体及重布线路结构。所述集成电路组件配置于所述管芯贴合膜上且包括多个导电端子。所述管芯贴合膜包括升高的边缘，所述升高的边缘朝所述集成电路组件的侧壁凸起。所述绝缘包封体包覆所述升高的边缘及所述集成电路组件。所述重布线路结构配置于所述集成电路组件及所述绝缘包封体上，且所述重布线路结构电连接至所述集成电路组件的所述导电端子。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1至图11说明制作根据某些实施例的集成扇出型封装件的工艺流程。
图12是说明根据某些实施例的叠层封装(package-on-package，POP) 结构的剖视图。
图13是说明根据某些实施例的管芯贴合膜的升高的边缘的放大剖视图。
[符号的说明]
100：晶片
100’：薄化晶片
110、110’、110a：半导体衬底
120：导电垫
130、130a：钝化层
132、142：接触开口
140、140a：后钝化层
150：导电柱或导电孔
160、160a、160a’：保护层
180、180’：管芯贴合膜
182：升高的边缘/延伸部分
184：管芯贴合部分
200：集成电路组件
210：绝缘材料
210’：绝缘包封体
220：重布线路结构
222：层间介电层
224：重布线导电层
224a：球下金属图案
224b：连接垫
230、250：导电球
240：无源组件
300：封装件
C：载板
DB：剥离层
DI：介电层
L：长度
O：接触开口
SUB：支撑衬底
TIV：贯穿绝缘体的导电通孔
θ：夹角
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本发明。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复参考编号及/或字母。这种重复是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对性描述语可同样相应地进行解释。
图1至图11说明制作根据某些实施例的集成扇出型封装件的工艺流程，且图12是说明根据某些实施例的叠层封装(POP)结构的剖视图。
参照图1，提供包括排列成阵列的多个管芯(或集成电路组件)200的晶片100。在对晶片100进行晶片切割(wafer dicing)工艺之前，晶片100 中的集成电路组件200是彼此连接的。在某些实施例中，晶片100包括半导体衬底110、形成在半导体衬底110之上的多个导电垫120及钝化层130。钝化层130形成在半导体衬底110之上且界定多个接触开口132，以局部地暴露出导电垫120。半导体衬底110上的导电垫120经由接触开口132从钝化层130局部地暴露出。半导体衬底110可为硅衬底，所述硅衬底包括形成在所述硅衬底中的有源组件(例如，晶体管等)及无源组件(例如，电阻器、电容器、电感器等)；导电垫120可为铝垫、铜垫或其他适合的金属垫；且钝化层130可为氧化硅层、氮化硅层、氮氧化硅层或由其他适合的介电材料形成的介电层。
如图1中所示，在某些实施例中，晶片100可进一步包括形成在钝化层130之上的后钝化(post-passivation)层140。后钝化层140覆盖钝化层 130且具有多个接触开口142。导电垫120被后钝化层140局部地覆盖但从接触开口132暴露出。换句话说，导电垫120被后钝化层140的接触开口 142局部地暴露出。后钝化层140可为聚酰亚胺(polyimide，PI)层、聚苯并恶唑(polybenzoxazole，PBO)层或由其他适合的聚合物形成的介电层。
参照图2，在导电垫120上形成多个导电柱或导电孔150。在某些实施例中，导电柱或导电孔150镀覆在导电垫120上。例如，首先将晶种层(例如，Ti/Cu晶种层)溅射至后钝化层140及被接触开口142暴露出的导电垫 120上；接着通过光刻(photolithography)在所述晶种层之上形成用于暴露出导电垫120的图案化光刻胶层(图中未示出)；接着将包括形成在晶片100 上的图案化光刻胶层的晶片100浸入至镀覆溶液中，进而使得导电柱或导电孔150镀覆在与导电垫120对应的晶种层上。在形成所镀覆的导电柱或导电孔150之后，剥除所述图案化光刻胶层。此后，利用导电柱或导电孔 150作为硬掩模，例如通过刻蚀(etching)移除所述晶种层的未被导电柱或导电孔150覆盖的部分直至暴露出后钝化层140为止。在某些实施例中，导电柱或导电孔150为铜柱或铜孔。
参照图3，在形成导电柱或导电孔150之后，在后钝化层140上形成保护层160，以覆盖导电柱或导电孔150。在某些实施例中，保护层160可为具有足以包覆及保护导电柱或导电孔150的厚度的聚合物层。例如，保护层160可为聚苯并恶唑(PBO)层、聚酰亚胺(PI)层或其他适合的聚合物。在某些替代实施例中，保护层160可由无机材料制成。
参照图3及图4，在形成保护层160之后，对晶片100的后表面进行背侧研磨(backside grinding)工艺。在所述背侧研磨工艺期间，研磨半导体衬底110，进而使得形成包括半导体衬底110’的薄化晶片100’。接着，将薄化晶片100’通过管芯贴合膜180贴合至支撑衬底SUB上。应注意，在半导体衬底110的厚度足够薄时，所述背侧研磨工艺为选择性的工艺。换句话说，当半导体衬底110的厚度对于制作者来说可接受时，可将晶片100通过管芯贴合膜180贴合至支撑衬底SUB上，且在所述管芯贴合工艺之前无需进行背侧研磨工艺。
参照图5，在进行上述管芯贴合或管芯结合工艺之后，对薄化晶片100’ (或图3中所示的晶片100)进行晶片切割工艺，进而使得薄化晶片100’ (或图3中所示的晶片100)的集成电路组件200彼此单体化。如图5中所示，经单体化的集成电路组件200各自包括半导体衬底110a、形成在半导体衬底110a上的导电垫120、钝化层130a、后钝化层140a、导电柱或导电孔150及保护层160a。导电垫120及电连接至导电垫120的导电孔150可被视作集成电路组件200的导电端子。半导体衬底110a、钝化层130a、后钝化层140a及保护层160a的材料与半导体衬底110、钝化层130、后钝化层140及保护层160的材料相似。因此，省略了对半导体衬底110a、钝化层130a、后钝化层140a及保护层160a的详细说明。
在所述晶片切割工艺期间，对薄化晶片100’下方的管芯贴合膜180进行图案化或切割，进而使得在经单体化的集成电路组件200下方形成多个管芯贴合膜180’。应注意，管芯贴合膜180’的侧壁与集成电路组件200的侧壁实质上对齐。
如图4及图5中所示，在所述背侧研磨工艺及所述晶片切割工艺期间，保护层160及160a可完善地保护集成电路组件200的导电端子(例如，导电垫120及导电孔150)。另外，可保护集成电路组件200的导电垫120及导电孔150不被例如集成电路组件200的拾取及放置(pick-up and placing) 工艺、模塑(molding)工艺等後续进行的工艺损坏。
参照图6，在形成集成电路组件200及管芯贴合膜180’之后，提供其上已形成有剥离(de-bonding)层DB及介电层DI的载板C，其中剥离层DB 处于载板C与介电层DI之间。在某些实施例中，载板C是玻璃衬底，剥离层DB是形成在所述玻璃衬底上的光-热转换(light-to-heat conversion， LTHC)释放层，且介电层DI是形成在剥离层DB上的聚苯并恶唑(PBO)层。
在提供其上已形成有剥离层DB及介电层DI的载板C之后，在介电层 DI上形成多个贯穿绝缘体的导电通孔TIV。在某些实施例中，所述多个贯穿绝缘体的导电通孔TIV是通过光刻、镀覆及光刻胶剥除(photoresist stripping)工艺形成。例如，贯穿绝缘体的导电通孔TIV包括铜柱(copper post)。
如图5及图6中所示，在某些实施例中，可将包括有导电端子(例如，导电垫120及导电孔150)及形成在所述导电端子上的保护层160a的其中一个集成电路组件200拾取且放置在介电层DI上。将集成电路组件200通过管芯贴合膜180’贴合(或粘合)在介电层DI上。应注意，在将集成电路组件200拾取且放置在介电层DI上之后，管芯贴合膜180’可侧向地延伸且管芯贴合膜180’所占据的面积增大。换句话说，管芯贴合膜180’的侧壁并不与集成电路组件200的侧壁对齐。因施加在集成电路组件200上的压力导致的管芯贴合膜180’的膨胀对应于管芯贴合膜180’的体积(或厚度)及施加在集成电路组件200上的压力。
在某些替代实施例中，可将多于一个集成电路组件200拾取且放置在介电层DI上，其中放置在介电层DI上的集成电路组件200可排列成阵列。当放置在介电层DI上的集成电路组件200排列成阵列时，可将贯穿绝缘体的导电通孔TIV归类成多个群组。集成电路组件200的数目可对应于贯穿绝缘体的导电通孔TIV的群组的数目。
如图6中所示，在所示实施例中，保护层160a的顶表面低于贯穿绝缘体的导电通孔TIV的顶表面，且保护层160a的顶表面高于导电柱或导电孔 150的顶表面。然而，本发明的实施例不限于此。在某些替代实施例中，保护层160a的顶表面可与贯穿绝缘体的导电通孔TIV的顶表面实质上对齐，且保护层160a的顶表面高于导电柱或导电孔150的顶表面。
如图6中所示，可在形成贯穿绝缘体的导电通孔TIV之后，将集成电路组件200中的一个或多个拾取且放置在介电层DI上。然而，本发明的实施例不限于此。在某些替代实施例中，可在形成贯穿绝缘体的导电通孔TIV 之前，将集成电路组件200中的一个或多个拾取且放置在介电层DI上。
参照图7，通过例如压缩模塑(compression molding)工艺在介电层DI 上形成绝缘材料210，以包覆集成电路组件200、管芯贴合膜180’及贯穿绝缘体的导电通孔TIV。集成电路组件200的导电柱或导电孔150及保护层 160a被绝缘材料210包覆且完善地保护。换句话说，集成电路组件200的导电柱或导电孔150及保护层160a未被绝缘材料210显露出且被绝缘材料 210完善地保护。在某些实施例中，绝缘材料210包括环氧树脂(epoxy) 或其他适合的树脂。
如图7中所示，在压缩模塑工艺期间，从管芯贴合膜180’的侧向突出的部分形成升高的边缘182，升高的边缘182朝集成电路组件200的侧壁凸起或折叠。在进行所述压缩模塑工艺之后，管芯贴合膜180’的升高的边缘 182及集成电路组件200被绝缘材料210包覆。因此，管芯贴合膜180’可包括管芯贴合部分184及连接至管芯贴合部分184的延伸部分182(即，升高的边缘182)，其中集成电路组件200直接安装在管芯贴合部分184上，且延伸部分182(即，升高的边缘182)从管芯贴合部分184的边缘向上及向外延伸。延伸部分182(即，升高的边缘182)可为连接至管芯贴合部分184 的框型结构(或框架)。
应注意，在所述压缩模塑工艺中使用的模塑化合物将管芯贴合膜180’的延伸部分182(即，升高的边缘182)提升以从载板C上的介电层DI层离(delaminate)，进而使得延伸部分182(即，升高的边缘182)可朝集成电路组件200的侧壁凸起。延伸部分182(即，升高的边缘182)与集成电路组件200的侧壁之间产生空间，且所述空间被绝缘材料210填充。在某些实施例中，延伸部分182(即，升高的边缘182)被所述模塑化合物提升，延伸部分182(即，升高的边缘182)与集成电路组件200的侧壁之间的夹角θ介于约0度至约70度范围内，且延伸部分182(即，升高的边缘182) 的长度L介于例如约10微米至约20微米范围内。在某些实施例中，管芯贴合膜180’的延伸部分182(即，升高的边缘182)可增大管芯贴合膜180’与绝缘材料210的接触面积且增强管芯贴合膜180’与绝缘材料210之间的粘合，进而可降低管芯贴合膜180’与绝缘材料210之间发生层离的可能性。管芯贴合膜180’的夹角θ与所述压缩模塑工艺的压力分布相关。换句话说，管芯贴合膜180’的夹角θ是所述压缩模塑工艺的压力分布的指标。
延伸部分182(即，升高的边缘182)与集成电路组件200的侧壁之间的夹角θ与所述压缩模塑工艺的参数(例如，压力、用于形成绝缘材料210 的模(mold)的形状等等)相关。此外，延伸部分182(即，升高的边缘 182)的长度L与在所述拾取及放置工艺期间施加在集成电路组件200上的按压力相关。换句话说，延伸部分182(即，升高的边缘182)的长度L与因上述按压力导致的侧向膨胀相关。
在某些替代实施例中，如图13中所示，管芯贴合膜180’的延伸部分182 (即，升高的边缘182)可沿集成电路组件200的侧壁延伸且可接触集成电路组件200的侧壁。换句话说，延伸部分182(即，升高的边缘182)与集成电路组件200的侧壁之间几乎不具有空间。
参照图8，研磨绝缘材料210直至暴露出导电柱或导电孔150(即，导电端子)的顶表面、贯穿绝缘体的导电通孔TIV的顶表面及保护层160a的顶表面为止，以形成绝缘包封体210’。在某些实施例中，通过机械研磨工艺及/或化学机械抛光(chemical mechanicalpolishing，CMP)工艺来研磨绝缘材料210。在绝缘材料210的研磨工艺期间，研磨保护层160a的部分以形成保护层160a’。在某些实施例中，在绝缘材料210及保护层160a的机械研磨工艺期间，也研磨贯穿绝缘体的导电通孔TIV的部分。
如图8中所示，绝缘包封体210’侧向地包覆管芯贴合膜180’的延伸部分182(即，升高的边缘182)及集成电路组件200，且绝缘包封体210’被贯穿绝缘体的导电通孔TIV穿透。换句话说，集成电路组件200、管芯贴合膜180’及贯穿绝缘体的导电通孔TIV嵌于绝缘包封体210’中。
参照图9，在形成绝缘包封体210’及保护层160a’之后，在贯穿绝缘体的导电通孔TIV的顶表面、绝缘包封体210’的顶表面、导电孔150的顶表面及保护层160a’的顶表面上形成电连接至集成电路组件200的导电柱或导电孔150的重布线路结构220。所制作的重布线路结构220会与位于其下的一个或多个导电端子电连接。以下搭配图9详细阐述重布线路结构220。
参照图9，重布线路结构220包括交替堆叠的多个层间介电层 (inter-dielectriclayer)222及多个重布线导电层224，且重布线导电层224 电连接至集成电路组件200的导电孔150及嵌于绝缘包封体210’中的贯穿绝缘体的导电通孔TIV。如图9中所示，在某些实施例中，导电孔150的顶表面及贯穿绝缘体的导电通孔TIV的顶表面接触重布线路结构220。导电孔150的顶表面及贯穿绝缘体的导电通孔TIV的顶表面被最底部层间介电层222局部地覆盖。此外，最顶部重布线导电层224包括多个垫。在某些实施例中，上述垫包括用于导电球安装(ball mount)的多个球下金属 (under-ball metallurgy，UBM)图案224a及/或用于安装无源组件的至少一个连接垫224b。球下金属图案224a及连接垫224b的数目在本发明的实施例中并无限制。
如图9中所示，在形成重布线路结构220之后，在球下金属图案224a 上放置多个导电球230，且在连接垫224b上安装多个无源组件240。在某些实施例中，可通过植球(ballplacement)工艺在球下金属图案224a上放置导电球230且可通过焊接(soldering)工艺在连接垫224b上安装无源组件240。
参照图9及图10，在重布线路结构220上安装导电球230及无源组件 240之后，从剥离层DB剥离在绝缘包封体210’的顶表面上形成的介电层 DI，进而使得介电层DI从载板C分离。在某些实施例中，可通过UV激光照射剥离层DB(例如，光-热转换释放层)，进而使得介电层DI从载板C 脱落(peel)。如图10中所示，接着将介电层DI图案化，进而使得形成多个接触开口O以暴露出贯穿绝缘体的导电通孔TIV的底表面。接触开口O 的数目对应于贯穿绝缘体的导电通孔TIV的数目。在某些实施例中，通过激光钻孔(laser drilling)工艺形成介电层DI的接触开口O。
参照图11，在介电层DI中形成接触开口O之后，在贯穿绝缘体的导电通孔TIV的被接触开口O暴露出的底表面上放置多个导电球250。例如对导电球250进行回焊以使导电球250与贯穿绝缘体的导电通孔TIV的底表面接合。如图11中所示，在形成导电球230及导电球250之后，具有双侧端子的集成电路组件200的集成扇出型封装件制作完成。
参照图12，接着提供另一封装件300。在某些实施例中，封装件300 为例如存储器装置。通过导电球250将封装件300堆叠在图11中所示的集成扇出型封装件之上并电连接至所述集成扇出型封装件，进而使得叠层封装(POP)结构制作完成。
在上述实施例中，集成扇出型封装件的可靠性及良率(yield rate)可通过所述具有延伸部分或升高的边缘的管芯贴合膜可获得提升 。
根据本发明的某些实施例，提供集成扇出型封装件，所述集成扇出型封装件包括管芯贴合膜、集成电路组件、绝缘包封体及重布线路结构。所述集成电路组件配置于所述管芯贴合膜上且包括多个导电端子。所述管芯贴合膜包括升高的边缘，所述升高的边缘从所述集成电路组件的周边部分的下方突出地延伸并朝所述集成电路组件的侧壁凸起。所述绝缘包封体包覆所述升高的边缘及所述集成电路组件。所述重布线路结构配置于所述集成电路组件及所述绝缘包封体上，且所述重布线路结构电连接至所述集成电路组件的所述导电端子。
在所述集成扇出型封装件中，所述升高的边缘沿所述集成电路组件的所述侧壁延伸并接触所述集成电路组件的所述侧壁。
在所述集成扇出型封装件中，在所述升高的边缘与所述集成电路组件的所述侧壁之间具有空间，且所述空间被所述绝缘包封体填充。
在所述集成扇出型封装件中，所述升高的边缘与所述集成电路组件的所述侧壁之间的夹角介于约0度至约70度范围内。
在所述集成扇出型封装件中，所述升高的边缘的长度介于约10微米至约20微米范围内。
在所述集成扇出型封装件中，所述升高的边缘为框型结构。
所述集成扇出型封装件进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述贯穿绝缘体的导电通孔电连接至所述重布线路结构。
根据本发明的替代实施例，提供一种集成扇出型封装件，所述集成扇出型封装件包括管芯贴合膜、集成电路组件、绝缘包封体及重布线路结构。所述集成电路组件包括多个导电端子。所述管芯贴合膜以粘合方式贴合至所述集成电路组件的底表面。所述管芯贴合膜包括与所述集成电路组件接触的管芯贴合部分及连接至所述管芯贴合部分的延伸部分，所述延伸部分从所述管芯贴合部分向上及向外延伸。所述绝缘包封体侧向地包覆所述管芯贴合膜及所述集成电路组件。所述重布线路结构配置于所述集成电路组件及所述绝缘包封体上，且所述重布线路结构电连接至所述集成电路组件的所述导电端子。
在所述集成扇出型封装件中，所述延伸部分沿所述集成电路组件的所述侧壁延伸并接触所述集成电路组件的所述侧壁。
在所述集成扇出型封装件中，在所述延伸部分与所述集成电路组件的所述侧壁之间具有空间，且所述空间被所述绝缘包封体填充。
在所述集成扇出型封装件中，所述延伸部分与所述集成电路组件的所述侧壁之间的夹角介于约0度至约70度范围内。
在所述集成扇出型封装件中，所述延伸部分的长度介于约10微米至约 20微米范围内。
在所述集成扇出型封装件中，所述延伸部分为框型结构。
所述集成扇出型封装件进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述贯穿绝缘体的导电通孔电连接至所述重布线路结构。
根据本发明又一些替代实施例，提供一种制作集成扇出型封装件的方法。所述方法包括以下步骤。提供包括多个导电端子的集成电路组件且将所述集成电路组件通过管芯贴合膜安装至载板上。通过压缩模塑工艺在所述载板上形成绝缘包封体，其中所述绝缘包封体侧向地包覆所述集成电路组件及所述管芯贴合膜，在所述压缩模塑工艺期间形成所述管芯贴合膜的升高的边缘，且所述升高的边缘朝所述集成电路组件的侧壁凸起。在所述集成电路组件及所述绝缘包封体上形成重布线路结构，且所述重布线路结构电连接至所述集成电路组件的所述导电端子。
在所述方法中，所述压缩模塑工艺使所述管芯贴合膜的所述升高的边缘提升，以从所述载板层离并朝所述集成电路组件的所述侧壁凸起。
在所述方法中，所述压缩模塑工艺使得所述管芯贴合膜的所述升高的边缘沿所述集成电路组件的所述侧壁延伸。
在所述方法中，所述压缩模塑工艺使得所述管芯贴合膜的所述升高的边缘朝所述集成电路组件的所述侧壁凸起，且所述升高的边缘与所述集成电路组件的所述侧壁之间的空间被所述绝缘包封体填充。
在所述方法中，所述压缩模塑工艺使得所述管芯贴合膜的所述升高的边缘朝所述集成电路组件的所述侧壁凸起，且所述升高的边缘与所述集成电路组件的所述侧壁之间的夹角介于约0度至约70度范围内。
所述方法进一步包括：在形成所述绝缘包封体之前在所述载板上形成多个贯穿绝缘体的导电通孔，其中在形成所述贯穿绝缘体的导电通孔及所述重布线路结构之后所述贯穿绝缘体的导电通孔电连接至所述重布线路结构。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，他们可容易地使用本发明作为设计或修改其他工艺及结构的基础来实施与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (74)

1.一种集成扇出型封装件，其特征在于，包括：
管芯贴合膜；
集成电路组件，配置于所述管芯贴合膜上且包括多个导电端子，所述管芯贴合膜包括升高的边缘，所述升高的边缘从所述集成电路组件的周边部分的下方突出地延伸并朝所述集成电路组件的侧壁凸起；
绝缘包封体，包覆所述升高的边缘及所述集成电路组件；以及
重布线路结构，配置于所述集成电路组件及所述绝缘包封体上，所述重布线路结构电连接至所述集成电路组件的所述导电端子，其中所述管芯贴合膜的底表面与所述绝缘包封体的底表面共面。
2.根据权利要求1所述的集成扇出型封装件，其特征在于，所述升高的边缘沿所述集成电路组件的所述侧壁延伸并接触所述集成电路组件的所述侧壁。
3.根据权利要求1所述的集成扇出型封装件，其特征在于，在所述升高的边缘与所述集成电路组件的所述侧壁之间具有空间，且所述空间被所述绝缘包封体填充。
4.根据权利要求1所述的集成扇出型封装件，其特征在于，所述升高的边缘与所述集成电路组件的所述侧壁之间的夹角介于0度至70度范围内。
5.根据权利要求1所述的集成扇出型封装件，其特征在于，所述升高的边缘的长度介于10微米至20微米范围内。
6.根据权利要求1所述的集成扇出型封装件，其特征在于，所述升高的边缘为框型结构。
7.根据权利要求1所述的集成扇出型封装件，其特征在于，进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
8.一种集成扇出型封装件，其特征在于，包括：
集成电路组件，包括多个导电端子；
管芯贴合膜，以粘合方式贴合至所述集成电路组件的底表面，所述管芯贴合膜包括与所述集成电路组件接触的管芯贴合部分及连接至所述管芯贴合部分的延伸部分，所述延伸部分从所述管芯贴合部分向上及向外延伸；
绝缘包封体，侧向地密封所述管芯贴合膜及所述集成电路组件，其中所述管芯贴合膜的底表面与所述绝缘包封体的底表面共面；以及
重布线路结构，配置于所述集成电路组件及所述绝缘包封体上，所述重布线路结构电连接至所述集成电路组件的所述导电端子。
9.根据权利要求8所述的集成扇出型封装件，其特征在于，所述延伸部分沿所述集成电路组件的侧壁延伸并接触所述集成电路组件的所述侧壁。
10.根据权利要求8所述的集成扇出型封装件，其特征在于，在所述延伸部分与所述集成电路组件的侧壁之间具有空间，且所述空间被所述绝缘包封体填充。
11.根据权利要求8所述的集成扇出型封装件，其特征在于，所述延伸部分与所述集成电路组件的侧壁之间的夹角介于0度至70度范围内。
12.根据权利要求8所述的集成扇出型封装件，其特征在于，所述延伸部分的长度介于10微米至20微米范围内。
13.根据权利要求8所述的集成扇出型封装件，其特征在于，所述延伸部分为框型结构。
14.根据权利要求8所述的集成扇出型封装件，其特征在于，进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
15.一种制作集成扇出型封装件的方法，其特征在于，所述方法包括：
提供包括多个导电端子的集成电路组件；
将所述集成电路组件通过管芯贴合膜安装至载板上；
通过压缩模塑工艺在所述载板上形成绝缘包封体，所述绝缘包封体侧向地密封所述集成电路组件及所述管芯贴合膜，在所述压缩模塑工艺期间形成所述管芯贴合膜的升高的边缘，且所述升高的边缘朝所述集成电路组件的侧壁凸起；以及
在所述集成电路组件及所述绝缘包封体上形成重布线路结构，所述重布线路结构电连接至所述集成电路组件的所述导电端子。
16.根据权利要求15所述的方法，其特征在于，所述压缩模塑工艺使所述管芯贴合膜的所述升高的边缘提升，以从所述载板层离并朝所述集成电路组件的所述侧壁凸起。
17.根据权利要求15所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述升高的边缘沿所述集成电路组件的所述侧壁延伸。
18.根据权利要求15所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述升高的边缘朝所述集成电路组件的所述侧壁凸起，且所述升高的边缘与所述集成电路组件的所述侧壁之间的空间被所述绝缘包封体填充。
19.根据权利要求15所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述升高的边缘朝所述集成电路组件的所述侧壁凸起，且所述升高的边缘与所述集成电路组件的所述侧壁之间的夹角介于0度至70度范围内。
20.根据权利要求15所述的方法，其特征在于，进一步包括：
在形成所述绝缘包封体之前在所述载板上形成多个贯穿绝缘体的导电通孔，其中在形成所述多个贯穿绝缘体的导电通孔及所述重布线路结构之后所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
21.一种集成扇出型封装件，其特征在于，包括：
管芯贴合膜；
集成电路组件，配置于所述管芯贴合膜上，其中所述管芯贴合膜具有升高部位，所述升高部位朝所述集成电路组件的侧壁凸起，且所述升高部位的至少部分在沿着其延伸方向上具有均一厚度；
绝缘包封体，包覆所述升高部位及所述集成电路组件，其中在所述管芯贴合膜与所述集成电路组件的所述侧壁之间具有空间，且所述空间被所述绝缘包封体的部分所填充；以及
重布线路结构，配置于所述集成电路组件及所述绝缘包封体上，所述重布线路结构电连接至所述集成电路组件。
22.根据权利要求21所述的集成扇出型封装件，其特征在于，所述升高部位与所述集成电路组件的所述侧壁之间的夹角小于70度。
23.根据权利要求21所述的集成扇出型封装件，其特征在于，在所述升高部位沿着所述延伸方向的长度介于10微米至20微米范围内。
24.根据权利要求21所述的集成扇出型封装件，其特征在于，所述升高部位包括环绕所述集成电路组件的所述侧壁的框型结构。
25.根据权利要求21所述的集成扇出型封装件，其特征在于，进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
26.一种集成扇出型封装件，其特征在于，包括：
集成电路组件；
管芯贴合膜，以粘合方式贴合至所述集成电路组件的底表面，所述管芯贴合膜包括管芯贴合部分及连接至所述管芯贴合部分的延伸部分，所述延伸部分从所述管芯贴合部分的边缘向上及向外延伸，其中所述延伸部分包括沿着其延伸方向上具有均一厚度的部位；
绝缘包封体，侧向地密封所述管芯贴合膜及所述集成电路组件，其中在所述管芯贴合膜与所述集成电路组件的侧壁之间具有空间，且所述空间被所述绝缘包封体的部分所填充；以及
重布线路结构，配置于所述集成电路组件及所述绝缘包封体上，所述重布线路结构电连接至所述集成电路组件。
27.根据权利要求26所述的集成扇出型封装件，其特征在于，所述集成电路组件的所述底表面的面积与所述管芯贴合部分的面积相同。
28.根据权利要求26所述的集成扇出型封装件，其特征在于，所述管芯贴合部分与所述延伸部分不共面。
29.根据权利要求26所述的集成扇出型封装件，其特征在于，所述延伸部分与所述集成电路组件的所述侧壁之间的夹角小于70度。
30.根据权利要求26所述的集成扇出型封装件，其特征在于，所述延伸部分的长度介于10微米至20微米范围内。
31.根据权利要求26所述的集成扇出型封装件，其特征在于，所述延伸部分包括环绕所述集成电路组件的所述侧壁的框型结构。
32.根据权利要求26所述的集成扇出型封装件，其特征在于，进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
33.一种集成扇出型封装件，其特征在于，包括：
集成电路组件；
管芯贴合膜，以粘合方式贴合至所述集成电路组件的底表面，所述管芯贴合膜包括管芯贴合部分及连接至所述管芯贴合部分的延伸部分，所述延伸部分从所述管芯贴合部分的边缘向上及向外延伸，其中所述延伸部分包括沿着其延伸方向上具有均一厚度的部位；
绝缘包封体，侧向地密封所述管芯贴合膜及所述集成电路组件，所述绝缘包封体的厚度与所述集成电路组件以及所述管芯贴合部分的总厚度相同，所述管芯贴合部分的底表面与所述绝缘包封体的底表面共面，其中在所述延伸部分与所述集成电路组件的侧壁之间具有空间，且所述空间被所述绝缘包封体的部分所填充；以及
重布线路结构，配置于所述集成电路组件及所述绝缘包封体上，所述重布线路结构电连接至所述集成电路组件。
34.根据权利要求33所述的集成扇出型封装件，其特征在于，所述延伸部分与所述集成电路组件的所述侧壁之间的夹角小于70度。
35.根据权利要求33所述的集成扇出型封装件，其特征在于，所述延伸部分的长度介于10微米至20微米范围内。
36.根据权利要求33所述的集成扇出型封装件，其特征在于，所述延伸部分包括框型结构。
37.根据权利要求33所述的集成扇出型封装件，其特征在于，进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
38.根据权利要求33所述的集成扇出型封装件，其特征在于，所述集成电路组件的顶表面与所述集成电路组件的所述底表面相对，所述集成电路组件的所述顶表面与所述绝缘包封体的顶表面共面，且所述重布线路结构所述集成电路组件的所述顶表面与所述绝缘包封体的所述顶表面上。
39.根据权利要求33所述的集成扇出型封装件，其特征在于，所述延伸部分的顶表面与所述延伸部分的底表面平行。
40.根据权利要求33所述的集成扇出型封装件，其特征在于，所述延伸部分从所述绝缘包封体的所述底表面延伸至所述绝缘包封体中且嵌于所述绝缘包封体中。
41.一种制作集成扇出型封装件的方法，其特征在于，所述方法包括：
将集成电路组件通过管芯贴合膜贴附至载板上；
在所述载板上形成绝缘包封体以侧向地密封所述集成电路组件及所述管芯贴合膜，其中在形成所述绝缘包封体期间，所述管芯贴合膜的升高部位会升高，且所述升高部位朝所述集成电路组件的侧壁凸起；以及
在所述集成电路组件及所述绝缘包封体上形成重布线路结构，所述重布线路结构电连接至所述集成电路组件。
42.根据权利要求41所述的方法，其特征在于，所述绝缘包封体通过压缩模塑工艺形成在所述载板上，且所述压缩模塑工艺使所述管芯贴合膜的所述升高部位提升，以从所述载板层离并朝所述集成电路组件的所述侧壁凸起。
43.根据权利要求42所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述升高部位沿所述集成电路组件的所述侧壁延伸。
44.根据权利要求42所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述升高部位朝所述集成电路组件的所述侧壁凸起，且所述升高部位与所述集成电路组件的所述侧壁之间的空间被所述绝缘包封体的部分所填充。
45.根据权利要求42所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述升高部位朝所述集成电路组件的所述侧壁凸起，且所述升高部位与所述集成电路组件的所述侧壁之间的夹角介于0度至70度范围内。
46.根据权利要求41所述的方法，其特征在于，进一步包括：
在形成所述绝缘包封体之前，在所述载板上形成多个贯穿绝缘体的导电通孔，其中在形成所述多个贯穿绝缘体的导电通孔及所述重布线路结构之后所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
47.根据权利要求41所述的方法，其特征在于，在形成所述管芯贴合膜的所述升高部位之前，所述管芯贴合膜的底表面未被所述绝缘包封体覆盖且与所述绝缘包封体的底表面共面。
48.一种制作集成扇出型封装件的方法，其特征在于，所述方法包括：
将集成电路组件通过管芯贴合膜贴附至载板上；
在所述载板上形成绝缘包封体以侧向地密封所述集成电路组件及所述管芯贴合膜，其中所述管芯贴合膜包括与所述集成电路组件接触的管芯贴合部分及连接至所述管芯贴合部分的延伸部分，所述延伸部分从所述管芯贴合部分向上及向外延伸，且所述延伸部分在形成所述绝缘包封体期间提升；以及
在所述集成电路组件及所述绝缘包封体上形成重布线路结构，所述重布线路结构电连接至所述集成电路组件。
49.根据权利要求48所述的方法，其特征在于，所述绝缘包封体通过压缩模塑工艺形成在所述载板上，且所述压缩模塑工艺使所述管芯贴合膜的所述延伸部分提升，以从所述载板层离并朝所述集成电路组件的侧壁凸起。
50.根据权利要求49所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述延伸部分沿所述集成电路组件的所述侧壁延伸。
51.根据权利要求49所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述延伸部分朝所述集成电路组件的所述侧壁凸起，且所述延伸部分与所述集成电路组件的所述侧壁之间的空间被所述绝缘包封体的部分所填充。
52.根据权利要求49所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述延伸部分朝所述集成电路组件的所述侧壁凸起，且所述延伸部分与所述集成电路组件的所述侧壁之间的夹角介于0度至70度范围内。
53.根据权利要求48所述的方法，其特征在于，进一步包括：
在形成所述绝缘包封体之前，在所述载板上形成多个贯穿绝缘体的导电通孔，其中在形成所述多个贯穿绝缘体的导电通孔及所述重布线路结构之后所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
54.根据权利要求48所述的方法，其特征在于，所述管芯贴合膜的底表面与所述绝缘包封体的底表面共面。
55.一种制作集成扇出型封装件的方法，其特征在于，所述方法包括：
将集成电路组件通过管芯贴合膜贴附至载板上；
通过压缩模塑工艺在所述载板上形成绝缘包封体以侧向地密封所述集成电路组件及所述管芯贴合膜，其中所述管芯贴合膜的未被所述集成电路组件覆盖的部分从所述载板层离并朝所述集成电路组件的侧壁凸起，以形成所述管芯贴合膜的升高部位；以及
在所述集成电路组件及所述绝缘包封体上形成重布线路结构，所述重布线路结构电连接至所述集成电路组件。
56.根据权利要求55所述的方法，其特征在于，所述压缩模塑工艺使所述管芯贴合膜的所述升高部位朝所述集成电路组件的所述侧壁凸起，且所述部分与所述集成电路组件的所述侧壁之间的空间被所述绝缘包封体的部分所填充。
57.根据权利要求55所述的方法，其特征在于，所述压缩模塑工艺使所述管芯贴合膜的所述升高部位朝所述集成电路组件的所述侧壁凸起，且所述升高部位与所述集成电路组件的所述侧壁之间的第一空间以及所述载板与所述升高部位之间的第二空间被所述绝缘包封体的多个部分所填充。
58.根据权利要求55所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述部分朝所述集成电路组件的所述侧壁凸起，且所述管芯贴合膜的所述升高部位沿所述集成电路组件的所述侧壁延伸。
59.根据权利要求55所述的方法，其特征在于，所述压缩模塑工艺使得所述管芯贴合膜的所述部分朝所述集成电路组件的所述侧壁凸起，且所述升高部位与所述集成电路组件的所述侧壁之间的夹角介于0度至70度范围内。
60.根据权利要求55所述的方法，其特征在于，进一步包括：
在形成所述绝缘包封体之前，在所述载板上形成多个贯穿绝缘体的导电通孔，其中在形成所述多个贯穿绝缘体的导电通孔及所述重布线路结构之后所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
61.一种集成扇出型封装件，其特征在于，包括：
管芯贴合膜；
集成电路组件，配置于所述管芯贴合膜上，
其中所述管芯贴合膜具有升高部位，所述升高部位朝所述集成电路组件的侧壁凸起；
绝缘包封体，包覆所述升高部位及所述集成电路组件，其中在所述升高部位与所述集成电路组件的所述侧壁之间具有空间，且所述空间被所述绝缘包封体的部分所填充；以及
重布线路结构，配置于所述集成电路组件及所述绝缘包封体上，所述重布线路结构电连接至所述集成电路组件，其中在沿着所述重布线路结构与所述绝缘包封体的堆栈方向上所述升高部位与所述重布线路结构重迭，在所述升高部位沿着延伸方向的长度介于10微米至20微米范围内，所述升高部位包括环绕所述集成电路组件的所述侧壁的框型结构。
62.根据权利要求61所述的集成扇出型封装件，其特征在于，所述升高部位与所述集成电路组件的所述侧壁之间的夹角小于70度。
63.根据权利要求61所述的集成扇出型封装件，其特征在于，进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
64.一种集成扇出型封装件，其特征在于，包括：
介电层；
集成电路组件，配置于所述介电层上；
管芯贴合膜，以粘合方式贴合至所述集成电路组件的底表面至所述介电层，所述管芯贴合膜包括管芯贴合部分及连接至所述管芯贴合部分的延伸部分，在沿着所述管芯贴合膜与所述集成电路组件的堆栈方向上，所述管芯贴合部分的投影面积与所述集成电路组件的投影面积相等，所述延伸部分从所述管芯贴合部分的边缘向上及向外延伸，其中所述延伸部分的至少部分与所述介电层接触；以及
绝缘包封体，侧向地密封所述管芯贴合膜及所述集成电路组件，其中在所述管芯贴合膜与所述集成电路组件的侧壁之间具有空间，且所述空间被所述绝缘包封体的部分所填充；以及
重布线路结构，配置于所述集成电路组件及所述绝缘包封体上，所述重布线路结构电连接至所述集成电路组件，所述延伸部分与所述集成电路组件的所述侧壁之间的夹角小于70度，所述延伸部分沿著其延伸方向的长度介于10微米至20微米范围内。
65.根据权利要求64所述的集成扇出型封装件，其特征在于，所述管芯贴合部分与所述延伸部分不共面。
66.根据权利要求64所述的集成扇出型封装件，其特征在于，所述延伸部分包括环绕所述集成电路组件的所述侧壁的框型结构。
67.根据权利要求64所述的集成扇出型封装件，其特征在于，进一步包括嵌于所述绝缘包封体中的多个贯穿绝缘体的导电通孔，其中所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构。
68.根据权利要求67所述的集成扇出型封装件，其特征在于，所述延伸部分从所述管芯贴合部分的边缘向上及向外朝向所述多个贯穿绝缘体的导电通孔延伸。
69.一种集成扇出型封装件，其特征在于，包括：
集成电路组件；
管芯贴合膜，以粘合方式贴合至所述集成电路组件的底表面，所述管芯贴合膜包括管芯贴合部分及连接至所述管芯贴合部分的延伸部分，所述延伸部分从所述管芯贴合部分的边缘向上及向外延伸；
绝缘包封体，侧向地密封所述管芯贴合膜及所述集成电路组件，所述绝缘包封体的厚度与所述集成电路组件以及所述管芯贴合部分的总厚度相同，所述管芯贴合部分的底表面与所述绝缘包封体的底表面共面，其中在所述延伸部分与所述集成电路组件的侧壁之间具有空间，且所述空间被所述绝缘包封体的部分所填充；
重布线路结构，配置于所述集成电路组件及所述绝缘包封体上，所述重布线路结构电连接至所述集成电路组件；以及
多个贯穿绝缘体的导电通孔，嵌于所述绝缘包封体中，其中所述多个贯穿绝缘体的导电通孔电连接至所述重布线路结构，所述延伸部分与所述集成电路组件的所述侧壁之间的夹角小于70度，所述延伸部分沿着其延伸方向的长度介于10微米至20微米范围内。
70.根据权利要求69所述的集成扇出型封装件，其特征在于，所述延伸部分包括框型结构。
71.根据权利要求69所述的集成扇出型封装件，其特征在于，所述延伸部分从所述管芯贴合部分的边缘向上及向外朝向所述多个贯穿绝缘体的导电通孔延伸。
72.根据权利要求69所述的集成扇出型封装件，其特征在于，所述集成电路组件的顶表面与所述集成电路组件的所述底表面相对，所述集成电路组件的所述顶表面与所述绝缘包封体的顶表面共面，且所述重布线路结构所述集成电路组件的所述顶表面与所述绝缘包封体的所述顶表面上。
73.根据权利要求69所述的集成扇出型封装件，其特征在于，所述延伸部分的顶表面与所述延伸部分的底表面平行。
74.根据权利要求69所述的集成扇出型封装件，其特征在于，所述延伸部分从所述绝缘包封体的所述底表面延伸至所述绝缘包封体中且嵌于所述绝缘包封体中。
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US20180096942A1 (en) 2018-04-05
US9837359B1 (en) 2017-12-05
US20190131243A1 (en) 2019-05-02
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US11282796B2 (en) 2022-03-22
US20180096943A1 (en) 2018-04-05
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US10790235B2 (en) 2020-09-29

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