TW201813022A - 積體扇出型封裝件 - Google Patents

積體扇出型封裝件 Download PDF

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Publication number
TW201813022A
TW201813022A TW105140174A TW105140174A TW201813022A TW 201813022 A TW201813022 A TW 201813022A TW 105140174 A TW105140174 A TW 105140174A TW 105140174 A TW105140174 A TW 105140174A TW 201813022 A TW201813022 A TW 201813022A
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Taiwan
Prior art keywords
integrated circuit
conductive
circuit element
layer
die bonding
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TW105140174A
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English (en)
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TWI718219B (zh
Inventor
邱銘彥
張兢夫
黃信傑
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台灣積體電路製造股份有限公司
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Publication of TW201813022A publication Critical patent/TW201813022A/zh
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Publication of TWI718219B publication Critical patent/TWI718219B/zh

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Abstract

一種積體扇出型封裝件，其包括晶粒貼合膜、積體電路元件、絕緣包封體及重佈線路結構。積體電路元件配置於晶粒貼合膜上且包括多個導電端子。晶粒貼合膜包括升高的邊緣，升高的邊緣朝積體電路元件的側壁凸起。絕緣包封體包覆升高的邊緣及積體電路元件。重佈線路結構配置於積體電路元件及絕緣包封體上，且重佈線路結構電連接至積體電路元件的導電端子。還提供一種製作積體扇出型封裝件的方法。

Description

積體扇出型封裝件
本發明實施例是有關於一種積體扇出型封裝件。
由於不同電子元件(例如是電晶體、兩極真空管、電阻、電容等)的積體密度持續地增進，半導體工業經歷了快速成長。大部分而言，積體密度的增進是來自於最小特徵尺寸(feature size)上不斷地縮減，這允許更多的較小元件整合到一給定區域內。較小的電子元件會需要面積比以往的封裝更小的較小封裝。半導體元件的其中一部分較小型式的封裝包括有四面扁平封裝(quad flat packages，QFPs)、接腳柵格陣列(pin grid array，PGA)封裝、球狀柵格陣列(ball grid array，BGA)封裝等等。
目前，積體扇出型封裝件因其緊湊性而正變得日漸流行。對於未來的封裝件來說，積體扇出型封裝件所提供的提高的可佈線性（routability）及可靠性（reliability）是關鍵因素。
本發明的實施例提供一種積體扇出型封裝件，積體扇出型封裝件包括晶粒貼合膜、積體電路元件、絕緣包封體及重佈線路結構。積體電路元件配置於晶粒貼合膜上且包括多個導電端子。晶粒貼合膜包括升高的邊緣，升高的邊緣朝積體電路元件的側壁凸起。絕緣包封體包覆住升高的邊緣及積體電路元件。重佈線路結構配置於積體電路元件及絕緣包封體上，且重佈線路結構電連接至積體電路元件的導電端子。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
圖1至圖11說明製作根據某些實施例的積體扇出型封裝件的製程流程，且圖12是說明根據某些實施例的疊層封裝（POP）結構的剖視圖。
參照圖1，提供包括排列成陣列的多個晶粒（或積體電路元件）200的晶圓100。在對晶圓100進行晶圓切割（wafer dicing）製程之前，晶圓100中的積體電路元件200是彼此連接的。在某些實施例中，晶圓100包括半導體基底110、形成在半導體基底110上的多個導電墊120及鈍化層130。鈍化層130形成在半導體基底110上且界定多個接觸開口132，以局部地暴露出導電墊120。半導體基底110上的導電墊120經由接觸開口132從鈍化層130局部地暴露出。半導體基底110可為矽基底，矽基底包括形成在矽基底中的主動元件（例如，電晶體等）及被動元件（例如，電阻器、電容器、電感器等）；導電墊120可為鋁墊、銅墊或其他適合的金屬墊；且鈍化層130可為氧化矽層、氮化矽層、氮氧化矽層或由其他適合的介電材料形成的介電層。
如圖1中所示，在某些實施例中，晶圓100可進一步包括形成在鈍化層130上的後鈍化（post-passivation）層140。後鈍化層140覆蓋鈍化層130且具有多個接觸開口142。導電墊120被後鈍化層140局部地覆蓋但從接觸開口132暴露出。換句話說，導電墊120被後鈍化層140的接觸開口142局部地暴露出。後鈍化層140可為聚醯亞胺（polyimide，PI）層、聚苯並惡唑（polybenzoxazole，PBO）層或由其他適合的聚合物形成的介電層。
參照圖2，在導電墊120上形成多個導電柱或導電孔150。在某些實施例中，導電柱或導電孔150電鍍在導電墊120上。例如，首先將晶種層（例如，Ti/Cu晶種層）濺鍍至後鈍化層140及被接觸開口142暴露出的導電墊120上；接著，藉由微影製程（photolithography）在晶種層上形成用於暴露出導電墊120的圖案化光阻層（圖中未示出）；接著將包括形成在晶圓100上的圖案化光阻層的晶圓100浸入至電鍍溶液中，進而使得導電柱或導電孔150電鍍在與導電墊120對應的晶種層上。在形成電鍍導電柱或導電孔150之後，剝除圖案化光阻層。此後，利用導電柱或導電孔150作為硬罩幕，例如藉由刻蝕（etching）移除晶種層的未被導電柱或導電孔150覆蓋的部分直至暴露出後鈍化層140為止。在某些實施例中，導電柱或導電孔150為銅柱或銅孔。
參照圖3，在形成導電柱或導電孔150之後，在後鈍化層140上形成保護層160，以覆蓋導電柱或導電孔150。在某些實施例中，保護層160可為具有足以包覆及保護導電柱或導電孔150的厚度的聚合物層。例如，保護層160可為聚苯並惡唑（PBO）層、聚醯亞胺（PI）層或其他適合的聚合物。在某些替代實施例中，保護層160可由無機材料製成。
參照圖3及圖4，在形成保護層160之後，對晶圓100的後表面進行背側研磨（back side grinding）製程。在背側研磨製程期間，研磨半導體基底110，進而使得形成包括半導體基底110’的薄化晶圓100’。接著，將薄化晶圓100’藉由晶粒貼合膜180貼合至支撐基底SUB上。應注意，在半導體基底110的厚度足夠薄時，背側研磨製程為選擇性的製程。換句話說，當半導體基底110的厚度對於製造者來說可接受時，可將晶圓100藉由晶粒貼合膜180貼合至支撐基底SUB上，且在晶粒貼合製程之前無需進行背側研磨製程。
參照圖5，在進行上述晶粒貼合或晶粒結合製程之後，對薄化晶圓100’（或圖3中所示的晶圓100）進行晶圓切割製程，進而使得薄化晶圓100’（或圖3中所示的晶圓100）的積體電路元件200彼此單體化。如圖5中所示，經單體化的積體電路元件200各自包括半導體基底110a、形成在半導體基底110a上的導電墊120、鈍化層130a、後鈍化層140a、導電柱或導電孔150及保護層160a。導電墊120及電連接至導電墊120的導電孔150可被視作積體電路元件200的導電端子。半導體基底110a、鈍化層130a、後鈍化層140a及保護層160a的材料與半導體基底110、鈍化層130、後鈍化層140及保護層160的材料相似。因此，省略了對半導體基底110a、鈍化層130a、後鈍化層140a及保護層160a的詳細說明。
在晶圓切割製程期間，對薄化晶圓100’下方的晶粒貼合膜180進行圖案化或切割，進而使得在經單體化的積體電路元件200下方形成多個晶粒貼合膜180’。應注意，晶粒貼合膜180’的側壁與積體電路元件200的側壁實質上對齊。
如圖4及圖5中所示，在背側研磨製程及晶圓切割製程期間，保護層160及160a可完善地保護積體電路元件200的導電端子（例如，導電墊120及導電孔150）。另外，可保護積體電路元件200的導電墊120及導電孔150不被例如積體電路元件200的拾取及放置（pick-up and placing）製程、模塑（molding）製程等後續進行的製程損壞。
參照圖6，在形成積體電路元件200及晶粒貼合膜180’之後，提供其上已形成有剝離（de-bonding）層DB及介電層DI的載板C，其中剝離層DB處於載板C與介電層DI之間。在某些實施例中，載板C是玻璃基底，剝離層DB是形成在玻璃基底上的光-熱轉換（light-to-heat conversion，LTHC）釋放層，且介電層DI是形成在剝離層DB上的聚苯並惡唑（PBO）層。
在提供其上已形成有剝離層DB及介電層DI的載板C之後，在介電層DI上形成多個貫穿絕緣體的導電通孔TIV。在某些實施例中，多個貫穿絕緣體的導電通孔TIV是藉由微影、電鍍及光阻剝除（photoresist stripping）製程形成。例如，貫穿絕緣體的導電通孔TIV包括銅柱（copper post）。
如圖5及圖6中所示，在某些實施例中，可將其中一個包括有導電端子（例如，導電墊120及導電孔150）及形成在導電端子上的保護層160a的積體電路元件200拾取且放置在介電層DI上。將積體電路元件200藉由晶粒貼合膜180’貼合（或黏合）在介電層DI上。應注意，在將積體電路元件200拾取且放置在介電層DI上之後，晶粒貼合膜180’可側向地延伸且晶粒貼合膜180’所佔據的面積增大。換句話說，晶粒貼合膜180’的側壁並不與積體電路元件200的側壁對齊。因施加在積體電路元件200上的壓力導致的晶粒貼合膜180’的膨脹對應於晶粒貼合膜180’的體積（或厚度）及施加在積體電路元件200上的壓力。
在某些替代實施例中，可將多於一個積體電路元件200拾取且放置在介電層DI上，其中放置在介電層DI上的積體電路元件200可排列成陣列。當放置在介電層DI上的積體電路元件200排列成陣列時，可將貫穿絕緣體的導電通孔TIV歸類成多個群組。積體電路元件200的數目可對應於貫穿絕緣體的導電通孔TIV的群組的數目。
如圖6中所示，在所示實施例中，保護層160a的頂表面低於貫穿絕緣體的導電通孔TIV的頂表面，且保護層160a的頂表面高於導電柱或導電孔150的頂表面。然而，本發明的實施例不限於此。在某些替代實施例中，保護層160a的頂表面可與貫穿絕緣體的導電通孔TIV的頂表面實質上對齊，且保護層160a的頂表面高於導電柱或導電孔150的頂表面。
如圖6中所示，可在形成貫穿絕緣體的導電通孔TIV之後，將積體電路元件200中的一個或多個拾取且放置在介電層DI上。然而，本發明的實施例不限於此。在某些替代實施例中，可在形成貫穿絕緣體的導電通孔TIV之前，將積體電路元件200中的一個或多個拾取且放置在介電層DI上。
參照圖7，藉由例如壓縮模塑（compression molding）製程在介電層DI上形成絕緣材料210，以包覆積體電路元件200、晶粒貼合膜180’及貫穿絕緣體的導電通孔TIV。積體電路元件200的導電柱或導電孔150及保護層160a被絕緣材料210包覆且完善地保護。換句話說，積體電路元件200的導電柱或導電孔150及保護層160a未被絕緣材料210顯露出且被絕緣材料210完善地保護。在某些實施例中，絕緣材料210包括環氧樹脂（epoxy）或其他適合的樹脂。
如圖7中所示，在壓縮模塑製程期間，從晶粒貼合膜180’的側向突出的部分形成升高的邊緣182，升高的邊緣182朝積體電路元件200的側壁凸起或折疊。在進行壓縮模塑製程之後，晶粒貼合膜180’的升高的邊緣182及積體電路元件200會被絕緣材料210包覆。因此，晶粒貼合膜180’可包括晶粒貼合部分184及連接至晶粒貼合部分184的延伸部分182（即，升高的邊緣182），其中積體電路元件200直接安裝在晶粒貼合部分184上，且延伸部分182（即，升高的邊緣182）從晶粒貼合部分184的邊緣向上及向外延伸。延伸部分182（即，升高的邊緣182）可為連接至晶粒貼合部分184的框型結構（或框架）。
應注意，在壓縮模塑製程中使用的模塑化合物將晶粒貼合膜180’的延伸部分182（即，升高的邊緣182）提升以從載板C上的介電層DI層離（delaminate），進而使得延伸部分182（即，升高的邊緣182）可朝積體電路元件200的側壁凸起。延伸部分182（即，升高的邊緣182）與積體電路元件200的側壁之間產生空間，且空間會被絕緣材料210所填充。在某些實施例中，延伸部分182（即，升高的邊緣182）被模塑化合物提升，延伸部分182（即，升高的邊緣182）與積體電路元件200的側壁之間的夾角q介於約0度至約70度範圍內，且延伸部分182（即，升高的邊緣182）的長度L介於例如約10微米至約20微米範圍內。在某些實施例中，晶粒貼合膜180’的延伸部分182（即，升高的邊緣182）可增大晶粒貼合膜180’與絕緣材料210的接觸面積且增強晶粒貼合膜180’與絕緣材料210之間的黏合，進而可降低晶粒貼合膜180’與絕緣材料210之間發生層離的可能性。晶粒貼合膜180’的夾角q與壓縮模塑製程的壓力分佈相關。換句話說，晶粒貼合膜180’的夾角q是壓縮模塑製程的壓力分佈的指標。
延伸部分182（即，升高的邊緣182）與積體電路元件200的側壁之間的夾角q與壓縮模塑製程的參數（例如，壓力、用於形成絕緣材料210的模（mold）的形狀等等）相關。此外，延伸部分182（即，升高的邊緣182）的長度L與在拾取及放置製程期間施加在積體電路元件200上的按壓力相關。換句話說，延伸部分182（即，升高的邊緣182）的長度L與因上述按壓力導致的側向膨脹相關。
在某些替代實施例中，如圖13中所示，晶粒貼合膜180’的延伸部分182（即，升高的邊緣182）可沿積體電路元件200的側壁延伸且可接觸積體電路元件200的側壁。換句話說，延伸部分182（即，升高的邊緣182）與積體電路元件200的側壁之間幾乎不具有空間。
參照圖8，研磨絕緣材料210直至暴露出導電柱或導電孔150（即，導電端子）的頂表面、貫穿絕緣體的導電通孔TIV的頂表面及保護層160a的頂表面為止，以形成絕緣包封體210’。在某些實施例中，藉由機械研磨製程及/或化學機械研磨（chemical mechanical polishing，CMP）製程來研磨絕緣材料210。在絕緣材料210的研磨製程期間，研磨保護層160a的部分以形成保護層160a’。在某些實施例中，在絕緣材料210及保護層160a的機械研磨製程期間，也研磨貫穿絕緣體的導電通孔TIV的部分。
如圖8中所示，絕緣包封體210’側向地包覆晶粒貼合膜180’的延伸部分182（即，升高的邊緣182）及積體電路元件200，且絕緣包封體210’被貫穿絕緣體的導電通孔TIV穿透。換句話說，積體電路元件200、晶粒貼合膜180’及貫穿絕緣體的導電通孔TIV嵌於絕緣包封體210’中。
參照圖9，在形成絕緣包封體210’及保護層160a’之後，在貫穿絕緣體的導電通孔TIV的頂表面、絕緣包封體210’的頂表面、導電孔150的頂表面及保護層160a’的頂表面上形成電連接至積體電路元件200的導電柱或導電孔150的重佈線路結構220。所製作的重佈線路結構220會與位於其下的一個或多個導電端子電連接。以下搭配圖9詳細闡述重佈線路結構220。
參照圖9，重佈線路結構220包括交替堆疊的多個層間介電層（inter-dielectric layer）222及多個重佈線導電層224，且重佈線導電層224電連接至積體電路元件200的導電孔150及嵌於絕緣包封體210’中的貫穿絕緣體的導電通孔TIV。如圖9中所示，在某些實施例中，導電孔150的頂表面及貫穿絕緣體的導電通孔TIV的頂表面接觸重佈線路結構220。導電孔150的頂表面及貫穿絕緣體的導電通孔TIV的頂表面被最底部層間介電層222局部地覆蓋。此外，最頂部重佈線導電層224包括多個墊。在某些實施例中，上述墊包括用於導電球安裝（ball mount）的多個球下金屬（under-ball metallurgy，UBM）圖案224a及/或用於安裝被動元件的至少一個連接墊224b。球下金屬圖案224a及連接墊224b的數目在本發明的實施例中並無限制。
如圖9中所示，在形成重佈線路結構220之後，在球下金屬圖案224a上放置多個導電球230，且在連接墊224b上安裝多個被動元件240。在某些實施例中，可藉由植球（ball placement）製程在球下金屬圖案224a上放置導電球230且可藉由焊接（soldering）製程在連接墊224b上安裝被動元件240。
參照圖9及圖10，在重佈線路結構220上安裝導電球230及被動元件240之後，從剝離層DB剝離在絕緣包封體210’的頂表面上形成的介電層DI，進而使得介電層DI從載板C分離。在某些實施例中，可藉由UV雷射照射剝離層DB（例如，光-熱轉換釋放層），進而使得介電層DI從載板C脫落（peel）。如圖10中所示，接著將介電層DI圖案化，進而使得形成多個接觸開口O以暴露出貫穿絕緣體的導電通孔TIV的底表面。接觸開口O的數目對應於貫穿絕緣體的導電通孔TIV的數目。在某些實施例中，藉由雷射鑽孔（laser drilling）製程形成介電層DI的接觸開口O。
參照圖11，在介電層DI中形成接觸開口O之後，在貫穿絕緣體的導電通孔TIV的被接觸開口O暴露出的底表面上放置多個導電球250。例如，對導電球250進行回焊以使導電球250與貫穿絕緣體的導電通孔TIV的底表面接合。如圖11中所示，在形成導電球230及導電球250之後，具有雙側端子的積體電路元件200的積體扇出型封裝件製作完成。
參照圖12，接著，提供另一封裝件300。在某些實施例中，封裝件300為例如記憶體裝置。藉由導電球250將封裝件300堆疊在圖11中所示的積體扇出型封裝件上並電連接至積體扇出型封裝件，進而使得疊層封裝（POP）結構製作完成。
在上述實施例中，積體扇出型封裝件的可靠性及良率（yield rate）可藉由具有延伸部分或升高的邊緣的晶粒貼合膜可獲得提昇。
根據本發明的某些實施例，提供積體扇出型封裝件，所述積體扇出型封裝件包括晶粒貼合膜、積體電路元件、絕緣包封體及重佈線路結構。所述積體電路元件配置於所述晶粒貼合膜上且包括多個導電端子。所述晶粒貼合膜包括升高的邊緣，所述升高的邊緣從所述積體電路元件的周邊部分的下方突出地延伸並朝所述積體電路元件的側壁凸起。所述絕緣包封體包覆所述升高的邊緣及所述積體電路元件。所述重佈線路結構配置於所述積體電路元件及所述絕緣包封體上，且所述重佈線路結構電連接至所述積體電路元件的所述導電端子。
在所述積體扇出型封裝件中，所述升高的邊緣沿所述積體電路元件的所述側壁延伸並接觸所述積體電路元件的所述側壁。
在所述積體扇出型封裝件中，在所述升高的邊緣與所述積體電路元件的所述側壁之間具有空間，且所述空間被所述絕緣包封體填充。
在所述積體扇出型封裝件中，所述升高的邊緣與所述積體電路元件的所述側壁之間的夾角介於約0度至約70度範圍內。
在所述積體扇出型封裝件中，所述升高的邊緣的長度介於約10微米至約20微米範圍內。
在所述積體扇出型封裝件中，所述升高的邊緣為框型結構。
所述積體扇出型封裝件進一步包括嵌於所述絕緣包封體中的多個貫穿絕緣體的導電通孔，其中所述貫穿絕緣體的導電通孔電連接至所述重佈線路結構。
根據本發明的替代實施例，提供一種積體扇出型封裝件，所述積體扇出型封裝件包括晶粒貼合膜、積體電路元件、絕緣包封體及重佈線路結構。所述積體電路元件包括多個導電端子。所述晶粒貼合膜以黏合方式貼合至所述積體電路元件的底表面。所述晶粒貼合膜包括與所述積體電路元件接觸的晶粒貼合部分及連接至所述晶粒貼合部分的延伸部分，所述延伸部分從所述晶粒貼合部分向上及向外延伸。所述絕緣包封體側向地包覆所述晶粒貼合膜及所述積體電路元件。所述重佈線路結構配置於所述積體電路元件及所述絕緣包封體上，且所述重佈線路結構電連接至所述積體電路元件的所述導電端子。
在所述積體扇出型封裝件中，所述延伸部分沿所述積體電路元件的所述側壁延伸並接觸所述積體電路元件的所述側壁。
在所述積體扇出型封裝件中，在所述延伸部分與所述積體電路元件的所述側壁之間具有空間，且所述空間被所述絕緣包封體填充。
在所述積體扇出型封裝件中，所述延伸部分與所述積體電路元件的所述側壁之間的夾角介於約0度至約70度範圍內。
在所述積體扇出型封裝件中，所述延伸部分的長度介於約10微米至約20微米範圍內。
在所述積體扇出型封裝件中，所述延伸部分為框型結構。
所述積體扇出型封裝件進一步包括嵌於所述絕緣包封體中的多個貫穿絕緣體的導電通孔，其中所述貫穿絕緣體的導電通孔電連接至所述重佈線路結構。
根據本發明又一些替代實施例，提供一種製作積體扇出型封裝件的方法。所述方法包括以下步驟。提供包括多個導電端子的積體電路元件且將所述積體電路元件藉由晶粒貼合膜安裝至載板上。藉由壓縮模塑製程在所述載板上形成絕緣包封體，其中所述絕緣包封體側向地包覆所述積體電路元件及所述晶粒貼合膜，在所述壓縮模塑製程期間形成所述晶粒貼合膜的升高的邊緣，且所述升高的邊緣朝所述積體電路元件的側壁凸起。在所述積體電路元件及所述絕緣包封體上形成重佈線路結構，且所述重佈線路結構電連接至所述積體電路元件的所述導電端子。
在所述方法中，所述壓縮模塑製程使所述晶粒貼合膜的所述升高的邊緣提升，以從所述載板層離並朝所述積體電路元件的所述側壁凸起。
在所述方法中，所述壓縮模塑製程使得所述晶粒貼合膜的所述升高的邊緣沿所述積體電路元件的所述側壁延伸。
在所述方法中，所述壓縮模塑製程使得所述晶粒貼合膜的所述升高的邊緣朝所述積體電路元件的所述側壁凸起，且所述升高的邊緣與所述積體電路元件的所述側壁之間的空間被所述絕緣包封體填充。
在所述方法中，所述壓縮模塑製程使得所述晶粒貼合膜的所述升高的邊緣朝所述積體電路元件的所述側壁凸起，且所述升高的邊緣與所述積體電路元件的所述側壁之間的夾角介於約0度至約70度範圍內。
所述方法進一步包括：在形成所述絕緣包封體之前在所述載板上形成多個貫穿絕緣體的導電通孔，其中在形成所述貫穿絕緣體的導電通孔及所述重佈線路結構之後所述貫穿絕緣體的導電通孔電連接至所述重佈線路結構。
以上概述了多個實施例的特徵，使本領域具有通常知識者可更佳瞭解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
100‧‧‧晶圓
100’‧‧‧薄化晶圓
110、110’、110a‧‧‧半導體基底
120‧‧‧導電墊
130、130a‧‧‧鈍化層
132、142‧‧‧接觸開口
140、140a‧‧‧後鈍化層
150‧‧‧導電柱或導電孔
160、160a、160a’‧‧‧保護層
180、180’‧‧‧晶粒貼合膜
182‧‧‧升高的邊緣/延伸部分
184‧‧‧晶粒貼合部分
200‧‧‧積體電路元件
210‧‧‧絕緣材料
210’‧‧‧絕緣包封體
220‧‧‧重佈線路結構
222‧‧‧層間介電層
224‧‧‧重佈線導電層
224a‧‧‧球下金屬圖案
224b‧‧‧連接墊
230、250‧‧‧導電球
240‧‧‧被動元件
300‧‧‧封裝件
C‧‧‧載板
DB‧‧‧剝離層
DI‧‧‧介電層
L‧‧‧長度
O‧‧‧接觸開口
SUB‧‧‧支撐基底
TIV‧‧‧貫穿絕緣體的導電通孔
q‧‧‧夾角
圖1至圖11說明製作根據某些實施例的積體扇出型封裝件的製程流程。 圖12是說明根據某些實施例的疊層封裝（package-on-package，POP）結構的剖視圖。 圖13是說明根據某些實施例的晶粒貼合膜的升高的邊緣的放大剖視圖。

Claims (1)

  1. 一種集成扇出型封裝件，包括： 晶粒貼合膜； 積體電路元件，配置於所述晶粒貼合膜上且包括多個導電端子，所述晶粒貼合膜包括升高的邊緣，所述升高的邊緣從所述積體電路元件的周邊部分的下方突出地延伸並朝所述積體電路元件的側壁凸起； 絕緣包封體，包覆所述升高的邊緣及所述積體電路元件；以及 重佈線路結構，配置於所述積體電路元件及所述絕緣包封體上，所述重佈線路結構電連接至所述積體電路元件的所述導電端子。
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