TW201630086A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TW201630086A
TW201630086A TW104104985A TW104104985A TW201630086A TW 201630086 A TW201630086 A TW 201630086A TW 104104985 A TW104104985 A TW 104104985A TW 104104985 A TW104104985 A TW 104104985A TW 201630086 A TW201630086 A TW 201630086A
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package
layer
electronic
package substrate
conductive
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TWI555098B (zh
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陳彥亨
張翊峰
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矽品精密工業股份有限公司
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Priority to CN201510099236.XA priority patent/CN105990270B/zh
Priority to US14/981,364 priority patent/US9589841B2/en
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Abstract

一種電子封裝件之製法，係先提供一封裝結構，其包含具有相對之第一側與第二側的封裝基板、結合於該第一側上之電子元件、及設於該第一側上的複數導電體，再以絕緣包覆層包覆該封裝結構，其中，該絕緣包覆層覆蓋該封裝基板，之後形成線路重佈結構於該絕緣包覆層上，且該線路重佈結構電性連接該些導電體，故該絕緣包覆層之佈設面積無需配合該封裝基板之面積，因而該封裝基板可依需求縮小，使該電子封裝件之寬度得以減小。本發明復提供該電子封裝件。

Description

電子封裝件及其製法
本發明係有關一種封裝技術，尤指一種半導體封裝技術。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂開發出不同的立體封裝技術，例如，扇出式封裝堆疊(Fan Out Package on package，簡稱FO PoP)等，以配合各種晶片上大幅增加之輸入/出埠數量，進而將不同功能之積體電路整合於單一封裝結構，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。
第1圖係為習知用於PoP之半導體封裝件1的剖面示意圖。如第1圖所示，該半導體封裝件1係包括一具有至少一線路層101之封裝基板10，且以覆晶方式結合一半導體元件11於該線路層101上。
具體地，該半導體元件11具有相對之作用面11a與非 作用面11b，該作用面11a具有複數電極墊110，以藉由複數如銲錫凸塊12電性連接該電極墊110與該線路層101，並形成底膠13於該半導體元件11與該線路層101之間，以包覆該些銲錫凸塊12。
再者，形成一封裝膠體14於該封裝基板10上，以包覆該底膠13及該半導體元件11，且形成複數導電通孔17於該封裝膠體14中，以令該導電通孔17外露於該封裝膠體14，俾供結合一如中介板或封裝基板等之電子裝置(圖略)。
然而，習知半導體封裝件1中，於製作該封裝膠體14時，該封裝基板10需作為承載件，使該封裝膠體14之佈設面積需配合該封裝基板10之面積，因而無法縮小該封裝基板10之面積，導致該半導體封裝件1之寬度極大而難以減小，故無法符合輕、薄、短、小的需求。
因此，如何克服習知技術之缺點，實為目前各界亟欲解決之技術問題。
鑒於上述習知技術之缺失，本發明係提供一種電子封裝件，包括：封裝基板，係具有相對之第一側與第二側；電子元件，結合於該封裝基板之第一側上；複數導電體，設於該封裝基板之第一側上；絕緣包覆層，係包覆該封裝基板、該電子元件與該些導電體，且該封裝基板之第二側外露於該絕緣包覆層；以及線路重佈結構，係形成於該絕緣包覆層上，且該線路重佈結構電性連接該些導電體。
本發明復提供一種電子封裝件之製法，包括：提供至少一封裝結構，該封裝結構包含具有相對之第一側與第二側的封裝基板、結合於該第一側上之電子元件、及設於該第一側上的複數導電體；以絕緣包覆層包覆該封裝結構，其中，該絕緣包覆層覆蓋該封裝基板；以及形成線路重佈結構於該絕緣包覆層上，且該線路重佈結構電性連接該些導電體。
前述之製法，復包括於該線路重佈結構上形成一結合層。該結合層之邊緣設有金屬架。復包括先移除該結合層，再進行切單製程。
前述之製法，復包括於形成該線路重佈結構後，進行切單製程。
前述之電子封裝件及其製法，該導電體係為球狀、柱狀或釘狀。
前述之電子封裝件及其製法，該導電體係位於該電子元件之外圍。
前述之電子封裝件及其製法，該線路重佈結構具有至少一介電層、與設於該介電層上之至少一線路重佈層，使該線路重佈層直接電性連接該些導電體。
前述之電子封裝件及其製法，該線路重佈結構具有至少一介電層、設於該介電層上之至少一線路重佈層、與形成於該絕緣包覆層中之複數導電盲孔，以令該線路重佈層藉由該些導電盲孔電性連接該些導電體。
前述之電子封裝件及其製法，該封裝基板之第二側係 外露於該絕緣包覆層，以供形成複數導電元件於該封裝基板之第二側上，並使該些導電元件電性連接該封裝基板。
由上可知，本發明之電子封裝件及其製法，主要藉由先製作該些導電體，再以絕緣包覆層包覆該封裝結構，使該絕緣包覆層覆蓋該封裝基板之側面，並以線路重佈結構取代習知如中介板或封裝基板等之電子裝置，故相較於習知技術，該絕緣包覆層之佈設面積無需配合該封裝基板之面積，因而該封裝基板可依需求縮小，使該電子封裝件之寬度得以減小，以符合輕、薄、短、小的需求。
1‧‧‧半導體封裝件
10,20‧‧‧封裝基板
101,201‧‧‧線路層
11‧‧‧半導體元件
11a,21a‧‧‧作用面
11b,21b‧‧‧非作用面
110,210‧‧‧電極墊
12,22‧‧‧銲錫凸塊
13,23‧‧‧底膠
14‧‧‧封裝膠體
17‧‧‧導電通孔
2‧‧‧電子封裝件
2a‧‧‧封裝結構
20a‧‧‧第一側
20b‧‧‧第二側
20c‧‧‧側面
200,250‧‧‧介電層
21‧‧‧電子元件
24‧‧‧絕緣包覆層
25,25’‧‧‧線路重佈結構
251‧‧‧線路重佈層
252‧‧‧導電盲孔
26‧‧‧導電元件
27‧‧‧導電體
28‧‧‧結合層
29‧‧‧金屬架
30‧‧‧承載板
31‧‧‧離型層
32‧‧‧黏著層
S‧‧‧切割路徑
第1圖係為習知半導體封裝件的剖面示意圖；以及第2A至2F圖係為本發明之電子封裝件之製法的剖面示意圖；其中，第2C’圖係為第2C圖之另一實施方式。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如 「上」、「第一」、「第二」及「側」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供至少一封裝結構2a，再將該封裝結構2a設於一承載板30上。具體地，該封裝結構2a係包括一具有相對之第一側20a與第二側20b之封裝基板20、結合於該第一側20a上之一電子元件21、以及設於該第一側20a上的複數導電體27。
於本實施例中，該封裝基板20包含複數介電層200與複數形成於該介電層200上之線路層201，且該線路層201電性連接該電子元件21與該些導電體27。需注意，圖中僅揭露該第一側20a附近的線路層201，但實際情況，該第二側20b附近及該封裝基板20內部亦具有線路層。
再者，該電子元件21係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，該作用面21a具有複數電極墊210，且該電極墊210以覆晶方式藉由複數如銲錫凸塊22電性連接該線路層201，並形成底膠23於該電子元件21與該線路層201之間，以包覆該些銲錫凸塊22。
又，該導電體27係為如銲球之圓球狀、如銅柱、銲錫凸塊等金屬材之柱狀、或銲線機製作之釘狀(stud)，但不限於此。
另外，該承載板30係為直徑12吋(或300mm)玻璃材質之圓形板體，其上依序以塗佈方式形成有一離型層31與一黏著層32，且該黏著層22用以黏著該封裝結構2a之封裝基板20之第二側20b。
如第2B圖所示，形成一絕緣包覆層24於該承載板30上，以包覆該封裝結構2a。
於本實施例中，該絕緣包覆層24覆蓋該封裝基板20之側面20c，其中，該側面20c係鄰接該第一側20a與第二側20b。
再者，該絕緣包覆層24可用如環氧樹脂之封裝膠體以壓合(lamination)或模壓(molding)之方式形成之。
如第2C圖所示，形成一線路重佈結構25於該絕緣包覆層24上，且該線路重佈結構25電性連接該些導電體27。
於本實施例中，該線路重佈結構25係包括至少一介電層250與設於該介電層251上之至少一線路重佈層251。
再者，該線路重佈層251係直接電性連接該導電體27。
或者，如第2C’圖所示，該線路重佈結構25’可於該絕緣包覆層24中形成有複數導電盲孔252，以令該線路重佈層251藉由該些導電盲孔252電性連接該些導電體27。
又，形成該線路重佈層251之材質係為銅，且形成該介電層250之材質係為光阻材料或聚對二唑苯 (Polybenzoxazole，簡稱PBO)。
如第2D圖所示，接續第2C圖之製程，先於該線路重佈結構25上形成一如膠帶(Tape)之結合層28，再移除該承載板30及其黏著層32。
於本實施例中，以紫外光或雷射穿透該承載板30後，直接照射該離型層31(其為感光材)，使該離型層31感光消失，即可移除該承載板30。
再者，該結合層28之邊緣設有金屬架29(如鐵圈)，以避免該結合層28發生翹曲。
如第2E圖所示，形成複數如銲球之導電元件26於該封裝基板20之第二側20b上，以供後續接置另一封裝結構或其它電子裝置(如電路板或中介板)，且該些導電元件26電性連接該封裝基板20之線路層201。
如第2F圖所示，沿如第2E圖所示之切割路徑S進行切單製程，且一併移除該金屬架29，再將該線路重佈結構25上之該結合層28移除，以完成本發明之電子封裝件2。
因此，本發明之製法藉由先將該些導電體27製作於該封裝基板20上，再以該絕緣包覆層24包覆該封裝結構2a，使該絕緣包覆層24覆蓋該封裝基板20之側面20c，故該絕緣包覆層24之佈設面積係配合承載板30之面積，而無需配合該封裝基板20之面積，因而該封裝基板20可依需求縮小，使該電子封裝件2之寬度得以減小，以符合輕、薄、短、小的需求。
再者，本發明之製法以線路重佈結構25,25’取代習知 如中介板或封裝基板等之電子裝置，因而該封裝基板20可依需求縮小，使該電子封裝件2之寬度得以減小，以符合輕、薄、短、小的需求。
本發明提供一種電子封裝件2，其包括：一封裝基板20、一電子元件21、複數導電體27、一絕緣包覆層24以及一線路重佈結構25,25’。
所述之封裝基板20係具有相對之第一側20a與第二側20b。
所述之電子元件21係結合於該封裝基板20之第一側20a上。
所述之導電體27設於該封裝基板20之第一側20a上並位於該電子元件21之外圍，且該導電體27係為金屬柱。
所述之絕緣包覆層24係包覆該封裝基板20、該電子元件21與該些導電體27，其中，該絕緣包覆層24覆蓋該封裝基板20之側面20c，且令該封裝基板20之第二側20b外露於該絕緣包覆層24。
所述之線路重佈結構25,25’係形成於該絕緣包覆層24上，且該線路重佈結構25,25’電性連接該些導電體27。
於一實施例中，該線路重佈結構25具有至少一介電層250與設於該介電層250上之至少一線路重佈層251，使該線路重佈層251直接電性連接該導電體27。
於一實施例中，該線路重佈結構25’具有至少一介電層250、設於該介電層250上之至少一線路重佈層251與形成於該絕緣包覆層24中之複數導電盲孔252，以令該線路重 佈層251藉由該些導電盲孔252電性連接該些導電體27。
於一實施例中，該電子封裝件2復包括形成於該封裝基板20之第二側20b上的複數導電元件26，且該些導電元件26電性連接該些導電體27。
綜上所述，本發明之電子封裝件及其製法，係藉由先製作該些導電體於該封裝基板上，再以該絕緣包覆層包覆該封裝結構，使該絕緣包覆層覆蓋該封裝基板之側面，並以線路重佈結構取代習知如中介板或封裝基板等之電子裝置，故該絕緣包覆層之佈設面積無需配合該封裝基板之面積，因而該封裝基板可依需求縮小，使該電子封裝件之寬度得以減小，以符合輕、薄、短、小的需求。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧封裝基板
20a‧‧‧第一側
20b‧‧‧第二側
20c‧‧‧側面
201‧‧‧線路層
21‧‧‧電子元件
24‧‧‧絕緣包覆層
25‧‧‧線路重佈結構
26‧‧‧導電元件
27‧‧‧導電體

Claims (16)

  1. 一種電子封裝件，包括：封裝基板，係具有相對之第一側與第二側；電子元件，結合於該封裝基板之第一側上；複數導電體，設於該封裝基板之第一側上；絕緣包覆層，係包覆該封裝基板、該電子元件與該些導電體，且該封裝基板之第二側外露於該絕緣包覆層；以及線路重佈結構，係形成於該絕緣包覆層上，且該線路重佈結構電性連接該些導電體。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該導電體係為球狀、柱狀或釘狀。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該導電體係位於該電子元件之外圍。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該線路重佈結構具有至少一介電層、與設於該介電層上之至少一線路重佈層，使該線路重佈層直接電性連接該些導電體。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該線路重佈結構具有至少一介電層、設於該介電層上之至少一線路重佈層、與形成於該絕緣包覆層中之複數導電盲孔，以令該線路重佈層藉由該些導電盲孔電性連接該些導電體。
  6. 如申請專利範圍第1項所述之電子封裝件，復包括形 成於該封裝基板之第二側上的複數導電元件，且該些導電元件電性連接該些導電體。
  7. 一種電子封裝件之製法，包括：提供至少一封裝結構，該封裝結構包含具有相對之第一側與第二側的封裝基板、結合於該第一側上之電子元件、及設於該第一側上的複數導電體；以絕緣包覆層包覆該封裝結構，其中，該絕緣包覆層覆蓋該封裝基板；以及形成線路重佈結構於該絕緣包覆層上，且該線路重佈結構電性連接該些導電體。
  8. 如申請專利範圍第7項所述之電子封裝件之製法，其中，該導電體係為球狀、柱狀或釘狀。
  9. 如申請專利範圍第7項所述之電子封裝件之製法，其中，該導電體係位於該電子元件之外圍。
  10. 如申請專利範圍第7項所述之電子封裝件之製法，其中，該線路重佈結構具有至少一介電層、與設於該介電層上之至少一線路重佈層，使該線路重佈層直接電性連接該些導電體。
  11. 如申請專利範圍第7項所述之電子封裝件之製法，其中，該線路重佈結構具有至少一介電層、設於該介電層上之至少一線路重佈層、與形成於該絕緣包覆層中之複數導電盲孔，以令該線路重佈層藉由該些導電盲孔電性連接該些導電體。
  12. 如申請專利範圍第7項所述之電子封裝件之製法，其 中，該封裝基板之第二側係外露於該絕緣包覆層，以供形成複數導電元件於該封裝基板之第二側上，並使該些導電元件電性連接該封裝基板。
  13. 如申請專利範圍第7項所述之電子封裝件之製法，復包括於該線路重佈結構上形成一結合層。
  14. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該結合層之邊緣設有金屬架。
  15. 如申請專利範圍第13項所述之電子封裝件之製法，復包括先移除該結合層，再進行切單製程。
  16. 如申請專利範圍第7項所述之電子封裝件之製法，復包括於形成該線路重佈結構後，進行切單製程。
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