CN105990270B - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN105990270B
CN105990270B CN201510099236.XA CN201510099236A CN105990270B CN 105990270 B CN105990270 B CN 105990270B CN 201510099236 A CN201510099236 A CN 201510099236A CN 105990270 B CN105990270 B CN 105990270B
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CN105990270A (zh
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陈彦亨
张翊峰
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法，该制法先提供一封装结构，其包含具有相对的第一侧与第二侧的封装基板、结合于该第一侧上的电子元件、及设于该第一侧上的多个导电体，再以绝缘包覆层包覆该封装结构，其中，该绝缘包覆层覆盖该封装基板，之后形成线路重布结构于该绝缘包覆层上，且该线路重布结构电性连接该些导电体，所以该绝缘包覆层的布设面积无需配合该封装基板的面积，因而该封装基板可依需求缩小，使该电子封装件的宽度得以减小。

Description

电子封装件及其制法
技术领域
本发明涉及一种封装技术，尤指一种半导体封装技术。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂开发出不同的立体封装技术，例如，扇出式封装堆迭(Fan Out Package on package，简称FO PoP)等，以配合各种晶片上大幅增加的输入/出埠数量，进而将不同功能的积体电路整合于单一封装结构，此种封装方式能发挥系统封装(SiP)异质整合特性，可将不同功用的电子元件，例如：存储体、中央处理器、绘图处理器、影像应用处理器等，藉由堆迭设计达到系统的整合，适合应用于轻薄型各种电子产品。
图1为现有用于PoP的半导体封装件1的剖面示意图。如图1所示，该半导体封装件1包括一具有至少一线路层101的封装基板10，且以覆晶方式结合一半导体元件11于该线路层101上。
具体地，该半导体元件11具有相对的作用面11a与非作用面11b，该作用面11a具有多个电极垫110，以藉由多个如焊锡凸块12电性连接该电极垫110与该线路层101，并形成底胶13于该半导体元件11与该线路层101之间，以包覆该些焊锡凸块12。
此外，形成一封装胶体14于该封装基板10上，以包覆该底胶13及该半导体元件11，且形成多个导电通孔17于该封装胶体14中，以令该导电通孔17外露于该封装胶体14，以供结合一如中介板或封装基板等的电子装置(图略)。
然而，现有半导体封装件1中，于制作该封装胶体14时，该封装基板10需作为承载件，使该封装胶体14的布设面积需配合该封装基板10的面积，因而无法缩小该封装基板10的面积，导致该半导体封装件1的宽度极大而难以减小，所以无法符合轻、薄、短、小的需求。
因此，如何克服现有技术的缺点，实为目前各界亟欲解决的技术问题。
发明内容
鉴于上述现有技术的缺失，本发明的目的为提供一种电子封装件及其制法，使该电子封装件的宽度得以减小。
本案的电子封装件，包括：封装基板，其具有相对的第一侧与第二侧；电子元件，结合于该封装基板的第一侧上；多个导电体，设于该封装基板的第一侧上；绝缘包覆层，其包覆该封装基板、该电子元件与该些导电体，且该封装基板的第二侧外露于该绝缘包覆层；以及线路重布结构，其形成于该绝缘包覆层上，且该线路重布结构电性连接该些导电体。
本发明还提供一种电子封装件的制法，包括：提供至少一封装结构，该封装结构包含具有相对的第一侧与第二侧的封装基板、结合于该第一侧上的电子元件、及设于该第一侧上的多个导电体；以绝缘包覆层包覆该封装结构，其中，该绝缘包覆层覆盖该封装基板；以及形成线路重布结构于该绝缘包覆层上，且该线路重布结构电性连接该些导电体。
前述的制法，还包括于该线路重布结构上形成一结合层。该结合层的边缘设有金属架。还包括先移除该结合层，再进行切单制程。
前述的制法，还包括于形成该线路重布结构后，进行切单制程。
前述的电子封装件及其制法，该导电体为球状、柱状或钉状。
前述的电子封装件及其制法，该导电体位于该电子元件的外围。
前述的电子封装件及其制法，该线路重布结构具有至少一介电层、与设于该介电层上的至少一线路重布层，使该线路重布层直接电性连接该些导电体。
前述的电子封装件及其制法，该线路重布结构具有至少一介电层、设于该介电层上的至少一线路重布层、与形成于该绝缘包覆层中的多个导电盲孔，以令该线路重布层藉由该些导电盲孔电性连接该些导电体。
前述的电子封装件及其制法，该封装基板的第二侧外露于该绝缘包覆层，以供形成多个导电元件于该封装基板的第二侧上，并使该些导电元件电性连接该封装基板。
由上可知，本发明的电子封装件及其制法，主要藉由先制作该些导电体，再以绝缘包覆层包覆该封装结构，使该绝缘包覆层覆盖该封装基板的侧面，并以线路重布结构取代现有如中介板或封装基板等的电子装置，所以相较于现有技术，该绝缘包覆层的布设面积无需配合该封装基板的面积，因而该封装基板可依需求缩小，使该电子封装件的宽度得以减小，以符合轻、薄、短、小的需求。
附图说明
图1为现有半导体封装件的剖面示意图；以及
图2A至图2F为本发明的电子封装件的制法的剖面示意图；其中，图2C’为图2C的另一实施方式。
符号说明
1 半导体封装件
10,20 封装基板
101,201 线路层
11 半导体元件
11a,21a 作用面
11b,21b 非作用面
110,210 电极垫
12,22 焊锡凸块
13,23 底胶
14 封装胶体
17 导电通孔
2 电子封装件
2a 封装结构
20a 第一侧
20b 第二侧
20c 侧面
200,250 介电层
21 电子元件
24 绝缘包覆层
25,25’ 线路重布结构
251 线路重布层
252 导电盲孔
26 导电元件
27 导电体
28 结合层
29 金属架
30 承载板
31 离型层
32 粘着层
S 切割路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“侧”等的用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2F为本发明的电子封装件2的制法的剖面示意图
如图2A所示，提供至少一封装结构2a，再将该封装结构2a设于一承载板30上。具体地，该封装结构2a包括一具有相对的第一侧20a与第二侧20b的封装基板20、结合于该第一侧20a上的一电子元件21、以及设于该第一侧20a上的多个导电体27。
于本实施例中，该封装基板20包含多个介电层200与多个形成于该介电层200上的线路层201，且该线路层201电性连接该电子元件21与该些导电体27。需注意，图中仅揭露该第一侧20a附近的线路层201，但实际情况，该第二侧20b附近及该封装基板20内部也具有线路层。
此外，该电子元件21为主动元件、被动元件或其二者组合，且该主动元件为例如半导体晶片，而该被动元件为例如电阻、电容及电感。例如，该电子元件21为半导体晶片，其具有相对的作用面21a与非作用面21b，该作用面21a具有多个电极垫210，且该电极垫210以覆晶方式藉由多个如焊锡凸块22电性连接该线路层201，并形成底胶23于该电子元件21与该线路层201之间，以包覆该些焊锡凸块22。
又，该导电体27为如焊球的圆球状、如铜柱、焊锡凸块等金属材的柱状、或焊线机制作的钉状(stud)，但不限于此。
另外，该承载板30为直径12寸(或300㎜)玻璃材质的圆形板体，其上依序以涂布方式形成有一离型层31与一粘着层32，且该粘着层22用于粘着该封装结构2a的封装基板20的第二侧20b。
如图2B所示，形成一绝缘包覆层24于该承载板30上，以包覆该封装结构2a。
于本实施例中，该绝缘包覆层24覆盖该封装基板20的侧面20c，其中，该侧面20c邻接该第一侧20a与第二侧20b。
此外，该绝缘包覆层24可用如环氧树脂的封装胶体以压合(lamination)或模压(molding)的方式形成之。
如图2C所示，形成一线路重布结构25于该绝缘包覆层24上，且该线路重布结构25电性连接该些导电体27。
于本实施例中，该线路重布结构25包括至少一介电层250与设于该介电层251上的至少一线路重布层251。
此外，该线路重布层251直接电性连接该导电体27。
或者，如图2C’所示，该线路重布结构25’可于该绝缘包覆层24中形成有多个导电盲孔252，以令该线路重布层251藉由该些导电盲孔252电性连接该些导电体27。
又，形成该线路重布层251的材质为铜，且形成该介电层250的材质为光阻材料或聚对二唑苯(Polybenzoxazole，简称PBO)。
如图2D所示，接续图2C的制程，先于该线路重布结构25上形成一如胶带(Tape)的结合层28，再移除该承载板30及其粘着层32。
于本实施例中，以紫外线或激光穿透该承载板30后，直接照射该离型层31(其为感光材)，使该离型层31感光消失，即可移除该承载板30。
此外，该结合层28的边缘设有金属架29(如铁圈)，以避免该结合层28发生翘曲。
如图2E所示，形成多个如焊球的导电元件26于该封装基板20的第二侧20b上，以供后续接置另一封装结构或其它电子装置(如电路板或中介板)，且该些导电元件26电性连接该封装基板20的线路层201。
如图2F所示，沿如图2E所示的切割路径S进行切单制程，且一并移除该金属架29，再将该线路重布结构25上的该结合层28移除，以完成本发明的电子封装件2。
因此，本发明的制法藉由先将该些导电体27制作于该封装基板20上，再以该绝缘包覆层24包覆该封装结构2a，使该绝缘包覆层24覆盖该封装基板20的侧面20c，所以该绝缘包覆层24的布设面积配合承载板30的面积，而无需配合该封装基板20的面积，因而该封装基板20可依需求缩小，使该电子封装件2的宽度得以减小，以符合轻、薄、短、小的需求。
此外，本发明的制法以线路重布结构25,25’取代现有如中介板或封装基板等的电子装置，因而该封装基板20可依需求缩小，使该电子封装件2的宽度得以减小，以符合轻、薄、短、小的需求。
本发明提供一种电子封装件2，其包括：一封装基板20、一电子元件21、多个导电体27、一绝缘包覆层24以及一线路重布结构25,25’。
所述的封装基板20具有相对的第一侧20a与第二侧20b。
所述的电子元件21结合于该封装基板20的第一侧20a上。
所述的导电体27设于该封装基板20的第一侧20a上并位于该电子元件21的外围，且该导电体27为金属柱。
所述的绝缘包覆层24包覆该封装基板20、该电子元件21与该些导电体27，其中，该绝缘包覆层24覆盖该封装基板20的侧面20c，且令该封装基板20的第二侧20b外露于该绝缘包覆层24。
所述的线路重布结构25,25’形成于该绝缘包覆层24上，且该线路重布结构25,25’电性连接该些导电体27。
于一实施例中，该线路重布结构25具有至少一介电层250与设于该介电层250上的至少一线路重布层251，使该线路重布层251直接电性连接该导电体27。
于一实施例中，该线路重布结构25’具有至少一介电层250、设于该介电层250上的至少一线路重布层251与形成于该绝缘包覆层24中的多个导电盲孔252，以令该线路重布层251藉由该些导电盲孔252电性连接该些导电体27。
于一实施例中，该电子封装件2还包括形成于该封装基板20的第二侧20b上的多个导电元件26，且该些导电元件26电性连接该些导电体27。
综上所述，本发明的电子封装件及其制法，藉由先制作该些导电体于该封装基板上，再以该绝缘包覆层包覆该封装结构，使该绝缘包覆层覆盖该封装基板的侧面，并以线路重布结构取代现有如中介板或封装基板等的电子装置，所以该绝缘包覆层的布设面积无需配合该封装基板的面积，因而该封装基板可依需求缩小，使该电子封装件的宽度得以减小，以符合轻、薄、短、小的需求。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (16)

1.一种电子封装件，其特征为，该电子封装件包括：
封装基板，其具有相对的第一侧与第二侧；
电子元件，通过多个焊锡凸块结合于该封装基板的第一侧上；
底胶，形成于该封装基板及该电子元件之间，以包覆该多个焊锡凸块；
多个导电体，设于该封装基板的第一侧上；
绝缘包覆层，其包覆该封装基板、该电子元件与该些导电体并覆盖该封装基板的侧面，且该封装基板的第二侧外露于该绝缘包覆层；以及
线路重布结构，其形成于该绝缘包覆层上，且该线路重布结构电性连接该些导电体；
其中，该导电体介于该封装基板、该电子元件、该线路重布结构、与覆盖该封装基板的侧面的绝缘包覆层之间，且该导电体的下端高于覆盖该封装基板的侧面的绝缘包覆层的下表面。
2.根据权利要求1所述的电子封装件，其特征为，该导电体为球状、柱状或钉状。
3.根据权利要求1所述的电子封装件，其特征为，该导电体位于该电子元件的外围。
4.根据权利要求1所述的电子封装件，其特征为，该线路重布结构具有至少一介电层、与设于该介电层上的至少一线路重布层，使该线路重布层直接电性连接该些导电体。
5.根据权利要求1所述的电子封装件，其特征为，该线路重布结构具有至少一介电层、设于该介电层上的至少一线路重布层、与形成于该绝缘包覆层中的多个导电盲孔，以令该线路重布层藉由该些导电盲孔电性连接该些导电体。
6.根据权利要求1所述的电子封装件，其特征为，该电子封装件还包括形成于该封装基板的第二侧上的多个导电元件，且该些导电元件电性连接该些导电体。
7.一种电子封装件的制法，其特征为，该制法包括：
提供至少一封装结构，该封装结构包含具有相对的第一侧与第二侧的封装基板、通过多个焊锡凸块结合于该第一侧上的电子元件、形成于该封装基板及该电子元件之间且包覆该多个焊锡凸块的底胶及设于该第一侧上的多个导电体；
以绝缘包覆层包覆该封装结构，其中，该绝缘包覆层覆盖该封装基板的侧面；以及
形成线路重布结构于该绝缘包覆层上，且该线路重布结构电性连接该些导电体；
其中，该导电体介于该封装基板、该电子元件、该线路重布结构、与覆盖该封装基板的侧面的绝缘包覆层之间，且该导电体的下端高于覆盖该封装基板的侧面的绝缘包覆层的下表面。
8.根据权利要求7所述的电子封装件的制法，其特征为，该导电体为球状、柱状或钉状。
9.根据权利要求7所述的电子封装件的制法，其特征为，该导电体位于该电子元件的外围。
10.根据权利要求7所述的电子封装件的制法，其特征为，该线路重布结构具有至少一介电层、与设于该介电层上的至少一线路重布层，使该线路重布层直接电性连接该些导电体。
11.根据权利要求7所述的电子封装件的制法，其特征为，该线路重布结构具有至少一介电层、设于该介电层上的至少一线路重布层、与形成于该绝缘包覆层中的多个导电盲孔，以令该线路重布层藉由该些导电盲孔电性连接该些导电体。
12.根据权利要求7所述的电子封装件的制法，其特征为，该封装基板的第二侧外露于该绝缘包覆层，以供形成多个导电元件于该封装基板的第二侧上，并使该些导电元件电性连接该封装基板。
13.根据权利要求7所述的电子封装件的制法，其特征为，该制法还包括于该线路重布结构上形成一结合层。
14.根据权利要求13所述的电子封装件的制法，其特征为，该结合层的边缘设有金属架。
15.根据权利要求13所述的电子封装件的制法，其特征为，该制法还包括先移除该结合层，再进行切单制程。
16.根据权利要求7所述的电子封装件的制法，其特征为，该制法还包括于形成该线路重布结构后，进行切单制程。
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