JP2015534287A - 半導体デバイス及びその製造方法 - Google Patents
半導体デバイス及びその製造方法 Download PDFInfo
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- JP2015534287A JP2015534287A JP2015541911A JP2015541911A JP2015534287A JP 2015534287 A JP2015534287 A JP 2015534287A JP 2015541911 A JP2015541911 A JP 2015541911A JP 2015541911 A JP2015541911 A JP 2015541911A JP 2015534287 A JP2015534287 A JP 2015534287A
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Abstract
Description
本出願は、2012年11月9日に「半導体デバイス及びその製造方法」の名称で韓国特許庁に出願された韓国特許出願10−2012−0126932号を参照し、その優先権を主張し、その利益を主張するものであり、当該出願の開示全体を、ここに参照のために取り込む。
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付属の図面を参照して、以下に実施形態をさらに詳細に説明する。なお、本発明の種々の態様は違う形で実施されてもよく、提示の実施形態は限定とは解されない。
Claims (20)
- 半導体デバイスの製造方法であって、
再分配層と誘電体層とを備えるインターポーザをダミー基板上に形成し、
半導体ダイをインターポーザの上部に対向する再分配層に接続し、
封入材を用いて半導体ダイを封入し、
インターポーザからダミー基板を除去する、方法。 - ダミー基板は、シリコン及び/又はガラスのうちの少なくとも一つを備える、請求項1に記載の方法。
- 誘電体層は、酸化シリコン層、窒化シリコン層、及び/又はポリマー層のうちの少なくとも一つを備える、請求項1に記載の方法。
- はんだをインターポーザの上部に対向する再分配層上に形成し、
前記半導体ダイの接続において、半導体ダイをはんだに接続する、請求項1に記載の方法。 - 前記半導体ダイの接続の後、アンダーフィルを半導体ダイとインターポーザとの間に充填する、請求項1に記載の方法。
- 前記半導体ダイの封入の後、封入材を研削して半導体ダイの上面を露出する、請求項1に記載の方法。
- 前記ダミー基板の除去において、ダミー基板を研削及びエッチングしてインターポーザの下部に対向する再分配層の部分を露出する、請求項1に記載の方法。
- バンプをインターポーザの下部に対向する再分配層に接続し、
前記バンプの接続において、アンダーバンプメタルをインターポーザの下部に対向する再分配層上に形成し、バンプをアンダーバンプメタルに接続する、請求項1に記載の方法。 - 前記インターポーザの形成において、その上に少なくとも再分配層の一部が形成されるアンダーバンプメタルを形成する、請求項1に記載の方法。
- 接続したバンプを回路基板に搭載する、請求項8に記載の方法。
- アンダーフィルをインターポーザと回路基板との間に充填する、請求項10に記載の方法。
- カバーを回路基板に取り付けて半導体ダイを覆う、請求項10に記載の方法。
- 前記インターポーザの形成において、
シード層をダミー基板上に形成し、
再分配層をシード層上に形成及びパターニングし、
誘電体層を再分配層の外側に形成し、
シード層を除去する、請求項1に記載の方法。 - 前記インターポーザの形成において、
シード層をダミー基板上に形成し、
アンダーバンプメタルをシード層上に形成し、
再分配層をアンダーバンプメタル上に形成及びパターニングし、
誘電体層を再分配層の外側に形成し、
シード層を除去する、請求項1に記載の方法。 - 前記アンダーバンプメタルの形成において、アンダーバンプメタルの外側に形成されたシード層を除去する、請求項14に記載の方法。
- 半導体デバイスの製造方法であって、
再分配層と誘電体層とを備えるインターポーザをダミー基板上に形成し、
インターポーザからダミー基板を除去する、方法。 - 前記ダミー基板の除去において、ダミー基板を研削及びエッチングして再分配層の一部を露出する、請求項16に記載の方法。
- 前記インターポーザの形成において、その上に少なくとも再分配層の一部が形成されるアンダーバンプメタルを形成する、請求項16に記載の方法。
- 半導体デバイスであって、
再分配層と誘電体層とを備えるインターポーザと、
インターポーザの上部に対向する再分配層に接続される半導体ダイと、
半導体ダイを封入する封入材と、
インターポーザの下部に対向する再分配層に接続されるバンプと、を備える半導体デバイス。 - インターポーザ内にアンダーバンプメタルが配置される、請求項19に記載の半導体デバイス。
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JP2018152537A (ja) * | 2017-03-15 | 2018-09-27 | アオイ電子株式会社 | 半導体装置および半導体装置の製造方法 |
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JP2020167355A (ja) * | 2019-03-29 | 2020-10-08 | ラピスセミコンダクタ株式会社 | 半導体パッケージ及び半導体パッケージの製造方法 |
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JP7335036B2 (ja) | 2019-03-29 | 2023-08-29 | ラピスセミコンダクタ株式会社 | 半導体パッケージの製造方法 |
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US9536858B2 (en) | 2017-01-03 |
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CN110085523B (zh) | 2024-04-12 |
WO2014074776A1 (en) | 2014-05-15 |
US20140131856A1 (en) | 2014-05-15 |
KR20140060435A (ko) | 2014-05-20 |
EP2917934A1 (en) | 2015-09-16 |
TW201430967A (zh) | 2014-08-01 |
CN110085523A (zh) | 2019-08-02 |
US20150200179A1 (en) | 2015-07-16 |
CN104904006A (zh) | 2015-09-09 |
TWI594339B (zh) | 2017-08-01 |
US10297466B2 (en) | 2019-05-21 |
KR101411813B1 (ko) | 2014-06-27 |
US9000586B2 (en) | 2015-04-07 |
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