CN109427745B - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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- CN109427745B CN109427745B CN201711224895.7A CN201711224895A CN109427745B CN 109427745 B CN109427745 B CN 109427745B CN 201711224895 A CN201711224895 A CN 201711224895A CN 109427745 B CN109427745 B CN 109427745B
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Abstract
本发明实施例涉及半导体结构及其制造方法。根据本发明的一些实施例,一种半导体结构包含:第一裸片,其包含第一表面及与所述第一表面相对的第二表面;模塑物,其环绕所述第一裸片;第一通路,其延伸穿过所述模塑物;互连结构,其包含介电层及导电部件,其中所述介电层放置于所述第一裸片的所述第一表面及所述模塑物下方,且所述导电部件放置于所述介电层内;及第二裸片,其放置于所述模塑物上方,其中所述第二裸片电连接到所述第一通路。
Description
技术领域
本揭露关于半导体装置技术领域。
背景技术
使用半导体装置的电子设备对于许多现代应用是必要的。随着电子技术的进步,半导体装置在大小上变得越来越小同时具有更大功能性及更大量的集成电路。由于半导体装置的小型化尺度,封装中系统(SiP)广泛用于其低成本且相对简单的制造操作。在SiP操作期间,将若干个半导体组件组装于半导体装置上。此外,在此小型半导体装置內实施众多制造操作。
然而,半导体装置的制造操作涉及对此小且薄的半导体装置的许多步骤及操作。呈小型化尺度的半导体装置的制造变得更复杂。制造半导体装置的复杂性的增加可导致低效率(例如不良电互连、组件的脱层或其它问题),这导致半导体装置的高合格率损失。如此,存在针对修改半导体装置的结构及改善制造操作的许多挑战。
发明内容
本发明实施例提供一种半导体结构,其包括:第一裸片,其包含第一表面及与所述第一表面相对的第二表面;模塑物,其环绕所述第一裸片;通路,其延伸穿过所述模塑物;互连结构,其包含介电层及导电部件,其中所述介电层放置于所述第一裸片的所述第一表面及所述模塑物下方,且所述导电部件放置于所述介电层内;及第二裸片,其放置于所述模塑物上方,其中所述第二裸片电连接到所述通路。
附图说明
当与附图一起阅读时,从以下详细描述最佳地理解本揭露的各方面。应强调,根据工业中的标准实践,各种构件未按比例绘制。实际上,为论述清晰起见,可任意地增加或减小各种构件的尺寸。
图1是图解说明根据本揭露的一些实施例的半导体结构的示意性横截面图。
图2到5是各种布置中的半导体结构的裸片的示意性俯视横截面图。
图6是根据本揭露的一些实施例的半导体结构的示意性横截面图。
图7是根据本揭露的一些实施例的半导体结构的示意性横截面图。
图8是根据本揭露的一些实施例的制造半导体结构的方法的流程图。
图8A到8I是根据本揭露的一些实施例的通过图8的方法制造半导体结构的示意图。
具体实施方式
以下揭露内容提供用于实施所提供标的物的不同构件的许多不同实施例或实例。下文描述组件及布置的特定实例以简化本揭露。当然,这些仅是实例且不打算为限制性的。举例来说,以下描述中第一构件形成于第二构件上方或上可包含其中第一及第二构件形成为直接接触的实施例,且还可包含其中额外构件可形成于第一与第二构件之间使得第一与第二构件可不直接接触的实施例。另外,本揭露可在各种实例中重复参考编号及/或字母。此重复是出于简化及清晰的目的且自身不规定所论述的各种实施例及/或配置之间的关系。
此外,本文中为了便于描述可使用空间相对术语(例如“下面”、“下方”、“下部”、“上面”、“上部”等等)来描述一个元件或构件与另一元件或构件的关系,如各图中所图解说明。除图中所描绘的定向之外,所述空间相对术语还打算涵盖装置在使用或操作时的不同定向。设备可以其它方式定向(旋转90度或处于其它定向),且本文中所使用的空间相对描述语可同样相应地进行解释。
还可包含其它构件及过程。举例来说,可包含测试结构以帮助对3D封装或3DIC装置进行验证测试。举例来说,测试结构可包含形成于重布层中或衬底上的允许对3D封装或3DIC进行测试的测试垫、探针及/或探测卡的使用等等。可对中间结构以及最终结构执行验证测试。另外,本文中所揭露的结构及方法可联合并入有已知良好裸片的中间验证的测试方法来使用以增加合格率且降低成本。
从半导电晶片制作裸片并将其单粒化。在单粒化之后,将裸片封装以变成半导体封装且将其与另一裸片或封装集成在一起。通过模塑物囊封裸片,且通过放置于介电层内的导电线使裸片的I/O端子向外走线,且通过裸片或封装之间的连接器将裸片电连接到另一裸片或封装。然而,此配置可能无法满足对裸片之间的电通信速度、来自裸片的热的耗散等的高需求。因此,裸片或封装的性能可能不处于所要水平。
在本揭露中,揭露一种半导体结构。所述半导体结构包含放置于互连结构上方的第一裸片、环绕所述第一裸片的模塑物、放置于所述模塑物上方的第二裸片及延伸穿过所述模塑物的通路。所述第二裸片放置于所述第一裸片上方且通过所述通路与所述第一裸片电连接。如此,所述第一裸片与所述第二裸片之间的走线被最小化,且因此所述第一裸片与所述第二裸片之间的电通信速度可增加且操作功率可降低。此外,所述半导体结构的总体尺寸也可最小化。
图1是根据本揭露的各种实施例的半导体结构100的示意性横截面图。在一些实施例中,半导体结构100包含第一裸片101、模塑物102、通路103、互连结构104及第二裸片105。
在一些实施例中,半导体结构100是半导体封装。在一些实施例中,半导体结构100是集成式扇出型(InFO)封装,其中第一裸片101的I/O端子被扇出且在更大面积中重布于第一裸片101的表面上方。在一些实施例中,半导体结构100是芯片上芯片或封装上封装(PoP),使得芯片或封装彼此上下堆叠。在一些实施例中,半导体结构100是集成芯片上系统(SoIC)封装结构。在一些实施例中,半导体结构100是三维集成电路(3D IC)。
在一些实施例中,第一裸片101在第一裸片101内制作有预定功能电路。在一些实施例中,第一裸片101是通过机械或激光刀片从半导电晶片单粒化。在一些实施例中,第一裸片101包括适合于特定应用的各种电路。在一些实施例中,所述电路包含各种装置,例如晶体管、电容器、电阻器、二极管及/或类似物。
在一些实施例中,第一裸片101包括各种已知类型的半导体装置(例如微处理器、专用集成电路(ASIC)或类似物)中的任一者。在一些实施例中,第一裸片101是逻辑装置裸片、中央处理单元(CPU)裸片或类似物。在一些实施例中,第一裸片101是将所有电子组件集成到单个裸片中的芯片上系统(SOC)。在一些实施例中,第一裸片101是裸片、芯片或封装。在一些实施例中,第一裸片101具有呈四边形、矩形或正方形形状的俯视横截面(来自如图1中所展示的半导体结构100的俯视图的横截面)。
在一些实施例中,第一裸片101包含包括例如硅等半导电材料的衬底。在一些实施例中,第一裸片101的衬底包含数个电路及放置于其上的电组件。在一些实施例中,第一裸片101的衬底是硅衬底。
在一些实施例中,第一裸片101包含第一表面101a、与第一表面101a相对的第二表面101b及位于第一表面101a与第二表面101b之间的侧壁101c。在一些实施例中,第一表面101a是第一裸片101的前侧或现用侧。在一些实施例中,第二表面101b是第一裸片101的后侧或非现用侧。在一些实施例中,侧壁101c基本上正交于第一表面101a及第二表面101b。在一些实施例中,侧壁101c在第一表面101a与第二表面101b之间垂直地延伸。
在一些实施例中,第一连接器101d放置于第一裸片101上方或下方。在一些实施例中,第一连接器101d放置于第一裸片101的第一表面101a上方或下方。在一些实施例中,第一连接器101d从第一裸片101突出。在一些实施例中,第一连接器101d电连接到第一裸片101中的电路。在一些实施例中,第一连接器101d经配置以与在第一裸片101外部的电路或导电结构耦合。在一些实施例中,第一连接器101d包含导电材料,例如包含焊料、铜、镍、金等。在一些实施例中,第一连接器101d是导电凸块、焊球、球栅阵列(BGA)球、受控塌陷芯片连接(C4)凸块、微凸块、柱、杆或类似物。在一些实施例中,第一连接器101d呈球形、半球形或圆柱形形状。
在一些实施例中,第一底胶101e环绕第一连接器101d且部分地环绕第一裸片101。在一些实施例中,第一底胶101e与第一裸片101的第一表面101a、侧壁101c及第一连接器101d接触。在一些实施例中,第一裸片101的侧壁101c的一部分由第一底胶101e覆盖,且第一裸片101的侧壁101c的一部分从第一底胶101e暴露。在一些实施例中,第一底胶101e填充第一连接器101d之间的间隙。在一些实施例中,第一底胶101e是用于紧固第一裸片101与在第一裸片101外部的导电结构之间的接合的电绝缘粘合剂。在一些实施例中,第一底胶101e包含环氧树脂、环氧树脂模塑料等。
在一些实施例中,模塑物102环绕第一裸片101。在一些实施例中,模塑物102与第一裸片101的侧壁101c及第一底胶101e接触。在一些实施例中,第一裸片101的第二表面101b从模塑物102暴露。在一些实施例中,模塑物102的表面与第一裸片101的第二表面101b共面。在一些实施例中,模塑物102可为单层膜或复合堆叠。在一些实施例中,模塑物102包含各种材料,例如模塑料、模塑底胶、环氧树脂、树脂或类似物。在一些实施例中,模塑物102具有高热传导率、低湿气吸收率及高挠曲强度。
在一些实施例中,通路103延伸穿过模塑物102。在一些实施例中,通路103由模塑物102环绕。在一些实施例中,通路103环绕第一裸片101。在一些实施例中,通路103的外表面与模塑物102接触。在一些实施例中,通路103包含导电材料,例如铜、银、金、铝等。在一些实施例中,通路103是贯穿模塑物通路(TMV)。在一些实施例中,通路103的高度与模塑物102的厚度基本上相同。
在一些实施例中,互连结构104放置于模塑物102及第一裸片101上方或下方。在一些实施例中,互连结构104从第一裸片101沿一路径重新走线以便使第一裸片101的I/O端子重布于模塑物102上方。在一些实施例中,互连结构104是后钝化互连件(PPI)。在一些实施例中,第一裸片101、模塑物102及通路103放置于互连结构104上方。在一些实施例中,第一连接器101d及通路103电连接到互连结构104。在一些实施例中,模塑物102及第一底胶101e与互连结构104接触。
在一些实施例中,互连结构104包含彼此上下堆叠的一或多个介电层104a及放置于介电层104a内或由介电层104a环绕的一或多个导电部件104b。在一些实施例中,介电层104a放置于第一裸片101及模塑物102上方或下方。在一些实施例中,介电层104a放置于第一裸片101的第一表面101a及模塑物102上方或下方。在一些实施例中,第一连接器101d放置于第一裸片101与介电层104a之间。在一些实施例中,模塑物102与介电层104a接触。在一些实施例中,第一底胶101e与介电层104a接触。在一些实施例中,介电层104a包含介电材料,例如氧化硅、氮化硅、碳化硅、氧氮化硅、聚合物、聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)或类似物。
在一些实施例中,导电部件104b放置于介电层104a内。在一些实施例中,导电部件104b在介电层104a内延伸。在一些实施例中,导电部件104b电连接到通路103及第一连接器101d。在一些实施例中,导电部件104b包含导电材料,例如金、银、铜、镍、钨、铝、钯及/或其合金。
在一些实施例中,导电部件104b包含焊盘(land)部分104b-1及从焊盘部分104b-1突出的通路部分104b-2。在一些实施例中,焊盘部分104b-1在介电层104a中横向地延伸。在一些实施例中,焊盘部分104b-1与通路部分104b-2电耦合。在一些实施例中,焊盘部分104b-1经配置以接纳导电结构或与导电结构耦合。在一些实施例中,焊盘部分104b-1放置于介电层104a上方且与通路103电耦合。在一些实施例中,焊盘部分104b-1与第一连接器101d电耦合且通过第一连接器101d电连接到第一裸片101。在一些实施例中,焊盘部分104b-1是衬垫、接垫或类似物。
在一些实施例中,通路部分104b-2在介电层104a中垂直地延伸。在一些实施例中,通路部分104b-2与焊盘部分104b-1耦合。在一些实施例中,通路部分104b-2电连接到通路103、第一连接器101d或第一裸片101。
在一些实施例中,第二裸片105放置于模塑物102上方。在一些实施例中,第二裸片105从模塑物102暴露。在某一实施例中,第二裸片105被完全暴露。在一些实施例中,第二裸片105放置于模塑物102及通路103上方。在一些实施例中,无模塑物102放置于第一裸片101与第二裸片105之间。在一些实施例中,第一裸片101的宽度基本上大于第二裸片105的宽度。在一些实施例中,第二裸片105的厚度基本上大于第一裸片101的厚度。
在一些实施例中,第二裸片105在第二裸片105内制作有预定功能电路。在一些实施例中,第二裸片105是通过机械或激光刀片从半导电晶片单粒化。在一些实施例中,第二裸片105包括适合于特定应用的各种电路。在一些实施例中,所述电路包含各种装置,例如晶体管、电容器、电阻器、二极管及/或类似物。在一些实施例中,第二裸片105包括各种已知类型的半导体装置(例如存储器(例如DRAM、SRAMS、快闪存储器等)或类似物)中的任一者。在一些实施例中,第二裸片105是高带宽存储器(HBM)裸片或类似物。在一些实施例中,第二裸片105是中央处理单元(CPU)存储器或图形处理单元(GPU)存储器。在一些实施例中,第二裸片105具有8个通道,且每一通道具有128位的宽度。在一些实施例中,第二裸片105具有1024位的总宽度。在一些实施例中,第二裸片105具有基本上大于约100千兆字节/秒(GB/s)的带宽。在一些实施例中,第二裸片105是裸片、芯片或封装。在一些实施例中,第二裸片105具有呈四边形、矩形或正方形形状的俯视横截面(来自如图1中所展示的半导体结构100的俯视图的横截面)。
在一些实施例中,第二裸片105包含包括例如硅等半导电材料的衬底。在一些实施例中,第二裸片105的衬底包含数个电路及放置于其上的电组件。在一些实施例中,第二裸片105的衬底是硅衬底。
在一些实施例中,第二裸片105包含第三表面105a、与第三表面105a相对的第四表面105b及位于第三表面105a与第四表面105b之间的侧壁105c。在一些实施例中,第三表面105a是第二裸片105的前侧或现用侧。在一些实施例中,第四表面105b是第二裸片105的后侧或非现用侧。在一些实施例中,侧壁105c基本上正交于第三表面105a及第四表面105b。在一些实施例中,侧壁105c在第三表面105a与第四表面105b之间垂直地延伸。在一些实施例中,第二裸片105的第三表面105a、第四表面105b及侧壁105c是暴露的。在一些实施例中,第二裸片105的第三表面105a、第四表面105b及侧壁105c从模塑物102暴露。
在一些实施例中,第二裸片105放置于第一裸片101上方。在一些实施例中,第二裸片105放置于第一裸片101上面。在一些实施例中,第二裸片105至少部分地与第一裸片101重叠。在一些实施例中,第二裸片105的边缘放置于第一裸片101的边缘上方。在一些实施例中,第二裸片105放置于第一裸片101的第二表面101b的至少一部分上方。
在一些实施例中,第二连接器105d放置于第二裸片105上方或下方。在一些实施例中,第二连接器105d放置于第二裸片105的第三表面105a上方或下方。在一些实施例中,第二连接器105d从第二裸片105突出。在一些实施例中,第二连接器105d电连接到第二裸片105中的电路。在一些实施例中,第二连接器105d经配置以与在第二裸片105外部的电路或导电结构耦合。在一些实施例中,第二连接器105d放置于通路103上方且与通路103耦合。在一些实施例中,第二连接器105d电连接到通路103。在一些实施例中,第二裸片105通过第二连接器105d及通路103电连接到导电部件104b。在一些实施例中,第一裸片101通过第一连接器101d、导电部件104b、通路103及第二连接器105d电连接到第二裸片105。在一些实施例中,第二裸片105是虚拟裸片且与通路103或导电部件104b电隔离。在一些实施例中,第二连接器105d不电连接到通路103或导电部件104b。
在一些实施例中,第二连接器105d包含导电材料,例如包含焊料、铜、镍、金等。在一些实施例中,第二连接器105d是导电凸块、焊球、球栅阵列(BGA)球、受控塌陷芯片连接(C4)凸块、微凸块、柱、杆或类似物。在一些实施例中,第二连接器105d呈球形、半球形或圆柱形形状。
在一些实施例中,第二底胶105e环绕第二连接器105d且部分地环绕第二裸片105。在一些实施例中,第二底胶105e与第二裸片105的第三表面105a、侧壁105c及第二连接器105d接触。在一些实施例中,第二裸片105的侧壁105c的一部分由第二底胶105e覆盖,且第二裸片105的侧壁105c的一部分从第二底胶105e暴露。在一些实施例中,第二底胶105e填充第二连接器105d之间的间隙。在一些实施例中,第二底胶105e与模塑物102、第一裸片101或通路103接触。在一些实施例中,第二底胶105e放置于第一裸片101的第二表面101b上方。在一些实施例中,第二底胶105e是用于紧固第二裸片105与在第二裸片105外部的导电结构之间的接合的电绝缘粘合剂。在一些实施例中,第二底胶105e包含环氧树脂、环氧树脂模塑料等。
在一些实施例中,第一导电凸块106放置于互连结构104上方或下方。在一些实施例中,第一导电凸块106放置于导电部件104b上方或下方。在一些实施例中,第一导电凸块106放置于焊盘部分104b-1上方或下方。在一些实施例中,第一导电凸块106从互连结构104突出。在一些实施例中,第一导电凸块106电连接到导电部件104b或焊盘部分104b-1。
在一些实施例中,第一导电凸块106经配置以与电路或导电结构耦合。在一些实施例中,第一导电凸块106包含导电材料,例如包含焊料、铜、镍、金等。在一些实施例中,第一导电凸块106是导电凸块、焊球、球栅阵列(BGA)球、受控塌陷芯片连接(C4)凸块、微凸块、柱、杆或类似物。在一些实施例中,第一导电凸块106呈球形、半球形或圆柱形形状。
在一些实施例中,衬底108放置于互连结构104上方或下方。在一些实施例中,衬底108在其上制作有预定功能电路。在一些实施例中,衬底108包含放置于衬底108内的数个导电迹线及数个电组件,例如晶体管、二极管等。在一些实施例中,衬底108包含半导电材料,例如硅、锗、镓、砷或其组合。在一些实施例中,衬底108包含例如陶瓷、玻璃、聚合物等等材料。在一些实施例中,衬底108是硅衬底。在一些实施例中,衬底108是印刷电路板(PCB)。在一些实施例中,衬底108具有四边形、矩形、正方形、多边形或任何其它适合形状。
在一些实施例中,衬底108包含第五表面108a及与第五表面108a相对的第六表面108b。在一些实施例中,第五表面108a面对第一导电凸块106及互连结构104。在一些实施例中,第一导电凸块106放置于互连结构104与衬底108之间。在一些实施例中,第一导电凸块106放置于介电层104a与衬底108的第五表面108a之间。
在一些实施例中,衬底108包含放置于衬底108上方的接垫108c。在一些实施例中,接垫108c放置于衬底108的第五表面108a上方。在一些实施例中,接垫108c经配置以接纳导电结构。在一些实施例中,接垫108c电连接到衬底108中的电路。在一些实施例中,第一导电凸块106与接垫108c接合。在一些实施例中,第一导电凸块106放置于接垫108c上方以电连接到衬底108。在一些实施例中,衬底108通过接垫108c、第一导电凸块106、导电部件104b及第一连接器101d电连接到第一裸片101。在一些实施例中,衬底108通过接垫108c、第一导电凸块106、导电部件104b、通路103及第二连接器105d电连接到第二裸片105。在一些实施例中,接垫108c包含导电材料,例如金、银、铜、镍、钨、铝、钯及/或其合金。
在一些实施例中,第三底胶107放置于互连结构104与衬底108之间。在一些实施例中,第三底胶107放置于衬底108的第五表面108a上方。在一些实施例中,第三底胶107环绕第一导电凸块106及介电层104a的一部分。在一些实施例中,第三底胶107与介电层104a的侧壁、第一导电凸块106及衬底108的第五表面108a接触。在一些实施例中,介电层104a的一部分从第三底胶107暴露。在一些实施例中,第三底胶107填充第一导电凸块106之间的间隙。在一些实施例中,第三底胶107是用于紧固互连结构104与衬底108之间的接合的电绝缘粘合剂。在一些实施例中,第三底胶107包含环氧树脂、环氧树脂模塑料等。
在一些实施例中,第二导电凸块109放置于衬底108上方或下方。在一些实施例中,第二导电凸块109放置于衬底108的第六表面108b上方或下方。在一些实施例中,第二导电凸块109从衬底108突出。在一些实施例中,第二导电凸块109电连接到衬底108中的电路。在一些实施例中,第二导电凸块109经配置以与电路或导电结构耦合。在一些实施例中,第二导电凸块109经配置以接合于另一衬底或封装上方且将衬底108的电路与另一衬底或封装的电路电连接。
在一些实施例中,第二导电凸块109包含导电材料,例如包含焊料、铜、镍、金等。在一些实施例中,第二导电凸块109是导电凸块、焊球、球栅阵列(BGA)球、受控塌陷芯片连接(C4)凸块、微凸块、柱、杆或类似物。在一些实施例中,第二导电凸块109呈球形、半球形或圆柱形形状。
图2到5展示半导体结构100的示意性横截面俯视图,其图解说明第一裸片101及第二裸片105的各种布置。在一些实施例中,如图2、3及5中所展示,第二裸片105呈对称布置。在一些实施例中,如图2中所展示,半导体结构100包含一个第一裸片101及环绕第一裸片101的两个第二裸片105。在一些实施例中,如图3中所展示,两个第二裸片105放置成与第一裸片101相对。在一些实施例中,如图4中所展示,第二裸片105放置成与第一裸片101相对。在一些实施例中,如图5中所展示,四个第二裸片105环绕第一裸片101。
图6是根据本揭露的各种实施例的半导体结构200的示意性横截面图。在一些实施例中,半导体结构200包含第一裸片101、模塑物102、通路103、互连结构104及第二裸片105,其具有与上文所描述或图1到5中所图解说明的那些配置类似的配置。
在一些实施例中,半导体结构200包含放置于衬底108、第一裸片101及第二裸片105上方的盖110。在一些实施例中,盖110放置于第一裸片101的第二表面101b上方。在一些实施例中,盖110附接到衬底108。在一些实施例中,盖110与第一裸片101接触。在一些实施例中,盖110经配置以将来自第一裸片101的热耗散到周围环境。在一些实施例中,盖110包含热传导材料,例如铝、铜等。在一些实施例中,盖110是散热片或散热器。在一些实施例中,孔隙111放置于盖110与第二裸片105、模塑物102、互连结构104或衬底108之间。在一些实施例中,如图7中所展示,盖110包含与第一裸片101或衬底108接触的数个分开的部分。
在本揭露中,还揭露一种制造半导体结构100的方法。在一些实施例中,通过方法300形成半导体结构100。方法300包含若干个操作,且描述及说明不应视为对所述操作的序列的限制。图8是制造半导体结构100的方法300的实施例。方法300包含若干个操作(301、302、303、304及305)。
在操作301中,形成互连结构104,如图8A中所展示。在一些实施例中,提供载体112,且在载体112上方形成互连结构104。在一些实施例中,载体112经提供以用于暂时支撑随后放置于其上的组件。在一些实施例中,载体112是衬底或晶片。在一些实施例中,载体112包含硅、玻璃、陶瓷或类似物。
在一些实施例中,互连结构104包含介电层104a及放置于介电层104a内的导电部件104b。在一些实施例中,通过以下操作形成互连结构104:将介电层107a放置于载体112上方,移除介电层104a的一些部分以形成一些凹槽,及将导电材料放置到所述凹槽中以在介电层104a内形成导电部件104b。在一些实施例中,导电部件104b包含焊盘部分104b-1及突出且与焊盘部分104b-1耦合的通路部分104b-2。在一些实施例中,焊盘部分104b-1在介电层104a中横向地延伸,通路部分104b-2在介电层104a中垂直地延伸。在一些实施例中,互连结构104、介电层104a、导电部件104b、焊盘部分104b-1及通路部分104b-2具有与上文所描述或图1到7中的任一者中所图解说明的那些配置类似的配置。
在一些实施例中,通过旋涂、化学气相沉积(CVD)或任何其它适合操作而放置介电层104a。在一些实施例中,通过光刻、蚀刻或任何其它适合操作而移除介电层104a的部分。在一些实施例中,通过溅镀、电镀或任何其它适合操作而放置导电材料。
在操作302中,形成通路103,如图8B中所展示。在一些实施例中,在互连结构104上方形成通路103。在一些实施例中,在导电部件104b上方放置通路103。在一些实施例中,在焊盘部分104b-1上方放置通路103。在一些实施例中,通路103从互连结构104延伸。在一些实施例中,通路103具有与上文所描述或图1到7中的任一者中所图解说明的那些配置类似的配置。
在一些实施例中,通过以下操作而形成通路103:将光阻材料放置于互连结构104上方,将所述光阻材料图案化以形成开口,及将导电材料放置到所述开口中以形成通路103,以及接着移除所述光阻材料。在一些实施例中,导电材料的放置包含溅镀、电镀或任何其它适合操作。在一些实施例中,导电材料包含铜、银、金、铝等。在一些实施例中,通过旋涂或任何其它适合操作而放置光阻材料。在一些实施例中,通过蚀刻、剥离或任何其它适合操作而移除光阻材料。
在操作303中,放置第一裸片101,如图8C中所展示。在一些实施例中,将第一裸片101放置于互连结构104上方。在一些实施例中,将第一裸片101放置成邻近于通路103。在一些实施例中,第一裸片101包含面对互连结构104的第一表面101a、与第一表面101a相对的第二表面101b及位于第一表面101a与第二表面101b之间的侧壁101c。在一些实施例中,第一裸片101是逻辑装置裸片或类似物。在一些实施例中,第一裸片101具有与上文所描述或图1到7中的任一者中所图解说明的配置类似的配置。
在一些实施例中,第一裸片101通过第一连接器101d与导电部件104b接合。在一些实施例中,第一连接器101d与焊盘部分104b-1接合。在某一实施例中,第一裸片101通过第一连接器101d电连接到导电部件104b。
在一些实施例中,第一底胶101e放置于第一裸片101与互连结构104之间以环绕第一连接器101d,如图8C中所展示。在一些实施例中,第一底胶101e环绕第一裸片101的一部分。在一些实施例中,第一裸片101的侧壁101c的一部分由第一底胶101e覆盖。在一些实施例中,第一底胶101e填充邻近第一连接器101d之间的间隙。在一些实施例中,通过流动、注射或任何其它适合操作而放置第一底胶101e。在一些实施例中,第一连接器101d及第一底胶101e具有与上文所描述或图1到7中的任一者中所图解说明的那些配置类似的配置。
在操作304中,形成模塑物102,如图8D中所展示。在一些实施例中,在互连结构104上方以及围绕第一裸片101及通路103形成模塑物102。在一些实施例中,通路103延伸穿过模塑物102。在一些实施例中,通过转移成型、注射成型或任何其它适合操作而形成模塑物102。在一些实施例中,第一裸片101的第二表面101b从模塑物102暴露。在一些实施例中,模塑物102经研磨以暴露第一裸片101的第二表面101b。在一些实施例中,通过研磨、平面化、化学机械抛光(CMP)或任何其它适合操作而研磨模塑物102。在一些实施例中,模塑物102具有与上文所描述或图1到7中的任一者中所图解说明的配置类似的配置。
在操作305中,放置第二裸片105,如图8E中所展示。在一些实施例中,将第二裸片105放置于模塑物102上方。在一些实施例中,将第二裸片105放置于通路103上方。在一些实施例中,将第二裸片105放置于第一裸片101的至少一部分上方。在一些实施例中,第二裸片105至少部分地与第一裸片101重叠。在一些实施例中,第二裸片105包含面对模塑物102的第三表面105a、与第三表面105a相对的第四表面105b及位于第三表面105a与第四表面105b之间的侧壁105c。在一些实施例中,第二裸片105是HBM裸片或类似物。在一些实施例中,第二裸片105具有与上文所描述或图1到7中的任一者中所图解说明的配置类似的配置。
在一些实施例中,第二裸片105通过第二连接器105d与通路103接合,如图8E中所展示。在某一实施例中,第二裸片105通过第二连接器105d电连接到导电部件104b。在一些实施例中,第二裸片105通过第二连接器105d、通路103、导电部件104b及第一连接器101d电连接到第一裸片101。
在一些实施例中,第二底胶105e放置于第二裸片105与模塑物102之间以环绕第二连接器105d,如图8E中所展示。在一些实施例中,第二底胶105e环绕第二裸片105的一部分。在一些实施例中,第二裸片105的侧壁105c的一部分由第二底胶105e覆盖。在一些实施例中,第二底胶105e填充邻近第二连接器105d之间的间隙。在一些实施例中,通过流动、注射或任何其它适合操作而放置第二底胶105e。在一些实施例中,第二连接器105d及第二底胶105e具有与上文所描述或图1到7中的任一者中所图解说明的那些配置类似的配置。
在一些实施例中,移除载体112,如图8F中所展示。在一些实施例中,在放置第二裸片105或第二底胶105e之后移除载体112。在一些实施例中,将载体112从互连结构104或介电层104a解接合。
在一些实施例中,接纳或提供衬底108,如图8G中所展示。在一些实施例中,衬底108是硅衬底。在一些实施例中,衬底108是印刷电路板(PCB)。在一些实施例中,衬底108包含第五表面108a及与第五表面108a相对的第六表面108b。在一些实施例中,衬底108包含放置于衬底108的第五表面108a上方的接垫108c。在一些实施例中,衬底108具有与上文所描述或图1到7中的任一者中所图解说明的配置类似的配置。
在一些实施例中,第一导电凸块106放置于互连结构104上方,如图8G中所展示。在一些实施例中,第一导电凸块106放置于导电部件104b或焊盘部分104b-1上方。在一些实施例中,第一导电凸块106经配置以接合于另一衬底或封装上方且将衬底108的电路与另一衬底或封装的电路电连接。在一些实施例中,第一导电凸块106是焊接头、焊料凸块、焊球、球栅阵列(BGA)球、受控塌陷芯片连接(C4)凸块、微凸块、导电柱、杆或类似物。在一些实施例中,第一导电凸块106具有与上文所描述或图1到7中的任一者中所图解说明的配置类似的配置。
在一些实施例中,第一导电凸块106与衬底108的接垫108c接合,如图8H中所展示。在一些实施例中,第一导电凸块106放置于互连结构104与衬底108之间。在一些实施例中,衬底108通过接垫108c及第一导电凸块106电连接到导电部件104b。在一些实施例中,第一裸片101及第二裸片105通过第一连接器101d、第二连接器105d、通路103、导电部件104b及第一导电凸块106电连接到衬底108。
在一些实施例中,第三底胶107环绕互连结构104的一部分,如图8H中所展示。在一些实施例中,介电层104a的一部分由第三底胶107覆盖。在一些实施例中,第三底胶107围绕第一导电凸块106放置于互连结构104与衬底108之间。在一些实施例中,第三底胶107填充邻近第一导电凸块106之间的间隙。在一些实施例中,通过流动、注射或任何其它适合操作而放置第三底胶107。在一些实施例中,第三底胶107具有与上文所描述或图1到7中的任一者中所图解说明的配置类似的配置。
在一些实施例中,第二导电凸块109放置于衬底108的第六表面108b上方,如图8H中所展示。在一些实施例中,通过落球法、上焊料、丝网印刷或其它适合操作而放置第二导电凸块109。在一些实施例中,第二导电凸块109是焊接头、焊料凸块、焊球、球栅阵列(BGA)球、受控塌陷芯片连接(C4)凸块、微凸块、导电柱、杆或类似物。在一些实施例中,第二导电凸块109具有与上文所描述或图1到7中的任一者中所图解说明的配置类似的配置。在一些实施例中,形成具有与图1中的配置类似的配置的半导体结构100。
在一些实施例中,盖110形成于第一裸片101、第二裸片105及衬底108上方。在一些实施例中,盖110与第一裸片101接触且经配置以将来自第一裸片101的热耗散到四周。在一些实施例中,盖110附接到衬底108。在一些实施例中,通过按压成型或任何其它适合操作而形成盖110,且接着将盖110放在第一裸片101上方且使其与第一裸片101接触。在一些实施例中,盖110具有与上文所描述或者图6或7中所图解说明的配置类似的配置。在一些实施例中,形成具有与图6或7中的配置类似的配置的半导体结构200。
在本揭露中,揭露一种半导体结构。所述半导体结构包含放置于互连结构上方的第一裸片、环绕所述第一裸片的模塑物、放置于所述第一裸片及所述模塑物上方的第二裸片及延伸穿过所述模塑物以将所述第一裸片与所述第二裸片电连接的通路。如此,所述第一裸片与所述第二裸片之间的电通信速度可增加,操作功率可降低,且所述半导体结构的总体尺寸可最小化。
在一些实施例中,一种半导体结构包含:第一裸片,其包含第一表面及与所述第一表面相对的第二表面;模塑物,其环绕所述第一裸片;通路,其延伸穿过所述模塑物;互连结构,其包含介电层及导电部件,其中所述介电层放置于所述第一裸片的所述第一表面及所述模塑物下方,且所述导电部件放置于所述介电层内;及第二裸片,其放置于所述模塑物上方,其中所述第二裸片电连接到所述通路。
在一些实施例中,所述第二裸片至少部分地与所述第一裸片重叠。在一些实施例中,所述第二裸片放置于所述第一裸片的所述第二表面的至少一部分上方。在一些实施例中,所述第二裸片通过所述通路电连接到导电结构。在一些实施例中,所述第一裸片的所述第二表面从所述模塑物暴露。在一些实施例中,所述第二裸片从所述模塑物暴露。在一些实施例中,所述第一裸片放置成邻近于所述通路。在一些实施例中,所述半导体结构进一步包含盖,所述盖放置于所述第一裸片的所述第二表面上方且经配置以耗散来自所述第一裸片的热。在一些实施例中,所述盖的一部分放置于所述第二裸片上方。
在一些实施例中,一种半导体结构包含:第一裸片,其包含第一表面及与所述第一表面相对的第二表面;模塑物,其环绕所述第一裸片;通路,其延伸穿过所述模塑物;互连结构,其包含介电层及导电部件,其中所述介电层放置于所述第一裸片的所述第一表面及所述模塑物下方,且所述导电部件放置于所述介电层内;第二裸片,其放置于所述模塑物及所述通路上方;衬底,其包含面对所述互连结构的第三表面及与所述第三表面相对的第四表面;第一导电凸块,其放置于所述互连结构与所述衬底的所述第三表面之间;及第二导电凸块,其放置于所述衬底的所述第四表面上方,其中所述第二裸片放置于所述第一裸片的所述第二表面的至少一部分上方。
在一些实施例中,所述第一裸片通过所述通路及所述导电部件电连接到所述第二裸片。在一些实施例中,所述第二裸片与所述通路或所述导电部件电隔离。在一些实施例中,所述第一裸片是逻辑裸片,且所述第二裸片是高带宽存储器(HBM)裸片。在一些实施例中,所述半导体结构进一步包含放置于所述衬底的所述第三表面上方且环绕所述第一导电凸块的第一底胶。在一些实施例中,所述第一底胶与所述介电层的侧壁接触。在一些实施例中,所述半导体结构进一步包含放置于所述模塑物与所述第二裸片之间的第二底胶。在一些实施例中,所述第二底胶与所述第一裸片的所述第二表面的至少一部分接触。
在一些实施例中,一种制造半导体结构的方法包含:形成互连结构,所述互连结构包含介电层及放置于所述介电层内的导电部件;在所述互连结构上方形成通路;在所述互连结构上方放置第一裸片;在所述互连结构上方及围绕所述第一裸片及所述通路形成模塑物;及在所述模塑物上方放置第二裸片,其中所述第二裸片电连接到所述通路。
在一些实施例中,所述第二裸片放置于所述第一裸片的至少一部分上方。在一些实施例中,所述方法进一步包含:提供衬底;在所述互连结构与所述衬底之间放置第一导电凸块;在所述互连结构与所述衬底之间及围绕所述第一导电凸块放置第一底胶;及在所述模塑物与所述第二裸片之间放置第二底胶。
前述内容概述数个实施例的构件,使得所属领域的技术人员可更佳地理解本揭露的范围。所属领域的技术人员应了解,其可容易地使用本揭露作为用于设计或修改其它过程及结构以用于执行本文中所介绍的实施例的相同目的及/或实现本文中所介绍的实施例的相同优点的基础。所属领域的技术人员还应认识到,此类等效构造不背离本揭露的精神及范围,且其可在本文中在不背离本揭露的精神及范围的情况下做出各种改变、替代及更改。
Claims (39)
1.一种半导体结构,其包括:
第一裸片,其包含第一表面及与所述第一表面相对的第二表面;
模塑物,其环绕所述第一裸片;
通路,其延伸穿过所述模塑物;
互连结构,其包含介电层及导电部件,其中所述介电层放置于所述第一裸片的所述第一表面及所述模塑物下方,且所述导电部件放置于所述介电层内;
第二裸片,其放置于所述模塑物上方且包含面对所述第一裸片的第三表面、与所述第三表面相对的第四表面及位于所述第三表面与所述第四表面之间的侧壁;
连接器,其放置于所述第二裸片与所述通路之间且与所述第二裸片的所述第三表面及所述通路接触;及
底胶,其环绕所述连接器且与所述第一裸片的所述第二表面的一部分接触,其中所述第二裸片电连接到所述通路,且所述底胶覆盖所述第二裸片的所述侧壁的一部分且完全暴露所述第二裸片的所述第四表面。
2.根据权利要求1所述的半导体结构,其中所述第二裸片至少部分地与所述第一裸片重叠。
3.根据权利要求1所述的半导体结构,其中所述第二裸片放置于所述第一裸片的所述第二表面的至少一部分上方。
4.根据权利要求1所述的半导体结构,其中所述第二裸片通过所述通路电连接到所述导电部件。
5.根据权利要求1所述的半导体结构,其中所述第一裸片的所述第二表面从所述模塑物暴露。
6.根据权利要求1所述的半导体结构,其中所述通路由所述模塑物环绕。
7.根据权利要求1所述的半导体结构,其中所述第一裸片放置成邻近于所述通路。
8.根据权利要求1所述的半导体结构,其进一步包括盖,所述盖放置于所述第一裸片的所述第二表面上方且经配置以耗散来自所述第一裸片的热。
9.根据权利要求8所述的半导体结构,其中所述盖的一部分放置于所述第二裸片上方。
10.一种半导体结构,其包括:
第一裸片,其包含第一表面及与所述第一表面相对的第二表面;
模塑物,其环绕所述第一裸片;
通路,其延伸穿过所述模塑物;
互连结构,其包含介电层及导电部件,其中所述介电层放置于所述第一裸片的所述第一表面及所述模塑物下方,且所述导电部件放置于所述介电层内;
第二裸片,其放置于所述模塑物及所述通路上方且包含面对所述第一裸片的第三表面、与所述第三表面相对的第四表面及位于所述第三表面与所述第四表面之间的侧壁;
第一底胶,其放置于所述模塑物与所述第二裸片之间且覆盖所述第二裸片的所述侧壁的一部分并完全暴露所述第二裸片的所述第四表面;
衬底,其包含面对所述互连结构的第五表面及与所述第五表面相对的第六表面;
第一导电凸块,其放置于所述互连结构与所述衬底的所述第五表面之间;及
第二导电凸块,其放置于所述衬底的所述第六表面上方,
其中所述第二裸片放置于所述第一裸片的所述第二表面的至少一部分上方。
11.根据权利要求10所述的半导体结构,其中所述第一裸片通过所述通路及所述导电部件电连接到所述第二裸片。
12.根据权利要求10所述的半导体结构,其中所述第二裸片与所述通路或所述导电部件电隔离。
13.根据权利要求10所述的半导体结构,其中所述第一裸片是逻辑裸片,且所述第二裸片是高带宽存储器HBM裸片。
14.根据权利要求10所述的半导体结构,其进一步包括放置于所述衬底的所述第五表面上方且环绕所述第一导电凸块的第二底胶。
15.根据权利要求14所述的半导体结构,其中所述第二底胶与所述介电层的侧壁接触。
16.根据权利要求10所述的半导体结构,其中所述第一底胶与所述第一裸片的所述第二表面的至少一部分接触。
17.一种制造半导体结构的方法,其包括:
形成包含介电层及放置于所述介电层内的导电部件的互连结构;
在所述形成所述互连结构之后在所述互连结构上方形成通路;
在所述互连结构上方放置第一裸片;
在所述在所述互连结构上方放置所述第一裸片之后在所述互连结构上方且围绕所述第一裸片及所述通路形成模塑物;
在所述模塑物上方放置第二裸片;
提供衬底;
在所述互连结构与所述衬底之间放置第一导电凸块;
在所述互连结构与所述衬底之间且围绕所述第一导电凸块放置第一底胶;及
在所述模塑物与所述第二裸片之间放置第二底胶,
其中将连接器放置于所述第二裸片与所述通路之间且与所述通路接触,且所述第二裸片通过所述连接器电连接到所述通路。
18.根据权利要求17所述的方法,其中在所述第一裸片的至少一部分上方放置所述第二裸片。
19.根据权利要求17所述的方法,其进一步包括在所述衬底上方放置盖。
20.根据权利要求17所述的方法,其中所述第二裸片通过所述通路电连接到所述互连结构。
21.一种半导体结构,其包括:
第一裸片,其包含第一表面及与所述第一表面相对的第二表面;
模塑物,其环绕所述第一裸片;
通路,其延伸穿过所述模塑物;
第二裸片,其放置于所述模塑物上方且包含面对所述第一裸片的第三表面、与所述第三表面相对的第四表面及位于所述第三表面与所述第四表面之间的侧壁;
连接器,其放置于所述第二裸片与所述通路之间且与所述第二裸片的所述第三表面及所述通路接触;及
底胶,其环绕所述连接器,
其中所述第二裸片电连接到所述通路,所述底胶覆盖所述第二裸片的所述侧壁的一部分及所述第一裸片的所述第二表面的一部分,且所述底胶完全暴露所述第二裸片的所述第四表面。
22.根据权利要求21所述的半导体结构,其中所述第二裸片与所述第一裸片的一部分重叠。
23.根据权利要求21所述的半导体结构,其中所述底胶与所述模塑物的一部分接触。
24.根据权利要求21所述的半导体结构,其中所述第一裸片放置成邻近于所述通路。
25.根据权利要求21所述的半导体结构,其进一步包括互连结构,其中所述第一裸片、所述模塑物及所述通路放置于所述互连结构与所述第二裸片之间。
26.根据权利要求25所述的半导体结构,其中所述第二裸片通过所述连接器及所述通路电连接到所述互连结构。
27.一种半导体结构,其包括:
第一裸片;
模塑物,其环绕所述第一裸片;
通路,其延伸穿过所述模塑物;
第二裸片,其放置于所述模塑物及所述第一裸片上方且电连接到所述通路;及
盖,其放置于所述第一裸片及所述第二裸片上方,
其中所述盖与所述第二裸片分开,且所述盖的一部分与所述第一裸片接触。
28.根据权利要求27所述的半导体结构,其进一步包括:
连接器,其放置于所述第二裸片与所述通路之间;及
第一底胶,其放置于所述模塑物上方且环绕所述连接器,
其中所述第一底胶与所述第一裸片的一部分、所述模塑物的一部分及所述第二裸片的侧壁的一部分接触。
29.根据权利要求27所述的半导体结构,其进一步包括:
衬底;
互连结构,其放置于所述衬底与所述第一裸片之间及所述衬底与所述模塑物之间;及
第一导电凸块,其放置于所述互连结构与所述衬底之间。
30.根据权利要求29所述的半导体结构,其中所述衬底具有面对所述互连结构的表面,且所述盖与所述衬底的所述表面的一部分接触。
31.根据权利要求30所述的半导体结构,其进一步包括第二导电凸块,所述第二导电凸块放置于所述衬底的与面对所述互连结构的所述表面相对的表面上方。
32.根据权利要求29所述的半导体结构,其中所述盖包括与所述第一裸片接触的第一部分、与衬底接触的第二部分,且所述第一部分与所述第二部分彼此分开。
33.根据权利要求29所述的半导体结构,其进一步包括放置于所述互连结构与所述衬底之间且环绕所述第一导电凸块的第二底胶。
34.根据权利要求33所述的半导体结构,其中所述盖与所述第二底胶分开。
35.一种半导体结构,其包括:
互连结构;
第一裸片,其放置于所述互连结构上方;
模塑物,其放置于所述互连结构上方且环绕所述第一裸片;
通路,其延伸穿过所述模塑物且电连接到所述互连结构;
第二裸片,其放置于所述第一裸片及所述模塑物上方;
第一连接器,其放置于所述第一裸片与所述互连结构之间;
第二连接器,其放置于所述第二裸片与所述通路之间;
第一底胶,其环绕所述第一连接器;及
第二底胶,其环绕所述第二连接器,其中所述第二底胶覆盖所述第二裸片的侧壁的一部分且暴露所述第二裸片的所述侧壁的一部分,所述第二底胶与所述第一裸片的一部分及所述模塑物的一部分接触。
36.根据权利要求35所述的半导体结构,其中所述第一底胶与所述第一裸片的侧壁的一部分接触,且所述第二底胶与所述第二裸片的侧壁的一部分接触。
37.根据权利要求35所述的半导体结构,其中所述第一裸片通过所述第一连接器电连接到所述互连结构,且所述第二裸片通过所述第二连接器及所述通路电连接到所述互连结构。
38.根据权利要求35所述的半导体结构,其进一步包括:
衬底,其具有面对所述互连结构的第一表面及与所述第一表面相对的第二表面;
第一导电凸块,其放置于所述衬底的所述第一表面上且将所述衬底电连接到所述互连结构;及
第二导电凸块,其放置于所述衬底的所述第二表面上。
39.根据权利要求38所述的半导体结构,其进一步包括环绕所述第一导电凸块的第三底胶,其中所述第三底胶与所述衬底的所述第一表面的一部分及所述互连结构的侧壁的一部分接触。
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Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9922964B1 (en) * | 2016-09-19 | 2018-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure with dummy die |
TW202404049A (zh) | 2016-12-14 | 2024-01-16 | 成真股份有限公司 | 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器 |
US11625523B2 (en) | 2016-12-14 | 2023-04-11 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips |
US10447274B2 (en) | 2017-07-11 | 2019-10-15 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells |
US10957679B2 (en) | 2017-08-08 | 2021-03-23 | iCometrue Company Ltd. | Logic drive based on standardized commodity programmable logic semiconductor IC chips |
US10461022B2 (en) * | 2017-08-21 | 2019-10-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and manufacturing method thereof |
US10630296B2 (en) | 2017-09-12 | 2020-04-21 | iCometrue Company Ltd. | Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells |
US10608642B2 (en) | 2018-02-01 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells |
US10623000B2 (en) | 2018-02-14 | 2020-04-14 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
US10608638B2 (en) | 2018-05-24 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
US20200066626A1 (en) * | 2018-08-21 | 2020-02-27 | Intel Corporation | Pocket structures, materials, and methods for integrated circuit package supports |
US10892011B2 (en) | 2018-09-11 | 2021-01-12 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US11309334B2 (en) | 2018-09-11 | 2022-04-19 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US10937762B2 (en) | 2018-10-04 | 2021-03-02 | iCometrue Company Ltd. | Logic drive based on multichip package using interconnection bridge |
US20210320096A1 (en) * | 2018-10-26 | 2021-10-14 | Phoenix Pioneer Technology Co., Ltd. | Manufacturing method for semiconductor package structure |
US11616046B2 (en) | 2018-11-02 | 2023-03-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11211334B2 (en) | 2018-11-18 | 2021-12-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11037915B2 (en) * | 2019-02-14 | 2021-06-15 | Facebook Technologies, Llc | Integrated display devices |
US11658095B2 (en) * | 2019-03-29 | 2023-05-23 | Intel Corporation | Bump integrated thermoelectric cooler |
US10937736B2 (en) * | 2019-06-14 | 2021-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid integrated circuit package and method |
US10985154B2 (en) | 2019-07-02 | 2021-04-20 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits |
US11227838B2 (en) | 2019-07-02 | 2022-01-18 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits |
US11887930B2 (en) | 2019-08-05 | 2024-01-30 | iCometrue Company Ltd. | Vertical interconnect elevator based on through silicon vias |
US11637056B2 (en) | 2019-09-20 | 2023-04-25 | iCometrue Company Ltd. | 3D chip package based on through-silicon-via interconnection elevator |
US11830783B2 (en) * | 2019-10-11 | 2023-11-28 | Intel Corporation | Embedded substrate heat sink for bottom side cooling |
TWI711131B (zh) * | 2019-12-31 | 2020-11-21 | 力成科技股份有限公司 | 晶片封裝結構 |
US11600526B2 (en) | 2020-01-22 | 2023-03-07 | iCometrue Company Ltd. | Chip package based on through-silicon-via connector and silicon interconnection bridge |
US11347001B2 (en) * | 2020-04-01 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method of fabricating the same |
US11966090B2 (en) * | 2021-03-03 | 2024-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Heterogeneous packaging integration of photonic and electronic elements |
US11824032B2 (en) * | 2021-03-18 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company Limited | Die corner removal for underfill crack suppression in semiconductor die packaging |
US20230065615A1 (en) * | 2021-08-27 | 2023-03-02 | Advanced Semiconductor Engineering, Inc. | Electronic device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740551A (zh) * | 2008-11-21 | 2010-06-16 | 育霈科技股份有限公司 | 用于半导体元件的叠层晶粒封装结构及其方法 |
CN102387659A (zh) * | 2010-09-03 | 2012-03-21 | 南亚电路板股份有限公司 | 印刷电路板及其制造方法 |
TW201537719A (zh) * | 2014-03-28 | 2015-10-01 | J Devices Corp | 堆疊型半導體封裝 |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9875911B2 (en) * | 2009-09-23 | 2018-01-23 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interposer with opening to contain semiconductor die |
US8558392B2 (en) * | 2010-05-14 | 2013-10-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant |
KR101715761B1 (ko) * | 2010-12-31 | 2017-03-14 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US9190297B2 (en) * | 2011-08-11 | 2015-11-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures |
US8803316B2 (en) | 2011-12-06 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV structures and methods for forming the same |
US8803292B2 (en) | 2012-04-27 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias and methods for forming the same |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
US8802504B1 (en) | 2013-03-14 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
KR102127772B1 (ko) * | 2013-05-16 | 2020-06-29 | 삼성전자주식회사 | 방열 판을 갖는 반도체 패키지 및 그 형성 방법 |
US20150206866A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Package and Methods of Forming Same |
US9653442B2 (en) * | 2014-01-17 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and methods of forming same |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9601463B2 (en) * | 2014-04-17 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out stacked system in package (SIP) and the methods of making the same |
US9425126B2 (en) | 2014-05-29 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structure for chip-on-wafer-on-substrate |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US9496196B2 (en) * | 2014-08-15 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages and methods of manufacture thereof |
US9666559B2 (en) * | 2014-09-05 | 2017-05-30 | Invensas Corporation | Multichip modules and methods of fabrication |
US9318442B1 (en) * | 2014-09-29 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out package with dummy vias |
US9941207B2 (en) * | 2014-10-24 | 2018-04-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of fabricating 3D package with short cycle time and high yield |
US9893017B2 (en) * | 2015-04-09 | 2018-02-13 | STATS ChipPAC Pte. Ltd. | Double-sided semiconductor package and dual-mold method of making same |
US9768145B2 (en) * | 2015-08-31 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming multi-die package structures including redistribution layers |
KR20170027391A (ko) * | 2015-09-02 | 2017-03-10 | 에스케이하이닉스 주식회사 | 복수의 칩들이 내장된 반도체 패키지 및 그의 제조방법 |
US10181457B2 (en) * | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9607967B1 (en) * | 2015-11-04 | 2017-03-28 | Inotera Memories, Inc. | Multi-chip semiconductor package with via components and method for manufacturing the same |
US9984998B2 (en) * | 2016-01-06 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices employing thermal and mechanical enhanced layers and methods of forming same |
US9881908B2 (en) * | 2016-01-15 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out package on package structure and methods of forming same |
US10276402B2 (en) * | 2016-03-21 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing process thereof |
US10535632B2 (en) * | 2016-09-02 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and method of manufacturing the same |
US10163813B2 (en) * | 2016-11-17 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package structure including redistribution structure and conductive shielding film |
US10461022B2 (en) * | 2017-08-21 | 2019-10-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and manufacturing method thereof |
-
2017
- 2017-08-21 US US15/681,776 patent/US10461022B2/en active Active
- 2017-11-29 CN CN201711224895.7A patent/CN109427745B/zh active Active
- 2017-11-29 TW TW106141665A patent/TWI736715B/zh active
-
2019
- 2019-09-11 US US16/567,692 patent/US10937721B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740551A (zh) * | 2008-11-21 | 2010-06-16 | 育霈科技股份有限公司 | 用于半导体元件的叠层晶粒封装结构及其方法 |
CN102387659A (zh) * | 2010-09-03 | 2012-03-21 | 南亚电路板股份有限公司 | 印刷电路板及其制造方法 |
TW201537719A (zh) * | 2014-03-28 | 2015-10-01 | J Devices Corp | 堆疊型半導體封裝 |
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