TWI736715B - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法 Download PDF

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TWI736715B
TWI736715B TW106141665A TW106141665A TWI736715B TW I736715 B TWI736715 B TW I736715B TW 106141665 A TW106141665 A TW 106141665A TW 106141665 A TW106141665 A TW 106141665A TW I736715 B TWI736715 B TW I736715B
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Taiwan
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die
primer
substrate
molded object
connector
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TW106141665A
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TW201913908A (zh
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吳俊毅
余振華
劉重希
李建勳
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台灣積體電路製造股份有限公司
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Abstract

根據本發明之一些實施例，一種半導體結構包括：第一晶粒，其包括第一表面及與該第一表面相對的第二表面；模塑物，其環繞該第一晶粒；第一通路，其延伸穿過該模塑物；互連結構，其包括介電層及導電部件，其中該介電層置放於該第一晶粒之該第一表面及該模塑物下方，且該導電部件置放於該介電層內；及第二晶粒，其置放於該模塑物上方，其中該第二晶粒電連接至該第一通路。

Description

半導體結構及其製作方法
本發明實施例係有關半導體結構及其製作方法。
使用半導體裝置之電子設備對於許多現代應用係必要的。隨著電子技術之進步，半導體裝置在大小上變得越來越小同時具有更大功能性及更大量之積體電路。由於半導體裝置之小型化尺度，封裝中系統(SiP)廣泛用於其低成本且相對簡單的製造操作。在SiP操作期間，將若干個半導體組件組裝於半導體裝置上。此外，在此小型半導體裝置內實施眾多製造操作。 然而，半導體裝置之製造操作涉及對此小且薄的半導體裝置之許多步驟及操作。呈小型化尺度之半導體裝置之製造變得更複雜。製造半導體裝置之複雜性的增加可導致低效率(例如不良電互連、組件之脫層或其他問題)，這導致半導體裝置之高合格率損失。如此，存在針對修改半導體裝置之結構及改良製造操作之許多挑戰。
本發明的一實施例係關於一種半導體結構，其包括：第一裸片，其包含第一表面及與所述第一表面相對的第二表面；模塑物，其環繞所述第一裸片；通路，其延伸穿過所述模塑物；互連結構，其包含介電層及導電部件，其中所述介電層放置於所述第一裸片的所述第一表面及所述模塑物下方，且所述導電部件放置於所述介電層內；及第二裸片，其放置於所述模塑物上方，其中所述第二裸片電連接到所述通路。 本發明的一實施例係關於一種半導體結構，其包括：第一裸片，其包含第一表面及與所述第一表面相對的第二表面；模塑物，其環繞所述第一裸片；通路，其延伸穿過所述模塑物；互連結構，其包含介電層及導電部件，其中所述介電層放置於所述第一裸片的所述第一表面及所述模塑物下方，且所述導電部件放置於所述介電層內；第二裸片，其放置於所述模塑物及所述通路上方；襯底，其包含面對所述互連結構的第三表面及與所述第三表面相對的第四表面；第一導電凸塊，其放置於所述互連結構與所述襯底的所述第三表面之間；及第二導電凸塊，其放置於所述襯底的所述第四表面上方，其中所述第二裸片放置於所述第一裸片的所述第二表面的至少一部分上方。 本發明的一實施例係關於一種製造半導體結構的方法，其包括：形成互連結構，所述互連結構包含介電層及放置於所述介電層內的導電部件；在所述互連結構上方形成通路；在所述互連結構上方放置第一裸片；在所述互連結構上方以及圍繞所述第一裸片及所述通路形成模塑物；及在所述模塑物上方放置第二裸片，其中所述第二裸片電連接到所述通路。
以下揭示內容提供用於實施所提供標的物之不同構件之許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本發明。當然，此等僅為實例且不意欲為限制性的。舉例而言，以下描述中第一構件形成於第二構件上方或上可包括其中第一及第二構件形成為直接接觸之實施例，且亦可包括其中額外構件可形成於第一與第二構件之間使得第一與第二構件可不直接接觸之實施例。另外，本發明可在各種實例中重複參考編號及/或字母。此重複為出於簡化及清晰之目的且自身不規定所論述之各種實施例及/或組態之間的關係。 此外，本文中為了便於描述可使用空間相對術語(例如「下面」、「下方」、「下部」、「上面」、「上部」等)來描述一個元件或構件與另一元件或構件的關係，如各圖中所說明。除圖中所描繪之定向之外，該空間相對術語亦意欲涵蓋裝置在使用或操作時的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用之空間相對描述語可同樣相應地進行解釋。 亦可包括其他構件及過程。舉例而言，可包括測試結構以幫助對3D封裝或3DIC裝置進行驗證測試。舉例而言，測試結構可包括形成於重佈層中或基板上之允許對3D封裝或3DIC進行測試之測試墊、探針及/或探測卡之使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭示之結構及方法可聯合併入有已知良好晶粒之中間驗證之測試方法來使用以增加合格率且降低成本。 自半導電晶圓製作晶粒並將其單粒化。在單粒化之後，將晶粒封裝以變成半導體封裝且將其與另一晶粒或封裝整合在一起。藉由模塑物囊封晶粒，且藉由置放於介電層內之導電線使晶粒之I/O端子向外走線，且藉由晶粒或封裝之間的連接器將晶粒電連接至另一晶粒或封裝。然而，此組態可能無法滿足對晶粒之間的電通信速度、來自晶粒之熱的耗散等的高需求。因此，晶粒或封裝之效能可能不處於所要位準。 在本發明中，揭示一種半導體結構。該半導體結構包括置放於互連結構上方之第一晶粒、環繞該第一晶粒之模塑物、置放於該模塑物上方之第二晶粒及延伸穿過該模塑物之通路。該第二晶粒置放於該第一晶粒上方且藉由該通路與該第一晶粒電連接。如此，該第一晶粒與該第二晶粒之間的走線經最小化，且因此該第一晶粒與該第二晶粒之間的電通信速度可增加且操作功率可降低。此外，該半導體結構之總體尺寸也可最小化。 圖1為根據本發明之各種實施例之半導體結構100之示意性橫截面圖。在一些實施例中，半導體結構100包括第一晶粒101、模塑物102、通路103、互連結構104及第二晶粒105。 在一些實施例中，半導體結構100為半導體封裝。在一些實施例中，半導體結構100為整合式扇出型(InFO)封裝，其中第一晶粒101之I/O端子經扇出且在更大面積中重佈於第一晶粒101之表面上方。在一些實施例中，半導體結構100為晶片上晶片或封裝上封裝(PoP)，使得晶片或封裝彼此上下堆疊。在一些實施例中，半導體結構100為積體系統單晶片(SoIC)封裝結構。在一些實施例中，半導體結構100為三維積體電路(3D IC)。 在一些實施例中，第一晶粒101在第一晶粒101內製作有預定功能電路。在一些實施例中，第一晶粒101為藉由機械或雷射刀片自半導電晶圓單粒化。在一些實施例中，第一晶粒101包含適用於特定應用之各種電路。在一些實施例中，該電路包括各種裝置，例如電晶體、電容器、電阻器、二極體及/或類似物。 在一些實施例中，第一晶粒101包含各種已知類型之半導體裝置(例如微處理器、特殊應用積體電路(ASIC)或類似物)中之任一者。在一些實施例中，第一晶粒101為邏輯裝置晶粒、中央處理單元(CPU)晶粒或類似物。在一些實施例中，第一晶粒101為將所有電子組件整合至單個晶粒中之系統單晶片(SOC)。在一些實施例中，第一晶粒101為晶粒、晶片或封裝。在一些實施例中，第一晶粒101具有呈四邊形、長方形或正方形形狀之俯視橫截面(來自如圖1中所展示之半導體結構100之俯視圖的橫截面)。 在一些實施例中，第一晶粒101包括包含例如矽等半導電材料之基板。在一些實施例中，第一晶粒101之基板包括複數個電路及置放於其上之電組件。在一些實施例中，第一晶粒101之基板為矽基板。 在一些實施例中，第一晶粒101包括第一表面101a、與第一表面101a相對的第二表面101b及位於第一表面101a與第二表面101b之間的側壁101c。在一些實施例中，第一表面101a為第一晶粒101之前側或現用側。在一些實施例中，第二表面101b為第一晶粒101之後側或非現用側。在一些實施例中，側壁101c基本上正交於第一表面101a及第二表面101b。在一些實施例中，側壁101c在第一表面101a與第二表面101b之間垂直地延伸。 在一些實施例中，第一連接器101d置放於第一晶粒101上方或下方。在一些實施例中，第一連接器101d置放於第一晶粒101之第一表面101a上方或下方。在一些實施例中，第一連接器101d自第一晶粒101突出。在一些實施例中，第一連接器101d電連接至第一晶粒101中之電路。在一些實施例中，第一連接器101d經組態以與在第一晶粒101外部之電路或導電結構耦接。在一些實施例中，第一連接器101d包括導電材料，例如包括焊料、銅、鎳、金等。在一些實施例中，第一連接器101d為導電凸塊、焊球、球柵陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、柱、桿或類似物。在一些實施例中，第一連接器101d呈球形、半球形或圓柱形形狀。 在一些實施例中，第一底膠101e環繞第一連接器101d且部分地環繞第一晶粒101。在一些實施例中，第一底膠101e與第一晶粒101之第一表面101a、側壁101c及第一連接器101d接觸。在一些實施例中，第一晶粒101之側壁101c的一部分由第一底膠101e覆蓋，且第一晶粒101之側壁101c的一部分自第一底膠101e曝露。在一些實施例中，第一底膠101e填充第一連接器101d之間的間隙。在一些實施例中，第一底膠101e為用於緊固第一晶粒101與在第一晶粒101外部之導電結構之間的接合的電絕緣黏合劑。在一些實施例中，第一底膠101e包括環氧樹脂、環氧樹脂模塑膠等。 在一些實施例中，模塑物102環繞第一晶粒101。在一些實施例中，模塑物102與第一晶粒101之側壁101c及第一底膠101e接觸。在一些實施例中，第一晶粒101之第二表面101b自模塑物102曝露。在一些實施例中，模塑物102之表面與第一晶粒101之第二表面101b共面。在一些實施例中，模塑物102可為單層膜或複合堆疊。在一些實施例中，模塑物102包括各種材料，例如模塑膠、模塑底膠、環氧樹脂、樹脂或類似物。在一些實施例中，模塑物102具有高熱傳導率、低濕氣吸收率及高撓曲強度。 在一些實施例中，通路103延伸穿過模塑物102。在一些實施例中，通路103由模塑物102環繞。在一些實施例中，通路103環繞第一晶粒101。在一些實施例中，通路103之外表面與模塑物102接觸。在一些實施例中，通路103包括導電材料，例如銅、銀、金、鋁等。在一些實施例中，通路103為貫穿模塑物通路(TMV)。在一些實施例中，通路103之高度與模塑物102之厚度基本上相同。 在一些實施例中，互連結構104置放於模塑物102及第一晶粒101上方或下方。在一些實施例中，互連結構104自第一晶粒101沿一路徑重新走線以便使第一晶粒101之I/O端子重佈於模塑物102上方。在一些實施例中，互連結構104為後鈍化互連件(PPI)。在一些實施例中，第一晶粒101、模塑物102及通路103置放於互連結構104上方。在一些實施例中，第一連接器101d及通路103電連接至互連結構104。在一些實施例中，模塑物102及第一底膠101e與互連結構104接觸。 在一些實施例中，互連結構104包括彼此上下堆疊之一或多個介電層104a及置放於介電層104a內或由介電層104a環繞之一或多個導電部件104b。在一些實施例中，介電層104a置放於第一晶粒101及模塑物102上方或下方。在一些實施例中，介電層104a置放於第一晶粒101之第一表面101a及模塑物102上方或下方。在一些實施例中，第一連接器101d置放於第一晶粒101與介電層104a之間。在一些實施例中，模塑物102與介電層104a接觸。在一些實施例中，第一底膠101e與介電層104a接觸。在一些實施例中，介電層104a包括介電材料，例如氧化矽、氮化矽、碳化矽、氧氮化矽、聚合物、聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或類似物。 在一些實施例中，導電部件104b置放於介電層104a內。在一些實施例中，導電部件104b在介電層104a內延伸。在一些實施例中，導電部件104b電連接至通路103及第一連接器101d。在一些實施例中，導電部件104b包括導電材料，例如金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。 在一些實施例中，導電部件104b包括連接盤(land)部分104b-1及自連接盤部分104b-1突出之通路部分104b-2。在一些實施例中，連接盤部分104b-1在介電層104a中橫向地延伸。在一些實施例中，連接盤部分104b-1與通路部分104b-2電耦接。在一些實施例中，連接盤部分104b-1經組態以收容導電結構或與導電結構耦接。在一些實施例中，連接盤部分104b-1置放於介電層104a上方且與通路103電耦接。在一些實施例中，連接盤部分104b-1與第一連接器101d電耦接且藉由第一連接器101d電連接至第一晶粒101。在一些實施例中，連接盤部分104b-1為襯墊、接墊或類似物。 在一些實施例中，通路部分104b-2在介電層104a中垂直地延伸。在一些實施例中，通路部分104b-2與連接盤部分104b-1耦接。在一些實施例中，通路部分104b-2電連接至通路103、第一連接器101d或第一晶粒101。 在一些實施例中，第二晶粒105置放於模塑物102上方。在一些實施例中，第二晶粒105自模塑物102曝露。在某一實施例中，第二晶粒105經完全曝露。在一些實施例中，第二晶粒105置放於模塑物102及通路103上方。在一些實施例中，無模塑物102置放於第一晶粒101與第二晶粒105之間。在一些實施例中，第一晶粒101之寬度基本上大於第二晶粒105之寬度。在一些實施例中，第二晶粒105之厚度基本上大於第一晶粒101之厚度。 在一些實施例中，第二晶粒105在第二晶粒105內製作有預定功能電路。在一些實施例中，第二晶粒105為藉由機械或雷射刀片自半導電晶圓單粒化。在一些實施例中，第二晶粒105包含適用於特定應用之各種電路。在一些實施例中，該電路包括各種裝置，例如電晶體、電容器、電阻器、二極體及/或類似物。在一些實施例中，第二晶粒105包含各種已知類型之半導體裝置(例如記憶體(例如DRAM、SRAMS、快閃記憶體等)或類似物)中之任一者。在一些實施例中，第二晶粒105為高頻寬記憶體(HBM)晶粒或類似物。在一些實施例中，第二晶粒105為中央處理單元(CPU)記憶體或圖形處理單元(GPU)記憶體。在一些實施例中，第二晶粒105具有8個通道，且每一通道具有128位之寬度。在一些實施例中，第二晶粒105具有1024位之總寬度。在一些實施例中，第二晶粒105具有基本上大於約100千兆位元/秒(GB/s)之頻寬。在一些實施例中，第二晶粒105為晶粒、晶片或封裝。在一些實施例中，第二晶粒105具有呈四邊形、長方形或正方形形狀之俯視橫截面(來自如圖1中所展示之半導體結構100之俯視圖的橫截面)。 在一些實施例中，第二晶粒105包括包含例如矽等半導電材料之基板。在一些實施例中，第二晶粒105之基板包括複數個電路及置放於其上之電組件。在一些實施例中，第二晶粒105之基板為矽基板。 在一些實施例中，第二晶粒105包括第三表面105a、與第三表面105a相對的第四表面105b及位於第三表面105a與第四表面105b之間的側壁105c。在一些實施例中，第三表面105a為第二晶粒105之前側或現用側。在一些實施例中，第四表面105b為第二晶粒105之後側或非現用側。在一些實施例中，側壁105c基本上正交於第三表面105a及第四表面105b。在一些實施例中，側壁105c在第三表面105a與第四表面105b之間垂直地延伸。在一些實施例中，第二晶粒105之第三表面105a、第四表面105b及側壁105c為曝露的。在一些實施例中，第二晶粒105之第三表面105a、第四表面105b及側壁105c自模塑物102曝露。 在一些實施例中，第二晶粒105置放於第一晶粒101上方。在一些實施例中，第二晶粒105置放於第一晶粒101上面。在一些實施例中，第二晶粒105至少部分地與第一晶粒101重疊。在一些實施例中，第二晶粒105之邊緣置放於第一晶粒101之邊緣上方。在一些實施例中，第二晶粒105置放於第一晶粒101之第二表面101b之至少一部分上方。 在一些實施例中，第二連接器105d置放於第二晶粒105上方或下方。在一些實施例中，第二連接器105d置放於第二晶粒105之第三表面105a上方或下方。在一些實施例中，第二連接器105d自第二晶粒105突出。在一些實施例中，第二連接器105d電連接至第二晶粒105中之電路。在一些實施例中，第二連接器105d經組態以與在第二晶粒105外部之電路或導電結構耦接。在一些實施例中，第二連接器105d置放於通路103上方且與通路103耦接。在一些實施例中，第二連接器105d電連接至通路103。在一些實施例中，第二晶粒105藉由第二連接器105d及通路103電連接至導電部件104b。在一些實施例中，第一晶粒101藉由第一連接器101d、導電部件104b、通路103及第二連接器105d電連接至第二晶粒105。在一些實施例中，第二晶粒105為虛擬晶粒且與通路103或導電部件104b電隔離。在一些實施例中，第二連接器105d不電連接至通路103或導電部件104b。 在一些實施例中，第二連接器105d包括導電材料，例如包括焊料、銅、鎳、金等。在一些實施例中，第二連接器105d為導電凸塊、焊球、球柵陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、柱、桿或類似物。在一些實施例中，第二連接器105d呈球形、半球形或圓柱形形狀。 在一些實施例中，第二底膠105e環繞第二連接器105d且部分地環繞第二晶粒105。在一些實施例中，第二底膠105e與第二晶粒105之第三表面105a、側壁105c及第二連接器105d接觸。在一些實施例中，第二晶粒105之側壁105c的一部分由第二底膠105e覆蓋，且第二晶粒105之側壁105c的一部分自第二底膠105e曝露。在一些實施例中，第二底膠105e填充第二連接器105d之間的間隙。在一些實施例中，第二底膠105e與模塑物102、第一晶粒101或通路103接觸。在一些實施例中，第二底膠105e置放於第一晶粒101之第二表面101b上方。在一些實施例中，第二底膠105e為用於緊固第二晶粒105與在第二晶粒105外部之導電結構之間的接合之電絕緣黏合劑。在一些實施例中，第二底膠105e包括環氧樹脂、環氧樹脂模塑膠等。 在一些實施例中，第一導電凸塊106置放於互連結構104上方或下方。在一些實施例中，第一導電凸塊106置放於導電部件104b上方或下方。在一些實施例中，第一導電凸塊106置放於連接盤部分104b-1上方或下方。在一些實施例中，第一導電凸塊106自互連結構104突出。在一些實施例中，第一導電凸塊106電連接至導電部件104b或連接盤部分104b-1。 在一些實施例中，第一導電凸塊106經組態以與電路或導電結構耦接。在一些實施例中，第一導電凸塊106包括導電材料，例如包括焊料、銅、鎳、金等。在一些實施例中，第一導電凸塊106為導電凸塊、焊球、球柵陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、柱、桿或類似物。在一些實施例中，第一導電凸塊106呈球形、半球形或圓柱形形狀。 在一些實施例中，基板108置放於互連結構104上方或下方。在一些實施例中，基板108在其上製作有預定功能電路。在一些實施例中，基板108包括置放於基板108內之複數個導電跡線及複數個電組件，例如電晶體、二極體等。在一些實施例中，基板108包括半導電材料，例如矽、鍺、鎵、砷或其組合。在一些實施例中，基板108包括例如陶瓷、玻璃、聚合物等材料。在一些實施例中，基板108為矽基板。在一些實施例中，基板108為印刷電路板(PCB)。在一些實施例中，基板108具有四邊形、長方形、正方形、多邊形或任何其他適合形狀。 在一些實施例中，基板108包括第五表面108a及與第五表面108a相對的第六表面108b。在一些實施例中，第五表面108a面對第一導電凸塊106及互連結構104。在一些實施例中，第一導電凸塊106置放於互連結構104與基板108之間。在一些實施例中，第一導電凸塊106置放於介電層104a與基板108之第五表面108a之間。 在一些實施例中，基板108包括置放於基板108上方之接墊108c。在一些實施例中，接墊108c置放於基板108之第五表面108a上方。在一些實施例中，接墊108c經組態以收容導電結構。在一些實施例中，接墊108c電連接至基板108中之電路。在一些實施例中，第一導電凸塊106與接墊108c接合。在一些實施例中，第一導電凸塊106置放於接墊108c上方以電連接至基板108。在一些實施例中，基板108藉由接墊108c、第一導電凸塊106、導電部件104b及第一連接器101d電連接至第一晶粒101。在一些實施例中，基板108藉由接墊108c、第一導電凸塊106、導電部件104b、通路103及第二連接器105d電連接至第二晶粒105。在一些實施例中，接墊108c包括導電材料，例如金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。 在一些實施例中，第三底膠107置放於互連結構104與基板108之間。在一些實施例中，第三底膠107置放於基板108之第五表面108a上方。在一些實施例中，第三底膠107環繞第一導電凸塊106及介電層104a的一部分。在一些實施例中，第三底膠107與介電層104a之側壁、第一導電凸塊106及基板108之第五表面108a接觸。在一些實施例中，介電層104a的一部分自第三底膠107曝露。在一些實施例中，第三底膠107填充第一導電凸塊106之間的間隙。在一些實施例中，第三底膠107為用於緊固互連結構104與基板108之間的接合之電絕緣黏合劑。在一些實施例中，第三底膠107包括環氧樹脂、環氧樹脂模塑膠等。 在一些實施例中，第二導電凸塊109置放於基板108上方或下方。在一些實施例中，第二導電凸塊109置放於基板108之第六表面108b上方或下方。在一些實施例中，第二導電凸塊109自基板108突出。在一些實施例中，第二導電凸塊109電連接至基板108中之電路。在一些實施例中，第二導電凸塊109經組態以與電路或導電結構耦接。在一些實施例中，第二導電凸塊109經組態以接合於另一基板或封裝上方且將基板108之電路與另一基板或封裝之電路電連接。 在一些實施例中，第二導電凸塊109包括導電材料，例如包括焊料、銅、鎳、金等。在一些實施例中，第二導電凸塊109為導電凸塊、焊球、球柵陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、柱、桿或類似物。在一些實施例中，第二導電凸塊109呈球形、半球形或圓柱形形狀。 圖2至圖5展示半導體結構100之示意性橫截面俯視圖，其說明第一晶粒101及第二晶粒105之各種配置。在一些實施例中，如圖2、圖3及圖5中所展示，第二晶粒105呈對稱配置。在一些實施例中，如圖2中所展示，半導體結構100包括一個第一晶粒101及環繞第一晶粒101之兩個第二晶粒105。在一些實施例中，如圖3中所展示，兩個第二晶粒105置放成與第一晶粒101相對。在一些實施例中，如圖4中所展示，第二晶粒105置放成與第一晶粒101相對。在一些實施例中，如圖5中所展示，四個第二晶粒105環繞第一晶粒101。 圖6為根據本發明之各種實施例之半導體結構200之示意性橫截面圖。在一些實施例中，半導體結構200包括第一晶粒101、模塑物102、通路103、互連結構104及第二晶粒105，其具有與上文所描述或圖1至圖5中所說明之彼等組態類似之組態。 在一些實施例中，半導體結構200包括置放於基板108、第一晶粒101及第二晶粒105上方之蓋110。在一些實施例中，蓋110置放於第一晶粒101之第二表面101b上方。在一些實施例中，蓋110附接至基板108。在一些實施例中，蓋110與第一晶粒101接觸。在一些實施例中，蓋110經組態以將來自第一晶粒101之熱耗散至周圍環境。在一些實施例中，蓋110包括熱傳導材料，例如鋁、銅等。在一些實施例中，蓋110為散熱片或散熱器。在一些實施例中，孔隙111置放於蓋110與第二晶粒105、模塑物102、互連結構104或基板108之間。在一些實施例中，如圖7中所展示，蓋110包括與第一晶粒101或基板108接觸之複數個分開的部分。 在本發明中，亦揭示一種製造半導體結構100之方法。在一些實施例中，藉由方法300形成半導體結構100。方法300包括若干個操作，且描述及說明不應視為對該操作之序列的限制。圖8為製造半導體結構100之方法300之實施例。方法300包括若干個操作(301、302、303、304及305)。 在操作301中，形成互連結構104，如圖8A中所展示。在一些實施例中，提供載體112，且在載體112上方形成互連結構104。在一些實施例中，載體112經提供以用於暫時支撐隨後置放於其上之組件。在一些實施例中，載體112為基板或晶圓。在一些實施例中，載體112包括矽、玻璃、陶瓷或類似物。 在一些實施例中，互連結構104包括介電層104a及置放於介電層104a內之導電部件104b。在一些實施例中，藉由以下操作形成互連結構104：將介電層107a置放於載體112上方，移除介電層104a之一些部分以形成一些凹槽，及將導電材料置放至該凹槽中以在介電層104a內形成導電部件104b。在一些實施例中，導電部件104b包括連接盤部分104b-1及突出且與連接盤部分104b-1耦接之通路部分104b-2。在一些實施例中，連接盤部分104b-1在介電層104a中橫向地延伸，通路部分104b-2在介電層104a中垂直地延伸。在一些實施例中，互連結構104、介電層104a、導電部件104b、連接盤部分104b-1及通路部分104b-2具有與上文所描述或圖1至圖7中之任一者中所說明之彼等組態類似的組態。 在一些實施例中，藉由旋塗、化學氣相沈積(CVD)或任何其他適合操作而置放介電層104a。在一些實施例中，藉由光刻、蝕刻或任何其他適合操作而移除介電層104a之部分。在一些實施例中，藉由濺鍍、電鍍或任何其他適合操作而置放導電材料。 在操作302中，形成通路103，如圖8B中所展示。在一些實施例中，在互連結構104上方形成通路103。在一些實施例中，在導電部件104b上方置放通路103。在一些實施例中，在連接盤部分104b-1上方置放通路103。在一些實施例中，通路103自互連結構104延伸。在一些實施例中，通路103具有與上文所描述或圖1至圖7中之任一者中所說明之彼等組態類似的組態。 在一些實施例中，藉由以下操作而形成通路103：將光阻材料置放於互連結構104上方，將該光阻材料圖案化以形成開口，及將導電材料置放至該開口中以形成通路103，以及接著移除該光阻材料。在一些實施例中，導電材料之置放包括濺鍍、電鍍或任何其他合適的操作。在一些實施例中，導電材料包括銅、銀、金、鋁等。在一些實施例中，藉由旋塗或任何其他適合操作而置放光阻材料。在一些實施例中，藉由蝕刻、剝離或任何其他適合操作而移除光阻材料。 在操作303中，置放第一晶粒101，如圖8C中所展示。在一些實施例中，將第一晶粒101置放於互連結構104上方。在一些實施例中，將第一晶粒101置放成鄰近於通路103。在一些實施例中，第一晶粒101包括面對互連結構104之第一表面101a、與第一表面101a相對的第二表面101b及位於第一表面101a與第二表面101b之間的側壁101c。在一些實施例中，第一晶粒101為邏輯裝置晶粒或類似物。在一些實施例中，第一晶粒101具有與上文所描述或圖1至圖7中之任一者中所說明之組態類似的組態。 在一些實施例中，第一晶粒101藉由第一連接器101d與導電部件104b接合。在一些實施例中，第一連接器101d與連接盤部分104b-1接合。在某一實施例中，第一晶粒101藉由第一連接器101d電連接至導電部件104b。 在一些實施例中，第一底膠101e置放於第一晶粒101與互連結構104之間以環繞第一連接器101d，如圖8C中所展示。在一些實施例中，第一底膠101e環繞第一晶粒101的一部分。在一些實施例中，第一晶粒101之側壁101c的一部分由第一底膠101e覆蓋。在一些實施例中，第一底膠101e填充鄰近第一連接器101d之間的間隙。在一些實施例中，藉由流動、注射或任何其他適合操作而置放第一底膠101e。在一些實施例中，第一連接器101d及第一底膠101e具有與上文所描述或圖1至圖7中之任一者中所說明之彼等組態類似的組態。 在操作304中，形成模塑物102，如圖8D中所展示。在一些實施例中，在互連結構104上方以及圍繞第一晶粒101及通路103形成模塑物102。在一些實施例中，通路103延伸穿過模塑物102。在一些實施例中，藉由轉移成型、注射成型或任何其他適合操作而形成模塑物102。在一些實施例中，第一晶粒101之第二表面101b自模塑物102曝露。在一些實施例中，模塑物102經研磨以曝露第一晶粒101之第二表面101b。在一些實施例中，藉由研磨、平面化、化學機械拋光(CMP)或任何其他適合操作而研磨模塑物102。在一些實施例中，模塑物102具有與上文所描述或圖1至圖7中之任一者中所說明之組態類似的組態。 在操作305中，置放第二晶粒105，如圖8E中所展示。在一些實施例中，將第二晶粒105置放於模塑物102上方。在一些實施例中，將第二晶粒105置放於通路103上方。在一些實施例中，將第二晶粒105置放於第一晶粒101之至少一部分上方。在一些實施例中，第二晶粒105至少部分地與第一晶粒101重疊。在一些實施例中，第二晶粒105包括面對模塑物102之第三表面105a、與第三表面105a相對的第四表面105b及位於第三表面105a與第四表面105b之間的側壁105c。在一些實施例中，第二晶粒105為HBM晶粒或類似物。在一些實施例中，第二晶粒105具有與上文所描述或圖1至圖7中之任一者中所說明之組態類似的組態。 在一些實施例中，第二晶粒105藉由第二連接器105d與通路103接合，如圖8E中所展示。在某一實施例中，第二晶粒105藉由第二連接器105d電連接至導電部件104b。在一些實施例中，第二晶粒105藉由第二連接器105d、通路103、導電部件104b及第一連接器101d電連接至第一晶粒101。 在一些實施例中，第二底膠105e置放於第二晶粒105與模塑物102之間以環繞第二連接器105d，如圖8E中所展示。在一些實施例中，第二底膠105e環繞第二晶粒105的一部分。在一些實施例中，第二晶粒105之側壁105c的一部分由第二底膠105e覆蓋。在一些實施例中，第二底膠105e填充鄰近第二連接器105d之間的間隙。在一些實施例中，藉由流動、注射或任何其他適合操作而置放第二底膠105e。在一些實施例中，第二連接器105d 及第二底膠105e具有與上文所描述或圖1至圖7中之任一者中所說明之彼等組態類似的組態。 在一些實施例中，移除載體112，如圖8F中所展示。在一些實施例中，在置放第二晶粒105或第二底膠105e之後移除載體112。在一些實施例中，將載體112自互連結構104或介電層104a解接合。 在一些實施例中，收容或提供基板108，如圖8G中所展示。在一些實施例中，基板108為矽基板。在一些實施例中，基板108為印刷電路板(PCB)。在一些實施例中，基板108包括第五表面108a及與第五表面108a相對的第六表面108b。在一些實施例中，基板108包括置放於基板108之第五表面108a上方之接墊108c。在一些實施例中，基板108具有與上文所描述或圖1至圖7中之任一者中所說明之組態類似的組態。 在一些實施例中，第一導電凸塊106置放於互連結構104上方，如圖8G中所展示。在一些實施例中，第一導電凸塊106置放於導電部件104b或連接盤部分104b-1上方。在一些實施例中，第一導電凸塊106經組態以接合於另一基板或封裝上方且將基板108之電路與另一基板或封裝之電路電連接。在一些實施例中，第一導電凸塊106為焊接頭、焊料凸塊、焊球、球柵陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、導電柱、桿或類似物。在一些實施例中，第一導電凸塊106具有與上文所描述或圖1至圖7中之任一者中所說明之組態類似的組態。 在一些實施例中，第一導電凸塊106與基板108之接墊108c接合，如圖8H中所展示。在一些實施例中，第一導電凸塊106置放於互連結構104與基板108之間。在一些實施例中，基板108藉由接墊108c及第一導電凸塊106電連接至導電部件104b。在一些實施例中，第一晶粒101及第二晶粒105藉由第一連接器101d、第二連接器105d、通路103、導電部件104b及第一導電凸塊106電連接至基板108。 在一些實施例中，第三底膠107環繞互連結構104的一部分，如圖8H中所展示。在一些實施例中，介電層104a的一部分由第三底膠107覆蓋。在一些實施例中，第三底膠107圍繞第一導電凸塊106置放於互連結構104與基板108之間。在一些實施例中，第三底膠107填充鄰近第一導電凸塊106之間的間隙。在一些實施例中，藉由流動、注射或任何其他適合操作而置放第三底膠107。在一些實施例中，第三底膠107具有與上文所描述或圖1至圖7中之任一者中所說明之組態類似的組態。 在一些實施例中，第二導電凸塊109置放於基板108之第六表面108b上方，如圖8H中所展示。在一些實施例中，藉由落球法、上焊料、絲網印刷或其他適合操作而置放第二導電凸塊109。在一些實施例中，第二導電凸塊109為焊接頭、焊料凸塊、焊球、球柵陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、導電柱、桿或類似物。在一些實施例中，第二導電凸塊109具有與上文所描述或圖1至圖7中之任一者中所說明之組態類似的組態。在一些實施例中，形成具有與圖1中之組態類似之組態的半導體結構100。 在一些實施例中，蓋110形成於第一晶粒101、第二晶粒105及基板108上方。在一些實施例中，蓋110與第一晶粒101接觸且經組態以將來自第一晶粒101之熱耗散至四周。在一些實施例中，蓋110附接至基板108。在一些實施例中，藉由按壓成型或任何其他適合操作而形成蓋110，且接著將蓋110放在第一晶粒101上方且使其與第一晶粒101接觸。在一些實施例中，蓋110具有與上文所描述或者圖6或圖7中所說明之組態類似的組態。在一些實施例中，形成具有與圖6或圖7中之組態類似的組態的半導體結構200。 在本發明中，揭示一種半導體結構。該半導體結構包括置放於互連結構上方之第一晶粒、環繞該第一晶粒之模塑物、置放於該第一晶粒及該模塑物上方之第二晶粒及延伸穿過該模塑物以將該第一晶粒與該第二晶粒電連接之通路。如此，該第一晶粒與該第二晶粒之間的電通信速度可增加，操作功率可降低，且該半導體結構之總體尺寸可最小化。 在一些實施例中，一種半導體結構包括：第一晶粒，其包括第一表面及與該第一表面相對的第二表面；模塑物，其環繞該第一晶粒；通路，其延伸穿過該模塑物；互連結構，其包括介電層及導電部件，其中該介電層置放於該第一晶粒之該第一表面及該模塑物下方，且該導電部件置放於該介電層內；及第二晶粒，其置放於該模塑物上方，其中該第二晶粒電連接至該通路。 在一些實施例中，該第二晶粒至少部分地與該第一晶粒重疊。在一些實施例中，該第二晶粒置放於該第一晶粒之該第二表面的至少一部分上方。在一些實施例中，該第二晶粒藉由該通路電連接至導電結構。在一些實施例中，該第一晶粒之該第二表面自該模塑物曝露。在一些實施例中，該第二晶粒自該模塑物曝露。在一些實施例中，該第一晶粒置放成鄰近於該通路。在一些實施例中，該半導體結構進一步包括蓋，該蓋置放於該第一晶粒之該第二表面上方且經組態以耗散來自該第一晶粒之熱。在一些實施例中，該蓋之一部分置放於該第二晶粒上方。 在一些實施例中，一種半導體結構包括：第一晶粒，其包括第一表面及與該第一表面相對的第二表面；模塑物，其環繞該第一晶粒；通路，其延伸穿過該模塑物；互連結構，其包括介電層及導電部件，其中該介電層置放於該第一晶粒之該第一表面及該模塑物下方，且該導電部件置放於該介電層內；第二晶粒，其置放於該模塑物及該通路上方；基板，其包括面對該互連結構之第三表面及與該第三表面相對的第四表面；第一導電凸塊，其置放於該互連結構與該基板之該第三表面之間；及第二導電凸塊，其置放於該基板之該第四表面上方，其中該第二晶粒置放於該第一晶粒之該第二表面的至少一部分上方。 在一些實施例中，該第一晶粒藉由該通路及該導電部件電連接至該第二晶粒。在一些實施例中，該第二晶粒與該通路或該導電部件電隔離。在一些實施例中，該第一晶粒為邏輯晶粒，且該第二晶粒為高頻寬記憶體(HBM)晶粒。在一些實施例中，該半導體結構進一步包括置放於該基板之該第三表面上方且環繞該第一導電凸塊之第一底膠。在一些實施例中，該第一底膠與該介電層之側壁接觸。在一些實施例中，該半導體結構進一步包括置放於該模塑物與該第二晶粒之間的第二底膠。在一些實施例中，該第二底膠與該第一晶粒之該第二表面的至少一部分接觸。 在一些實施例中，一種製造半導體結構之方法包括：形成互連結構，該互連結構包括介電層及置放於該介電層內之導電部件；在該互連結構上方形成通路；在該互連結構上方置放第一晶粒；在該互連結構上方及圍繞該第一晶粒及該通路形成模塑物；及在該模塑物上方置放第二晶粒，其中該第二晶粒電連接至該通路。 在一些實施例中，該第二晶粒置放於該第一晶粒的至少一部分上方。在一些實施例中，該方法進一步包括：提供基板；在該互連結構與該基板之間置放第一導電凸塊；在該互連結構與該基板之間及圍繞該第一導電凸塊置放第一底膠；及在該模塑物與該第二晶粒之間置放第二底膠。 前述內容概述複數個實施例之構件，使得熟習此項技術者可更佳地理解本發明之範疇。熟習此項技術者應瞭解，其可容易地使用本發明作為用於設計或修改其他過程及結構以用於執行本文中所介紹之實施例之相同目的及/或實現本文中所介紹之實施例之相同優點的基礎。熟習此項技術者亦應認識到，此類等效構造不背離本發明之精神及範疇，且其可在本文中在不背離本發明之精神及範疇之情況下做出各種改變、替代及更改。
100‧‧‧半導體結構101‧‧‧第一晶粒101a‧‧‧第一表面101b‧‧‧第二表面101c‧‧‧側壁101d‧‧‧第一連接器101e‧‧‧第一底膠102‧‧‧模塑物103‧‧‧通路104‧‧‧互連結構104a‧‧‧介電層104b‧‧‧導電部件104b-1‧‧‧連接盤部分104b-2‧‧‧通路部分105‧‧‧第二晶粒105a‧‧‧第三表面105b‧‧‧第四表面105c‧‧‧側壁105d‧‧‧第二連接器105e‧‧‧第二底膠106‧‧‧第一導電凸塊107‧‧‧第三底膠107a‧‧‧介電層108‧‧‧基板108a‧‧‧第五表面108b‧‧‧第六表面108c‧‧‧接墊109‧‧‧第二導電凸塊110‧‧‧蓋111‧‧‧孔隙112‧‧‧載體200‧‧‧半導體結構300‧‧‧方法301‧‧‧操作302‧‧‧操作303‧‧‧操作304‧‧‧操作305‧‧‧操作
當與附圖一起閱讀時，自以下詳細描述最佳地理解本發明之各態樣。應強調，根據工業中之標準實踐，各種構件未按比例繪製。實際上，為論述清晰起見，可任意地增加或減小各種構件之尺寸。 圖1為說明根據本發明之一些實施例之半導體結構之示意性橫截面圖。 圖2至圖5為各種配置中之半導體結構之晶粒之示意性俯視橫截面圖。 圖6為根據本發明之一些實施例之半導體結構之示意性橫截面圖。 圖7為根據本發明之一些實施例之半導體結構之示意性橫截面圖。 圖8為根據本發明之一些實施例之製造半導體結構之方法的流程圖。 圖8A至圖8I為根據本發明之一些實施例之藉由圖8之方法製造半導體結構的示意圖。
100‧‧‧半導體結構
101‧‧‧第一晶粒
101a‧‧‧第一表面
101b‧‧‧第二表面
101c‧‧‧側壁
101d‧‧‧第一連接器
101e‧‧‧第一底膠
102‧‧‧模塑物
103‧‧‧通路
104‧‧‧互連結構
104a‧‧‧介電層
104b‧‧‧導電部件
104b-1‧‧‧連接盤部分
104b-2‧‧‧通路部分
105‧‧‧第二晶粒
105a‧‧‧第三表面
105b‧‧‧第四表面
105c‧‧‧側壁
105d‧‧‧第二連接器
105e‧‧‧第二底膠
106‧‧‧第一導電凸塊
107‧‧‧第三底膠
108‧‧‧基板
108a‧‧‧第五表面
108b‧‧‧第六表面
108c‧‧‧接墊
109‧‧‧第二導電凸塊

Claims (10)

  1. 一種半導體結構，其包含：一第一晶粒，其包括一第一表面、與該第一表面相對的一第二表面及位於該第一表面與該第二表面之間的一側壁；一模塑物，其環繞該第一晶粒；一通路，其延伸穿過該模塑物；一互連結構，其包括一介電層及一導電部件，其中該介電層置放於該第一晶粒之該第一表面及該模塑物下方，且該導電部件置放於該介電層內；一第二晶粒，其置放於該模塑物上方且包含面對該第一晶粒的一第三表面、與該第三表面相對的一第四表面及位於該第三表面與該第四表面之間的一側壁；一連接器，其置放於該第二晶粒與該通路之間且與該第二晶粒之該第三表面及該通路接觸；及一底膠，其環繞該連接器，其中該底膠與該第一晶粒之該第二表面的一部分接觸，且該底膠完全暴露該第一晶粒之該第一表面和該第一晶粒之該側壁，其中該第二晶粒電連接至該通路，且該底膠覆蓋該第二晶粒之該側壁的一部分且完全暴露該第二晶粒之該第四表面。
  2. 如請求項1之半導體結構，其中該第二晶粒至少部分地與該第一晶粒重疊。
  3. 如請求項1之半導體結構，其進一步包含一蓋，該蓋置放於該第一晶粒之該第二表面上方且經組態以耗散來自該第一晶粒的熱。
  4. 一種半導體結構，其包含：一第一晶粒，其包含一第一表面及與該第一表面相對的一第二表面；一模塑物，其環繞該第一晶粒；一通路，其延伸穿過該模塑物；一互連結構，其包含一介電層及一導電部件，其中該介電層置放於該第一晶粒之該第一表面及該模塑物下方，且該導電部件置放於該介電層內；一第二晶粒，其置放於該模塑物及該通路上方且包含面對該第一晶粒的一第三表面、與該第三表面相對的一第四表面及位於該第三表面與該第四表面之間的一側壁；一第一底膠，其置放於該模塑物與該第二晶粒之間且覆蓋該第二晶粒之該側壁的一部分且完全暴露該第二晶粒之該第四表面，其中該第一底膠接觸該第一晶粒之該第二表面且完全暴露該第一晶粒之該第一表面；一基板，其包含面對該互連結構的一第五表面及與該第五表面相對的一第六表面；一第一導電凸塊，其置放於該互連結構與該基板之該第五表面之間；及一第二導電凸塊，其置放於該基板之該第六表面上方， 其中該第二晶粒置放於該第一晶粒之該第二表面之至少一部分上方。
  5. 如請求項4之半導體結構，其進一步包含置放於該基板之該第五表面上方且環繞該第一導電凸塊的一第二底膠。
  6. 一種製造半導體結構之方法，其包含：形成包含一介電層及置放於該介電層內之一導電部件的一互連結構；在該形成該互連結構之後，在該互連結構上方形成一通路；在該互連結構上方置放一第一晶粒，其中該第一晶粒包括一第一表面及與該第一表面相對的一第二表面；在該在該互連結構上方置放該第一晶粒之後，在該互連結構上方且圍繞該第一晶粒及該通路形成一模塑物；在該模塑物上方置放一第二晶粒；提供一基板；在該互連結構與該基板之間置放一第一導電凸塊；在該互連結構與該基板之間且圍繞該第一導電凸塊置放第一底膠；及在該模塑物與該第二晶粒之間置放一第二底膠，其中該第二底膠接觸該第一晶粒之該第二表面且完全暴露該第一晶粒之該第一表面，其中將一連接器置放於該第二晶粒與該通路之間且與該通路接觸，且該第二晶粒藉由該連接器電連接至該通路。
  7. 一種半導體結構，其包含：一第一晶粒，其包含一第一表面及與該第一表面相對的一第二表面；一模塑物，其環繞該第一晶粒；一通路，其延伸穿過該模塑物；一第二晶粒，其置放於該模塑物上方且包含面對該第一晶粒的一第三表面、與該第三表面相對的一第四表面及位於該第三表面與該第四表面之間的一側壁；一連接器，其置放於該第二晶粒與該通路之間且與該第二晶粒之該第三表面及該通路接觸；及一底膠，其環繞該連接器，其中該第二晶粒電連接至該通路，該底膠覆蓋該第二晶粒之該側壁的一部分及該第一晶粒之該第二表面的一部分，該底膠接觸該第一晶粒之該第二表面，且該底膠完全暴露該第一晶粒之該第一表面和該第二晶粒之該第四表面。
  8. 一種半導體結構，其包含：一第一晶粒；一模塑物，其環繞該第一晶粒；一通路，其延伸穿過該模塑物；一第二晶粒，其置放於該模塑物及該第一晶粒上方且電連接至該通路； 一基板，其置放於該第一晶粒下方；及一蓋，其置放於該第一晶粒及該第二晶粒上方，其中該蓋與該第二晶粒分開，該蓋之一第一部分與該第一晶粒接觸，且該蓋之一第二部分與該基板接觸。
  9. 如請求項8該之半導體結構，其進一步包含：一互連結構，其置放於該基板與該第一晶粒之間及該基板與該模塑物之間；及一第一導電凸塊，其置放於該互連結構與該基板之間。
  10. 一種半導體結構，其包含：一互連結構；一第一晶粒，其置放於該互連結構上方，其中該第一晶粒包括一第一表面及與該第一表面相對的一第二表面；一模塑物，其置放於該互連結構上方且環繞該第一晶粒；一通路，其延伸穿過該模塑物且電連接至該互連結構；一第二晶粒，其置放於該第一晶粒及該模塑物上方；一第一連接器，其置放於該第一晶粒與該互連結構之間；一第二連接器，其置放於該第二晶粒與該通路之間；一第一底膠，其環繞該第一連接器；及一第二底膠，其環繞該第二連接器，其中該第二底膠覆蓋該第二晶粒之側壁的一部分且暴露該第二晶粒之該側壁的一部分，該第二底膠接觸該第一晶粒之該第二表面且完全暴露該第一晶粒之該第一表面。
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