JP6415365B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
- Publication number
- JP6415365B2 JP6415365B2 JP2015054934A JP2015054934A JP6415365B2 JP 6415365 B2 JP6415365 B2 JP 6415365B2 JP 2015054934 A JP2015054934 A JP 2015054934A JP 2015054934 A JP2015054934 A JP 2015054934A JP 6415365 B2 JP6415365 B2 JP 6415365B2
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- Prior art keywords
- semiconductor package
- conductive layer
- disposed
- circuit board
- package
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Description
本発明の実施形態1に係る積層型半導体パッケージ100の概要について、図1乃至図3を参照しながら、詳細に説明する。
図1は、本発明の実施形態1に係る積層型半導体パッケージ100の、図3におけるA−A’断面図を示したものである。図1を参照すると、第1の半導体パッケージ10と第2の半導体パッケージ20が半田ボール31を介して接合され、第1の半導体パッケージ10の上に第2の半導体パッケージ20が積層されていることがわかる。
本発明の実施形態1に係る積層型半導体パッケージ100は、第1の半導体パッケージ10に、導電層14及びサーマルビア15が配置される。
本発明の実施形態1に係る積層型半導体パッケージ100の変形例1を、図4を参照しながら、詳細に説明する。
本発明の実施形態1に係る積層型半導体パッケージ100の変形例2を、図5及び図6を参照しながら、詳細に説明する。
本発明の実施形態2に係る積層型半導体パッケージ100の概要について、図7及び図8を参照しながら詳細に説明する。
本発明の実施形態3に係る積層型半導体パッケージ100の概要について、図9を参照しながら詳細に説明する。
本発明の実施形態4に係る積層型半導体パッケージ100の概要について、図10を参照しながら説明する。
本発明の実施形態5に係る積層型半導体パッケージ100の概要について、図11及び図12を参照しながら詳細に説明する。
本発明の実施形態6に係る積層型半導体パッケージ100の概要について、図13及び図14を参照しながら詳細に説明する。
以下、従来技術に係るPoPと、本発明の実施形態1、実施形態2及び実施形態5に対応する実施例1〜3について、放熱効果をシミュレーション解析した結果を述べる。
比較例の解析対象は、従来技術に係る上下二層のPoPである。上段パッケージは216pinBGAとし、チップサイズを10.0[mm]×10.0[mm]×0.10[mmt]、発熱量を1.5[W]とした。また、下段パッケージは312pinBGAとし、チップサイズを7.0[mm]×7.0[mm]×0.08[mmt]、発熱量を2.5[W]とした。さらに、実装基板としてJEDEC標準4層基板(101.5[mm]×114.5[mm]×1.6[mmt])、環境温度を25[degC]、解析パラメータをTj(各チップの最高温度[degC])とした。上段パッケージの基板は2層(SR:0.03、Cu:0.02、コア:0.05、Cu:0.02、SR:0.03)とし、層厚は0.15[mm]とした。上段パッケージの基板とチップは、ボンディングワイヤ(ワイヤ直径:18[μm]、平均長さ:1.5[mm]、本数:300本、材質:Cu)で接続するものとした。上段パッケージの樹脂モールドは厚さを0.4[mm]、熱伝導率を0.6[W/mK]とした。上段パッケージの基板のうち配線層で覆われた部分の割合は、Top(L1):30%、Bottom(L2):40%とした。下段パッケージの基板は4層(SR:0.03、Cu:0.02、コア:0.05、Cu:0.02、コア:0.06、Cu:0.02、コア:0.05、Cu:0.02、SR:0.03)とし、層厚は0.3[mm]とした。下段パッケージの基板とチップは、バンプ(寸法:27×49[μm]、厚さ:43[μm]、数:742pin、材質:Cu(30μm厚)+SnAg(13μm厚)。SnAgが基板と接続する。)とした。下段パッケージの樹脂モールドは、厚さを0.25[mm]、熱伝導率を0.6[W/mK]とした。下段パッケージの基板のうち配線層で覆われた部分の割合は、Top(L1):30%、L2:80%、L3:80%、Bottom(L4):40%とした。上段パッケージと下段パッケージを接続する半田ボールの厚さを0.02[mm]、下段パッケージと実装基板とを接続する半田ボールの厚さを0.2[mm]とし、それぞれの半田ボールの熱伝導率は64.2[W/mK]とした。
実施例1は、本発明の実施形態1に対応しており、下段パッケージの上面に導電層を配置した。導電層の面積は10.0[mm]×10.0[mm]、厚さは0.05[mm]、材質はCu(熱伝導率390[W/mK])とした。また、サーマルビアの直径を0.15[mm]、材質をCuとし、下段パッケージのチップ周辺で、ビア16の内側に1周分、0.4[mm]ピッチでフルに、計96個配置した。その他の構成は、比較例と同様である。
実施例2は、本発明の実施形態2に対応しており、下段パッケージの上面及び側面に導電層を配置し、側面の導電層は実装基板に接続させた。側面に導電層を配置し、実装基板に接続させたこと以外は、実施例1と同様である。
実施例3は、本発明の実施形態5に対応しており、下段パッケージの封止樹脂の内部に導電層を配置し、導電層は接着材を介してチップと接している。ここで、導電層は、寸法が10.0×10.0×0.1[mm]であり、材質はCu(熱伝導率390[W/mK])とした。また、導電層とチップを接続する接着剤は、厚さ0.01[mm]、熱伝導率を60[W/mK]とし、チップ上面の全体に塗布されているものとした。その他の構成は、実施例1と同様である。
表1に、比較例、実施例1、実施例2及び実施例3について、放熱効果を解析した結果を示す。ここで、Tjはチップの最高温度、θJAはθJA=(Tj−Ta)/Powerの関係式で表現される熱抵抗、Taは環境温度(25[degC])、Powerは上段チップ及び下段チップの合計消費電力4[W]である。θJA変化率は、比較例の熱抵抗と各実施例の熱抵抗とを比較した変化率を表している。
11:第1の回路基板
12:第1の半導体素子
13:封止樹脂
14:導電層
15:サーマルビア
16:ビア
17:接合用電極端子
18:配線
19:導電部材
20:第2の半導体パッケージ
21:第2の回路基板
22:第2の半導体素子
23:封止樹脂
31:半田ボール
32:樹脂コアボール
34:ボンディングワイヤ
35:半田ボール
60:断熱層
70:配線基板
100:積層型半導体パッケージ
Claims (8)
- 第1の回路基板と、
前記第1の回路基板に第1の半導体素子が実装された第1の半導体パッケージと、
第2の回路基板と、
前記第2の回路基板に第2の半導体素子が実装され、前記第1の半導体パッケージに積層された第2の半導体パッケージと、
前記第1の半導体素子を封止する封止樹脂と、
前記封止樹脂に接して配置される導電層と、
前記第1の半導体パッケージと前記第2の半導体パッケージとを接合する複数の接合用電極端子と、
前記導電層と接続し前記第1の回路基板上に配置されるサーマルビアと、を有し、
前記複数の接合用電極端子は前記第1の半導体素子の周囲に配置され、
前記導電層は、前記第1の半導体素子の全体を覆い、一部の領域が前記接合用電極端子の領域に延長され、前記サーマルビアは前記複数の接合用電極端子の一部が置換えられて配置されている積層型半導体パッケージ。 - 前記導電層は、前記封止樹脂の上に配置されることを特徴とする、請求項1に記載の積層型半導体パッケージ。
- 前記導電層は、前記複数の接合用電極端子の内側に配置される、
ことを特徴とする請求項2に記載の積層型半導体パッケージ。 - 前記導電層は、銅又は銅合金であることを特徴とする請求項1に記載の積層型半導体パッケージ。
- 前記サーマルビアは、前記封止樹脂内の第1のサーマルビアと、前記第1の回路基板に形成される第2のサーマルビアと、を有し、
前記第1のサーマルビアと前記第2のサーマルビアとの間に、前記第1の半導体素子と接続される配線が介在していることを特徴とする請求項1に記載の積層型半導体パッケージ。 - 前記複数の接合用電極端子は樹脂コアボールを有することを特徴とする請求項2に記載の積層型半導体パッケージ。
- 前記導電層は前記封止樹脂に覆われていることを特徴とする、請求項1に記載の積層型半導体パッケージ。
- 前記導電層は前記第1の半導体素子上に接着剤又はスペーサを介して配置されることを特徴とする、請求項7に記載の積層型半導体パッケージ。
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CN202010516134.4A CN111627871A (zh) | 2014-03-28 | 2015-03-25 | 半导体封装件 |
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