CN111627871A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN111627871A
CN111627871A CN202010516134.4A CN202010516134A CN111627871A CN 111627871 A CN111627871 A CN 111627871A CN 202010516134 A CN202010516134 A CN 202010516134A CN 111627871 A CN111627871 A CN 111627871A
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China
Prior art keywords
semiconductor
semiconductor package
conductive layer
sealing resin
package
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Pending
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CN202010516134.4A
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English (en)
Inventor
宫腰武
细山田澄和
熊谷欣一
近井智哉
中村慎吾
松原宽明
作元祥太朗
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Amkor Technology Japan Inc
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J Devices Corp
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Publication of CN111627871A publication Critical patent/CN111627871A/zh
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本发明的一个实施方式的层叠型半导体封装件具有：第一电路基板；在第一电路基板上安装第一半导体元件而形成的第一半导体封装件；第二电路基板；在第二电路基板上安装第二半导体元件而形成的第二半导体封装件，第二半导体封装件层叠于第一半导体封装件；密封树脂，用于密封第一半导体；导电层，以与密封树脂相接的方式配置；以及散热通孔，与导电层相连接，并配置在第一电路基板上。

Description

半导体封装件
(相关申请的交叉引用)
本申请主张2014年3月28日提交的日本专利申请No.2014-069881和2015年3月18日提交的日本专利申请No.2015-054934的优先权，其全部内容通过参照的方式引用至此。
技术领域
本发明涉及半导体封装件的安装技术。尤其涉及用于减少层叠型半导体封装件中从下侧封装件向上侧封装件传递的热量的结构。
背景技术
近些年，伴随电子设备的小型化/高密度化或针对半导体元件的存取速度的提高等需求，正在利用层叠多个半导体封装件的层叠封装件(Pop：Package on Package)(例如，“日本特开2010-153651号公报”)。在手机或智能手机等便携式终端中，正在利用将包含用于进行图像处理的逻辑芯片的封装件设在下侧并将包含存储芯片的封装件设在上侧的半导体封装件。
在这种层叠型半导体封装件中，芯片之间的距离有时接近至1mm以下程度，存在从下侧的逻辑芯片发出的热量向上侧的存储芯片传递而导致上侧的存储芯片发生故障的情况。因此，正在寻求减少从下侧封装件向上侧封装件传递的热量的措施。
本发明的目的在于提供一种用于减少层叠型半导体封装件中从下侧的芯片向上侧的芯片传递的热量的半导体封装件。
发明内容
本发明一实施方式的层叠型半导体封装件具有：第一电路基板；在第一电路基板上安装第一半导体元件而形成的第一半导体封装件；第二电路基板；在第二电路基板上安装第二半导体元件而形成的第二半导体封装件，第二半导体封装件层叠于第一半导体封装件；密封树脂，用于密封第一半导体；导电层，以与密封树脂相接的方式配置；以及散热通孔，与导电层相连接，并配置在第一电路基板上。
另外，导电层可配置在密封树脂之上。
另外，第一半导体封装件可具有与第二半导体封装件相接合并配置于第一半导体的周围的多个接合用电极端子；导电层可配置于多个接合用电极端子的内侧。
另外，导电层可以为铜或铜合金。
另外，散热通孔可以配置在与接合用电极端子相比更靠内侧。
另外，多个接合用电极端子可具有树脂芯球。
另外，导电层还可配置于第一半导体封装件的侧面。
另外，导电层可被密封树脂覆盖。
另外，导电层可借助粘结剂或间隔件(spacer)而配置在第一半导体上。
另外，导电层可以为两层以上的布线基板。
另外，在两层以上的布线基板及密封树脂可配置有通孔(via)；第一电路基板和第二电路基板可经由通孔而电连接。
另外，在密封树脂上可配置有通孔；第一电路基板和第二电路基板可经由通孔和两层以上的布线基板的电路而电连接。
另外，本发明一个实施方式的层叠型半导体封装件具有：第一电路基板；在第一电路基板上安装了第一半导体元件而形成的第一半导体封装件；第二电路基板；在第二电路基板上安装第二半导体元件而形成的第二半导体封装件，第二半导体封装件层叠于第一半导体封装件；密封树脂，用于密封第一半导体；以及绝热层，以与密封树脂相接的方式配置。
附图说明
图1为本发明实施方式1的层叠型半导体封装件的剖视图。
图2为本发明实施方式1的层叠型半导体封装件的简要俯视图。
图3为本发明实施方式1的层叠型半导体封装件的简要俯视图。
图4为本发明实施方式1的变形例1的层叠型半导体封装件的简要俯视图。
图5为本发明实施方式1的变形例2的层叠型半导体封装件的剖视图。
图6为本发明实施方式1的变形例2的层叠型半导体封装件的剖视图。
图7为本发明实施方式2的层叠型半导体封装件的剖视图。
图8为本发明实施方式2的层叠型半导体封装件的简要俯视图。
图9为本发明实施方式3的层叠型半导体封装件的剖视图。
图10为本发明实施方式4的层叠型半导体封装件的剖视图。
图11为本发明实施方式5的层叠型半导体封装件的剖视图。
图12为本发明实施方式5的层叠型半导体封装件的简要俯视图。
图13为本发明实施方式6的层叠型半导体封装件的剖视图。
图14为本发明实施方式6的层叠型半导体封装件的简要俯视图。
具体实施方式
以下，参照附图，对本发明的层叠型半导体封装件进行说明。只是，本发明的层叠型半导体封装件能够以多种不同的方式来实施，并不限定于以下所示的实施方式的记载内容而解释。此外，在本实施方式中的附图中，对于同一部分或具有相同的功能的部分，标注同一的附图标记，并省略其重复说明。
<实施方式1>
参照图1至图3，详细说明本发明实施方式1的层叠型半导体封装件100的概要。
(层叠型半导体封装件的基本结构)
图1为本发明实施方式1的层叠型半导体封装件100的图3的A-A’线剖视图。参照图1可知，第一半导体封装件10和第二半导体封装件20经由焊料球31而接合，在第一半导体封装件10上层叠有第二半导体封装件20。
第一半导体封装件10具有第一电路基板11，在第一电路基板11上配置有第一半导体元件12。第一电路基板11由一个或多个布线基板构成，在图1中示出了四层。第一半导体元件12例如配置有应用处理器(application processor)等，但并不局限于此。另外，在图1中，将第一半导体元件12作为一个半导体进行示出，也可以将多个半导体元件作为第一半导体元件12配置在第一电路基板11上。
密封树脂13配置成覆盖第一电路基板11及第一半导体元件12。密封树脂13保护第一半导体元件12和第一电路基板11的上部免受外部的水分或杂质混入，并防止第一电路基板11的翘曲。作为密封树脂13，可使用环氧树脂、氰酸酯树脂、丙烯酸树脂、聚酰亚胺树脂、硅树脂等。
在密封树脂13中配置有多个通孔(via)16。通孔16的下端与配置于第一电路基板11上的电极相粘结，通孔16的上端作为接合用电极端子17而从密封树脂13露出。焊料球31配置在接合用电极端子17上，并与配置于第二半导体封装件20的第二电路基板21的下侧的电极相连接。即，通孔16将第一半导体封装件10的第一电路基板11的布线与第二半导体封装件20的第二电路基板21的布线电连接。例如，通孔16可利用下述方法形成，即向通过蚀刻密封树脂13的规定的位置而形成的开口部埋入利用金属镀敷或蚀刻等而形成的金属材料，并使该金属材料粘结于配置在第一电路基板11上的电极。
第二半导体封装件20具有由一个或多个布线基板构成的第二电路基板21，在第二电路基板21上配置有第二半导体元件22。第二半导体元件22利用以Au或Cu等作为材料的键合线34与第二电路基板21的布线电连接。第二半导体元件22例如配置有闪存(FLASH)、同步动态随机存储器(SDRAM)等存储器。也可以将多个相同种类或不同种类的存储器并排配置在第二电路基板21上来作为第二半导体元件22。另外，也可以将多个存储器层叠地配置来作为第二半导体元件22。
密封树脂23配置成覆盖第二电路基板21及第二半导体元件22。密封树脂23由与上述密封树脂13相同的材质形成。另外，在第二电路基板21的下侧配置有与第二电路基板21的布线电连接的电极。第二电路基板21的下侧的电极和第一半导体封装件10的接合用电极端子17借助焊料球31相连接，因而第一电路基板11和第二电路基板21的各个布线经由焊料球31电连接。在第一电路基板11的下侧配置有电极，用于安装层叠型半导体封装件100的外部的安装基板经由配置于该电极的焊料球35而连接。
(用于减少从下侧的半导体元件向上侧的半导体元件传递的热量的结构)
本发明实施方式1的层叠型半导体封装件100在第一半导体封装件10上配置有导电层14及散热通孔15。
图2为从上侧观察本发明实施方式1的层叠型半导体封装件100的第一半导体封装件10的俯视图。参照图2，在矩形形状的第一半导体封装件10的外周周边在上下左右各配置有两列的多个接合用电极端子17。此外，如上所述，接合用电极端子17为通孔16(未图示)的上端，因而示出通孔16以与接合用电极端子17相同的方式配置。可知导电层14以被配置于第一半导体封装件10的外周附近的多个接合用电极端子17包围的方式配置于上述多个接合用电极端子17的内侧区域。
图3为从上侧观察本发明实施方式1的层叠型半导体封装件100的第一半导体封装件10的俯视图，是透视导电层14并示出第一半导体元件12的俯视位置的图。被虚线14a包围的部分表示配置导电层14的位置。另外，被虚线12a包围的部分表示配置第一半导体元件12的位置。
参照图3可知，导电层14被配置成将配置有第一半导体元件12的部分全部覆盖，配置为比配置有第一半导体元件12的部分宽。第一半导体元件12呈矩形形状，以包围上述第一半导体元件12的方式配置有矩形形状的导电层14，因而配置有导电层14而未配置第一半导体元件12的区域50形成为中空的矩形形状。
散热通孔15配置于区域50。参照图3，散热通孔15配置于区域50的各顶点附近和各边的中央附近的共计8个位置，但散热通孔15的配置的数量或在区域50内的位置并不局限于这些。
再次参照图1可知，导电层14形成于密封树脂13的表面，即形成于第一半导体封装件10的上侧的面。另外，导电层14配置在与配置于第一半导体封装件10的外周附近的接合用电极端子17(通孔16)相比靠内侧，配置为比配置第一半导体元件12的区域更宽的区域。散热通孔15配置于配置导电层14而不配置第一半导体元件12的区域50，在导电层14的下侧的面上连接有散热通孔15的上部。导电层14由热传导率高的部件形成，例如，也可以使用铜或铜合金。作为导电层14的形成方法，例如，可在形成密封树脂13之后，在形成导电层14的位置除去树脂。除去树脂的方法可利用机械、化学等方法，但没有特别的限制。之后，可在除去后的凹陷部填充铜膏并使其固化，或者也可以将在与散热通孔连接的面上设置有导电性粘结剂的金属制的板状部件配置/接合于凹陷部，据此来形成导电层14。
散热通孔15形成于密封树脂13及第一电路基板11。关于散热通孔15的形成方法，例如，首先，在第一电路基板11形成通孔并形成密封树脂13之后，在密封树脂13的规定的位置以与上述通孔16相同的方法形成散热通孔15即可。在这里，形成于第一电路基板11的通孔和形成于密封树脂13的通孔不一定要直接相连接，也可以在两者之间存在金属部件或布线等。在图1中，在形成于第一电路基板11的通孔和形成于密封树脂13的通孔之间存在布线18。散热通孔15的下端、即形成于第一电路基板11的通孔的下端到达至配置于第一电路基板11的下侧的导电部件19。在导电部件19上配置有焊料球35，上述导电部件19经由焊料球35与层叠型半导体封装件100的外部相连接。
根据本发明实施方式1的层叠型半导体封装件100，可使第一半导体元件12发出的热量经由导电层14及散热通孔15向第一半导体封装件10的下侧逃逸。由于可将从第一半导体元件12发出的热量的一部分向第一半导体封装件10的下侧传递，因而可减少从第一半导体元件12向配置于第一半导体封装件10的上侧的第二半导体封装件20的第二半导体元件22的热量的传递，可抑制第二半导体元件22发生故障。
(变形例1)
参照图4，详细说明本发明实施方式1的层叠型半导体封装件100的变形例1。
在上述实施方式1的说明中，说明了区域50的形状为中空的矩形形状，但区域50的形状并不局限于此。在图2及图3中，接合用电极端子17(通孔16)在第一半导体封装件10的周边部分配置为内侧和外侧的两列。与此相对，参照图4，采用了将图2及图3的内侧的通孔16的一部分替换为散热通孔15的结构。在图4中，区域50的外侧的形状呈凸凹状，但也可呈波线状。
通过具有上述结构，可确保配置第一半导体元件12的空间更宽。另外，可将第一半导体元件12和散热通孔15的距离缩短，因而可将第一半导体元件12发出的热量更加有效地经由导电层14及散热通孔15向第一半导体封装件10的下侧传递。
(变形例2)
参照图5及图6，详细说明本发明实施方式1的层叠型半导体封装件100的变形例2。
在上述实施方式1的说明中示出了导电层14利用铜或铜合金之类的热传导率高的部件。但是，本发明实施方式1的层叠型半导体封装件100的导电层14并不局限于由如上所述的单一部件构成。如图5及图6所示，可将两层以上的布线基板70作为导电层14来配置。该情况下，例如，可以在第一半导体封装件10的整个上表面配置两层以上的布线基板。
变形例2的第一半导体封装件10和第二半导体封装件20的连接可以采用各种方式。参照图5可知，在配置于第一半导体封装件10的上表面的两层以上的布线基板70和密封树脂13中配置通孔16，借助于焊料球31将通孔16的上端与配置于第二电路基板21的下侧的电极相连接。或者，如图6可知，在布线基板70上不配置通孔，而将布线基板70的下侧的端子与配置于密封树脂13的通孔16的上端相连接，并借助于焊料球31将布线基板70的上侧的端子与配置于第二电路基板21的下侧的电极相连接。该情况下，可在布线基板70的内部布设布线而将第一半导体封装件10与第二半导体封装件20的所期望的端子电连接。
<实施方式2>
参照图7及图8，详细说明本发明实施方式2的层叠型半导体封装件100的概要。
图7为本发明实施方式2的层叠型半导体封装件100的剖视图。图7与图1类似，导电层14以不与接合用电极端子17相接的方式还配置于配置有接合用电极端子17的第一半导体封装件10的周边部，另外，在配置到第一半导体封装件10的侧面为止这一点上，与图1不同。
导电层14还配置于第一半导体封装件10的侧面，即还配置于密封树脂13及第一电路基板11的侧面。如上所述，呈矩形形状的第一半导体封装件10的侧面存在4个面，优选地，在4个面的所有侧面配置导电层14。作为在侧面形成导电层14的方法，例如，也可以在形成密封树脂13之后，将在与密封树脂13连接的面上设置有粘结剂的金属制的板状部件配置/接合于密封树脂13及第一电路基板11的侧面，据此形成导电层14。
图8为从上侧观察本发明实施方式2的层叠型半导体封装件100的第一半导体封装件10的俯视图。参照图8可知，导电层14以遍及整个面的方式配置于第一半导体封装件10的上侧。但是，在导电层14与接合用电极端子17之间存在密封树脂13，导电层14不与接合用电极端子17电连接。由图8可知，导电层14配置到第一半导体封装件10的外缘为止，配置于第一半导体封装件10的上表面和侧面的导电层14在第一半导体封装件10的外缘部分连接着。
如上所述，根据实施方式2的层叠型半导体封装件100，导电层14除了配置在第一半导体封装件10的上表面之外，还配置到侧面为止。根据该结构，不仅可以将从第一半导体元件12发出的热量经由导电层14和散热通孔15向第一半导体封装件10的下侧传递，还可借助于配置于第一半导体封装件10的侧面的导电层14而向侧面传递热量。因此，可以进一步减少从第一半导体封装件10的第一半导体元件12向第二半导体封装件20的第二半导体元件22传递的热量，并可以抑制第二半导体元件22发生故障。
此外，从向第一半导体封装件10的侧面传热的观点来看，配置于侧面的导电层14的面积越宽则越优选。另外，若配置于第一半导体封装件10的侧面的导电层14的下端与用于安装层叠型半导体封装件100的安装基板等相连接，则可从侧面的导电层14向该基板传递热量，因而更优选。
<实施方式3>
参照图9，详细说明本发明实施方式3的层叠型半导体封装件100的概要。
图9为本发明实施方式3的层叠型半导体封装件100的剖视图。图9与图1相似，但第一半导体封装件10与第二半导体封装件20借助树脂芯球32相连接，在这一点上，与图1不同。
在图1中，由第一半导体元件12产生的热量的一部分经由焊料球31向第二半导体封装件20的第二半导体元件22传递。在实施方式3中，将热传导性比焊料球31低的树脂芯球32用于第一半导体封装件10与第二半导体封装件20的连接。通过采用这种结构，不仅可减少经由导电层14和散热通孔15向第一半导体封装件10的下侧传递的第一半导体元件12发出的热量，还可减少从第一半导体封装件10和第二半导体封装件20的连接部分向第二半导体元件22传递的热量。
<实施方式4>
参照图10，说明本发明实施方式4的层叠型半导体封装件100的概要。
图10为本发明实施方式4的层叠型半导体封装件100的剖视图。图10与图1类似，但与实施方式2相同地将导电层14配置到第一半导体封装件10的侧面为止，并且，与实施方式3相同地将第一半导体封装件10和第二半导体封装件20借助树脂芯球32相连接，在这两点上与图1不同。具有实施方式4的结构而产生的效果为在实施方式2中说明的效果和在实施方式3中说明的效果的叠加。
<实施方式5>
参照图11及图12，详细说明本发明实施方式5的层叠型半导体封装件100的概要。
图11为本发明实施方式5的层叠型半导体封装件100的剖视图。图11与图1类似，但导电层14形成于密封树脂13的内部而不形成于密封树脂13的表面，在这点上不同。
导电层14使用例如金属制的板状部件。导电层14经由例如银膏等粘结剂配置在第一半导体元件12上。或者，导电层14经由例如硅等间隔件配置在第一半导体元件12上。导电层14配置在第一半导体元件12上之后，利用密封树脂13将导电层14埋入密封树脂13中。进而，在密封树脂13的规定的位置利用蚀刻等形成散热通孔15用开口部，但利用蚀刻也会除去导电层14的一部分。通过向开口部埋入金属材料来形成散热通孔15，埋入于密封树脂13的导电层14与散热通孔15相连接。
图12为从上侧观察本发明实施方式5的层叠型半导体封装件100的第一半导体封装件10的俯视图。
根据实施方式5的层叠型半导体封装件100，第一半导体元件12和导电层14紧贴地配置，因而导电层14直接地传递从第一半导体元件12发出的热量，可以经由散热通孔15向第一半导体封装件10的下侧更有效地传递热量。由此，可以进一步减少从第一半导体封装件10的第一半导体元件12向第二半导体封装件20的第二半导体元件22传递的热量，抑制第二半导体元件22发生故障。
<实施方式6>
参照图13及图14，详细说明本发明实施方式6的层叠型半导体封装件100的概要。
图13为本发明实施方式6的层叠型半导体封装件100的剖视图。比较图13与图1可知，图1中在第一半导体封装件10的上表面形成有导电层14，但图13中配置有绝热层60，在这一点上是不同的。另外，图13中未配置图1中的散热通孔15，在这一点上也是不同的。
绝热层60利用例如无机绝缘膜等、具有低热传导率的树脂。密封树脂13的热传导率为约0.6[W/mK]，与此相对，用于绝热层60的具有低热传导率的树脂的热传导率为约0.2[W/mK]。绝热层60与密封树脂13相比，热传导率低，因而从第一半导体元件12发出的热量更多地向密封树脂13的横向传递。由此，可使经由位于密封树脂13的侧面或密封树脂13的下侧的第一电路基板11向第一半导体封装件10的下侧传递的热量增加，因而可以进一步减少从第一半导体封装件10的第一半导体元件12向第二半导体封装件20的第二半导体元件22传递的热量，抑制第二半导体元件22发生故障。
图14为从上侧观察本发明实施方式6的层叠型半导体封装件100的第一半导体封装件10的俯视图。比较图8与图14可知，在图8中，导电层14以不与接合用电极端子17相接触的方式配置于第一半导体封装件10的整个面上，与此相对，在图14中，绝热层60与接合用电极端子17相接触并配置于第一半导体封装件10的整个面上，在这点上，两者是不同的。
如上所述，绝热层60利用具有绝缘性的树脂，因而也可以与接合用电极端子17相接。因此，在第一半导体封装件10的形成方法中，在配置了密封树脂13之后，在密封树脂13上的整个面配置绝热层60，并保持该状态地，在规定的位置形成孔而可以配置通孔16。
<模拟>
以下，针对现有技术的层叠封装件(PoP)和与本发明的实施方式1、实施方式2及实施方式5相对应的实施例1～实施例3模拟散热效果并论述解析的结果。
(比较例)
比较例的解析对象为现有技术的上下二层的PoP。上层封装件采用216pinBGA(Ball Grid Array；球状引脚栅格阵列封装)，芯片尺寸为10.0[mm]×10.0[mm]×0.10[mmt]，发热量为1.5[W]。另外，下层封装件采用312pin BGA，芯片尺寸为7.0[mm]×7.0[mm]×0.08[mmt]，发热量为2.5[W]。进而，安装基板采用JEDEC(固态技术协会)标准4层基板(101.5[mm]×114.5[mm]×1.6[mmt])，将环境温度设为25[℃]，并将解析参数设为Tj(各芯片的最高温度(℃))。将上层封装件的基板设为2层(SR：0.03、Cu：0.02、芯(core)：0.05、Cu：0.02、SR：0.03)，层厚为0.15[mm]。上层封装件的基板和芯片借助于键合线(线直径：18[μm]、平均长度：1.5[mm]、根数：300根、材质：Cu)进行连接。将上层封装件的树脂模制件的厚度设为0.4[mm]，将热传导率设为0.6[W/mK]。上层封装件的基板中被布线层覆盖的部分的比例为：顶部(Top)(L1)：30％、底部(Bottom)(L2)：40％。将下层封装件的基板设为4层(SR：0.03、Cu：0.02、芯：0.05、Cu：0.02、芯：0.06、Cu：0.02、芯：0.05、Cu：0.02、SR：0.03)，并将层厚设为0.3[mm]。下层封装件的基板和芯片采用凸块(尺寸：27×49[μm]、厚度：43[μm]、数量：742pin、材质：Cu(30μm厚)+SnAg(13μm厚)。SnAg与基板相连接)。将下层封装件的树脂模制件的厚度设为0.25[mm]，并将热传导率设为0.6[W/mK]。下层封装件的基板中被布线层覆盖的部分的比例为顶部(Top)(L1)：30％、L2：80％、L3：80％、底部(Bottom)(L4)：40％。将用于连接上层封装件和下层封装件的焊料球的厚度设为0.02[mm]，将连接下层封装件和安装基板的焊料球的厚度设为0.2[mm]，并将各个焊料球的热传导率设为64.2[W/mK]。
(实施例1)
实施例1与本发明的实施方式1相对应，在下层封装件的上表面配置了导电层。将导电层的面积设为10.0[mm]×10.0[mm]，将厚度设为0.05[mm]，并使材质为Cu(热传导率390[W/mK])。另外，将散热通孔的直径设为0.15[mm]，使材质为Cu，并在下层封装件的芯片周边，在通孔16的内侧的1周以0.4[mm]的间距满满地共配置了96个。其他结构与比较例相同。
(实施例2)
实施例2与本发明的实施方式2相对应，在下层封装件的上表面及侧面配置导电层，使侧面的导电层与安装基板相连接。在侧面配置导电层，并与安装基板相连接，除此之外，与实施例1相同。
(实施例3)
实施例3与本发明的实施方式5相对应，在下层封装件的密封树脂的内部配置导电层，导电层经由粘结材料与芯片相接。在这里，将导电层的尺寸设为10.0×10.0×0.1[mm]，并将材质设为Cu(热传导率390[W/mK])。另外，将用于连接导电层和芯片的粘结剂的厚度形成为0.01[mm]，热传导率为60[W/mK]，并涂敷于芯片的整个上表面。其他结构与实施例1相同。
(解析结果)
在表1中示出了针对比较例、实施例1、实施例2及实施例3的散热效果进行解析的结果。在这里，Tj为芯片的最高温度，θJA为由θJA＝(Tj－Ta)/Power的关系式表示的热阻，Ta为环境温度(25[℃])，Power(功耗)为上层芯片及下层芯片的合计功耗4[W]。θJA变化率表示将比较例的热阻和各实施例的热阻进行比较的变化率。
【表1】
Figure BDA0002530156610000101
参照表1可知，各实施例的最高温度Tj及热阻θJA均低于比较例，并且，可抑制从下层封装件发出的热量向上层封装件传递。实施例1(在封装件的上表面配置导电层)的上层芯片的θJA变化率为-9.9％。认为该效果的取得是通过配置导电层和散热通孔而可以将从下层封装件的芯片发出的热量向封装件下侧传递而产生的。另外，将实施例1(在封装件的上表面配置导电层)和实施例2(在封装件的上表面及侧面配置导电层，侧面的导电层与安装基板相连接)的上层芯片的θJA变化率进行比较可知，实施例1为-9.9％，实施例2为-18.1％，实施例2比实施例1相比，热阻低至约2倍。认为这种效果差是由于实施例2在封装件的侧面配置导电层并与安装基板相连接，据此使从下层封装件的芯片发出的热量不仅经由散热通孔还从侧面的导电层向下侧传递而产生的。
将实施例1和实施例3(在下层封装件的密封树脂的内部配置导电层，导电层经由粘结材料与芯片相接的结构)的上层芯片的θJA变化率进行比较可知，实施例1为-9.9％，实施例3为-10.2％，实施例3与实施例1相比获得了一些效果改善。但是，比较下层芯片的θJA变化率可知，实施例1为-15.1％，实施例3为-18.7％，就下层芯片的θJA变化率而言，实施例3得到了进一步的改善。
以上，参照图1至图14说明了本发明的实施方式1至实施方式6，并通过模拟对效果进行了验证。此外，本发明并不局限于上述的实施方式，只要在不脱离要旨的范围内，就能够进行适当的变更。

Claims (21)

1.一种半导体设备，具有:
第一半导体封装件，包括:
第一电路基板，所述第一电路基板包含第一导电结构；
第一半导体组件，所述第一半导体组件在所述第一电路基板上；
密封树脂，所述密封树脂在所述第一电路基板上并且接触所述第一半导体组件；
导电层，所述导电层在所述密封树脂上并且在所述第一半导体组件上；以及
垂直金属材料，所述垂直金属材料在所述密封树脂中并且与所述导电层和所述第一导电结构耦接。
2.根据权利要求1所述的半导体设备，其中所述密封树脂具有凹陷部，所述垂直金属材料暴露于所述凹陷部中，并且所述导电层在所述凹陷部中与所述垂直金属材料接触。
3.根据权利要求1所述的半导体设备，其中所述垂直金属材料在其长度的至少一部份上完全垂直。
4.根据权利要求1所述的半导体设备，其中所述垂直金属材料在其长度的至少一部份上不是完全垂直。
5.根据权利要求1所述的半导体设备，其中所述导电层接触所述密封树脂。
6.根据权利要求1所述的半导体设备，其中所述导电层在所述密封树脂中。
7.根据权利要求1所述的半导体设备，其中所述导电层包括铜或铜合金。
8.根据权利要求1所述的半导体设备，其中粘结剂或间隔件在所述导电层和所述第一半导体组件之间。
9.根据权利要求1所述的半导体设备，其中所述导电层接触所述第一电路基板的横向侧。
10.根据权利要求1所述的半导体设备，其中所述导电层接触所述密封树脂的横向侧。
11.根据权利要求1所述的半导体设备，其中所述导电层包括固化于所述密封树脂上的导电材料。
12.根据权利要求1所述的半导体设备，其进一步包括多个内部互连件，所述多个内部互连件在所述密封树脂中并且与所述第一导电结构耦接。
13.根据权利要求12所述的半导体设备，其中所述导电层的一部分延伸到所述多个内部互连件的区域。
14.根据权利要求12所述的半导体设备，其中所述导电层被定位在所述多个内部互连件的内部。
15.根据权利要求12所述的半导体设备，其中所述垂直金属材料被定位以代替所述多个内部互连件的一部分。
16.根据权利要求1所述的半导体设备，其进一步包含:
第二半导体封装件，所述第二半导体封装件层叠于所述第一半导体封装件，所述第二半导体封装件包括:
第二电路基板，所述第二电路基板包含第二导电结构；
第二半导体组件，所述第二半导体组件在所述第二电路基板上；及
多个外部互连件，所述多个外部互连件与所述多个内部互连件及所述第二半导体结构耦接。
17.根据权利要求16所述的半导体设备，其中所述多个外部互连件的每一个包含树脂芯球。
18.根据权利要求16所述的半导体设备，其中藉由与所述第二半导体组件的上侧耦接的键合线而将所述第二半导体组件与所述第二电路基板的所述第二导电结构耦接。
19.一种半导体设备，包括:
第一半导体封装件，包括:
第一电路基板，所述第一电路基板包含第一导电结构；
第一半导体，所述第一半导体在所述第一电路基板上；
密封树脂，所述密封树脂在所述第一电路基板上并且与所述第一半导体组件接触；
导电层，所述导电层在所述密封树脂上并且在所述第一半导体组件上；
垂直金属材料，所述垂直金属材料在所述密封树脂中并且与所述导电层和所述第一导电结构耦接；
多个内部互连件，所述多个内部互连件在所述密封树脂中并且与所述第一导电结构耦接；
第二半导体封装件，所述第二半导体封装件层迭于所述第一半导体封装件上，所述第二半导体封装件包括:
第二电路基板包括第二导电结构；以及
在所述第二电路基板上的第二半导体组件，所述第二半导体封装件层叠于所述第一半导体封装件上；以及
多个外部互连件，所述多个外部互连件与所述多个内部互连件和所述第二导电结构耦接；
其中所述密封树脂具有凹陷部，所述垂直金属材料被曝露在所述凹陷部中，并且所述导电层在所述凹陷部中与所述垂直金属材料接触。
20.根据权利要求19所述的半导体设备，其中所述垂直金属材料在其长度的至少一部份上完全垂直。
21.根据权利要求19所述的半导体设备，其中所述垂直金属材料在其长度的至少一部份上不是完全垂直。
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