JP5489454B2 - 積層型半導体パッケージ - Google Patents
積層型半導体パッケージ Download PDFInfo
- Publication number
- JP5489454B2 JP5489454B2 JP2008331194A JP2008331194A JP5489454B2 JP 5489454 B2 JP5489454 B2 JP 5489454B2 JP 2008331194 A JP2008331194 A JP 2008331194A JP 2008331194 A JP2008331194 A JP 2008331194A JP 5489454 B2 JP5489454 B2 JP 5489454B2
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- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor package
- wiring board
- semiconductor
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は、本発明に係る第1実施形態の積層型半導体パッケージ11を示す断面図である。
次に第2実施形態の積層型半導体パッケージについて説明する。なお、本第2実施形態において、上記第1実施形態と同一の構成については、同一符号を付して説明を省略する。
次に、第3実施形態の積層型半導体パッケージについて説明する。なお、本第3実施形態において、上記第1実施形態と同一の構成については、同一符号を付して説明を省略する。
次に、第4実施形態の積層型半導体パッケージについて説明する。なお、本第3実施形態において、上記第3実施形態と同一の構成については、同一符号を付して説明を省略する。
2 第1のプリント配線基板(配線基板)
3 第1の接合用電極端子
4 第1の半導体パッケージ
5 第2の半導体素子
6 第2のプリント配線基板(配線基板)
7 第2の接合用電極端子(接合用電極端子)
8 第2の半導体パッケージ
9 アンダーフィル材(封止樹脂材)
10 低熱伝導性樹脂材
11,11A,11B,11C 積層型半導体パッケージ
Claims (5)
- 配線基板と、前記配線基板に実装された半導体素子と、を有する半導体パッケージを複数備え、前記複数の半導体パッケージが積み重ねられた積層型半導体パッケージにおいて、
互いに対向する2つの配線基板を接合する複数の接合用電極端子と、
前記2つの配線基板で挟まれた領域のうち、前記複数の接合用電極端子が設けられた領域と少なくとも1つの前記半導体素子が配置された領域とを仕切る仕切り部と、
前記複数の接合用電極端子が設けられた領域に充填され、前記仕切り部により前記2つの配線基板間に介在する前記半導体素子と非接触状態である封止樹脂材と、を備え、
前記仕切り部は、前記2つの配線基板の互いに対向する面上に形成され、互いに対向して配置された一対のダムを有することを特徴とする積層型半導体パッケージ。 - 前記2つの配線基板間に介在する前記半導体素子の周りに前記仕切り部によって空隙が形成されており、前記2つの配線基板間に介在する前記半導体素子が、前記空隙により前記封止樹脂材と非接触状態となっている、
ことを特徴とする請求項1に記載の積層型半導体パッケージ。 - 前記2つの配線基板間に介在する前記半導体素子を覆う、前記封止樹脂材よりも熱伝導率の低い低熱伝導性樹脂材を更に備えた、
ことを特徴とする請求項1に記載の積層型半導体パッケージ。 - 前記低熱伝導性樹脂材は、多孔性の材料である、
ことを特徴とする請求項3に記載の積層型半導体パッケージ。 - 前記低熱伝導性樹脂材は、前記2つの配線基板のうち、前記2つの配線基板間に介在する前記半導体素子が実装された配線基板に対向する配線基板に対して、非接触状態であることを特徴とする請求項3又は4に記載の積層型半導体パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008331194A JP5489454B2 (ja) | 2008-12-25 | 2008-12-25 | 積層型半導体パッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008331194A JP5489454B2 (ja) | 2008-12-25 | 2008-12-25 | 積層型半導体パッケージ |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010153651A JP2010153651A (ja) | 2010-07-08 |
JP2010153651A5 JP2010153651A5 (ja) | 2012-02-16 |
JP5489454B2 true JP5489454B2 (ja) | 2014-05-14 |
Family
ID=42572417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008331194A Expired - Fee Related JP5489454B2 (ja) | 2008-12-25 | 2008-12-25 | 積層型半導体パッケージ |
Country Status (1)
Country | Link |
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JP (1) | JP5489454B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101930689B1 (ko) | 2012-05-25 | 2018-12-19 | 삼성전자주식회사 | 반도체 장치 |
JP6415365B2 (ja) | 2014-03-28 | 2018-10-31 | 株式会社ジェイデバイス | 半導体パッケージ |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002009265A (ja) * | 2000-06-21 | 2002-01-11 | Sony Corp | 固体撮像装置 |
JP2003347722A (ja) * | 2002-05-23 | 2003-12-05 | Ibiden Co Ltd | 多層電子部品搭載用基板及びその製造方法 |
JP4436179B2 (ja) * | 2004-04-20 | 2010-03-24 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
JP2007251070A (ja) * | 2006-03-18 | 2007-09-27 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007281043A (ja) * | 2006-04-04 | 2007-10-25 | Matsushita Electric Ind Co Ltd | 半導体装置 |
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2008
- 2008-12-25 JP JP2008331194A patent/JP5489454B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2010153651A (ja) | 2010-07-08 |
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