JP2013239660A - 半導体装置及びその製造方法 - Google Patents
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
【解決手段】配線基板10と、配線基板10に接続端子32が接続された半導体チップ30と、配線基板10と半導体チップ30との隙間から半導体チップ30の周辺領域にかけて形成され、半導体チップ30の周辺領域において半導体チップ30の上面と同じ高さで形成されたアンダーフィル樹脂19と、半導体チップ30の上に接着剤層40によって固定され、半導体チップ30から外側に突き出る突出部52を備え、突出部52がアンダーフィル樹脂19の上に配置された補助部材50とを備え、補助部材50及び接着剤層40の熱膨張係数は半導体チップ30の熱膨張係数より大きいことを含む。
【選択図】図3
Description
図3〜図5は実施形態の半導体装置を示す図である。図3(a)の断面図に示すように、実施形態の半導体装置1の配線基板10は、コア基板をもたないコアレス基板であり、絶縁基材として第1絶縁層12とその上に積層された第2絶縁層14とを備える。
Claims (8)
- 配線基板と、
前記配線基板に接続端子が接続された半導体チップと、
前記配線基板と前記半導体チップとの隙間から前記半導体チップの周辺領域にかけて形成され、前記半導体チップの周辺領域において前記半導体チップの上面と同じ高さで形成されたアンダーフィル樹脂と、
前記半導体チップの上に接着剤層によって固定され、前記半導体チップから外側に突き出る突出部を備え、前記突出部が少なくとも前記アンダーフィル樹脂の上に配置された補助部材とを有し、
前記補助部材及び接着剤層の熱膨張係数は、前記半導体チップの熱膨張係数より大きいことを特徴とする半導体装置。 - 前記補助部材の熱膨張係数は、前記配線基板の熱膨張係数より大きいことを特徴とする請求項1に記載の半導体装置。
- 前記アンダーフィル樹脂及び前記補助部材の少なくとも側面を封止する封止樹脂を有することを特徴とする請求項1又は2に記載の半導体装置。
- 前記封止樹脂には、前記配線基板の前記半導体チップが搭載された面側の接続パッドに到達する開口部が形成されていることを特徴とする請求項3に記載の半導体装置。
- 前記補助部材は、樹脂又は繊維補強材含有樹脂から形成されることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
- 配線基板の上に樹脂材を形成する工程と、
半導体チップの接続端子を樹脂材に押し込んで前記配線基板の接続パッドに接続すると共に、前記半導体チップと前記配線基板との隙間から前記半導体チップの周辺領域にかけて前記樹脂材からアンダーフィル樹脂を形成し、前記半導体チップの周辺領域の前記アンダーフィル樹脂を前記半導体チップの上面と同じ高さで形成する工程と、
前記半導体チップの上に接着剤層を介して、前記半導体チップから外側に突き出る突出部を備えた補助部材を形成し、前記突出部を前記アンダーフィル樹脂の上に配置する工程と、
前記アンダーフィル樹脂及び前記補助部材の少なくとも側面を封止する封止樹脂を形成する工程とを有し、
前記補助部材及び前記接着剤層の熱膨張係数は、前記半導体チップの熱膨張係数より大きいことを特徴とする半導体装置の製造方法。 - 前記接着剤層は、前記封止樹脂を形成する工程で同時に硬化されることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記封止樹脂を形成する工程の後に、
前記半導体装置は、前記配線基板の下に設けられた外部接続端子が加熱処理を伴って実装基板に接続されることを特徴とする請求項6又は7に記載の半導体装置の製造方法。
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JP2012112990A JP5980566B2 (ja) | 2012-05-17 | 2012-05-17 | 半導体装置及びその製造方法 |
KR1020130049749A KR101997548B1 (ko) | 2012-05-17 | 2013-05-03 | 반도체 장치 및 그 제조 방법 |
US13/892,483 US9087781B2 (en) | 2012-05-17 | 2013-05-13 | Semiconductor device and method of manufacturing the same |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2016031579A1 (ja) * | 2014-08-26 | 2016-03-03 | 日東電工株式会社 | 半導体装置の製造方法及び封止用シート |
WO2018038134A1 (ja) * | 2016-08-23 | 2018-03-01 | 株式会社村田製作所 | 回路モジュール |
Families Citing this family (7)
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US9559064B2 (en) | 2013-12-04 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage control in package-on-package structures |
KR102250997B1 (ko) * | 2014-05-02 | 2021-05-12 | 삼성전자주식회사 | 반도체 패키지 |
CN106601629B (zh) * | 2015-10-15 | 2018-11-30 | 力成科技股份有限公司 | 保护片服贴于芯片感应面的芯片封装构造 |
US10242927B2 (en) | 2015-12-31 | 2019-03-26 | Mediatek Inc. | Semiconductor package, semiconductor device using the same and manufacturing method thereof |
US11264330B2 (en) | 2017-08-04 | 2022-03-01 | Nepes Co., Ltd. | Chip package with connection portion that passes through an encapsulation portion |
KR102144933B1 (ko) * | 2017-08-04 | 2020-08-18 | 주식회사 네패스 | 칩 패키지 및 그 제조방법 |
KR20220000107A (ko) | 2020-06-25 | 2022-01-03 | 에스케이하이닉스 주식회사 | 보강층을 가진 반도체 패키지 |
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WO2016031579A1 (ja) * | 2014-08-26 | 2016-03-03 | 日東電工株式会社 | 半導体装置の製造方法及び封止用シート |
WO2018038134A1 (ja) * | 2016-08-23 | 2018-03-01 | 株式会社村田製作所 | 回路モジュール |
US11049821B2 (en) | 2016-08-23 | 2021-06-29 | Murata Manufacturing Co., Ltd. | Circuit module |
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KR20130129100A (ko) | 2013-11-27 |
JP5980566B2 (ja) | 2016-08-31 |
US20130307163A1 (en) | 2013-11-21 |
US9087781B2 (en) | 2015-07-21 |
KR101997548B1 (ko) | 2019-07-09 |
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