WO2014042165A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- WO2014042165A1 WO2014042165A1 PCT/JP2013/074445 JP2013074445W WO2014042165A1 WO 2014042165 A1 WO2014042165 A1 WO 2014042165A1 JP 2013074445 W JP2013074445 W JP 2013074445W WO 2014042165 A1 WO2014042165 A1 WO 2014042165A1
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
- MCP Multi Chip Package
- a semiconductor device based on MCP is usually required to have a so-called overhang portion in which a part of an upper semiconductor chip protrudes from a lower semiconductor chip for wire bonding. In order to reinforce the overhang portion, such an overhang portion may cause chip cracks and warpage in the subsequent wire bonding and resin sealing processes in combination with the thinning of the semiconductor chip.
- the structure is necessary. As such a structure, a structure is known in which a bonding wire is disposed immediately below an overhang portion to serve as a support portion (Patent Document 1).
- a first aspect of the present invention includes a wiring board having a recess and a plurality of connection pads on one surface, a first semiconductor chip mounted in the recess, and a plurality of electrode pads on at least one end surface.
- the second semiconductor chip stacked on the first semiconductor chip, the plurality of connection pads of the wiring board, and the plurality of the second semiconductor chips so that at least one end portion protrudes from the first semiconductor chip.
- a plurality of wires that electrically connect each of the electrode pads, and the one end of the second semiconductor chip extends beyond the inner surface of the recess and is supported on one surface of the wiring board. This is a semiconductor device.
- a first semiconductor chip is mounted in the recess of a wiring board having a recess and a plurality of connection pads on one surface, and (b) a plurality of electrodes on the surface of at least one end.
- a second semiconductor chip having a pad is stacked on the first semiconductor chip so that at least one end protrudes from the first semiconductor chip, and (c) a plurality of connection pads of the wiring board and the second semiconductor Electrically connecting each of the plurality of electrode pads of the chip with wires, wherein (b) extends the one end of the second semiconductor chip beyond the inner surface of the recess.
- FIG. 1 is a plan view showing the semiconductor device 200 according to the first embodiment, and only a part of the sealing body 220 is illustrated.
- 2 is a cross-sectional view taken along line AA ′ of FIG. 3 is a cross-sectional view taken along the line BB ′ of FIG.
- FIG. 4 is a diagram showing a procedure for manufacturing the semiconductor device 200.
- FIG. 5 is a diagram showing a procedure for manufacturing the semiconductor device 200 and shows details of wire bonding.
- FIG. 6 is a diagram showing a procedure for manufacturing the semiconductor device 200 and shows details of resin sealing.
- FIG. 7 is a diagram showing a procedure for manufacturing the semiconductor device 200.
- FIG. 8 is a plan view showing the semiconductor device 200a according to the second embodiment, and only a part of the sealing body 220 is illustrated.
- FIG. 9 is a cross-sectional view taken along the line CC ′ of FIG. 10 is a cross-sectional view taken along the line DD ′ of FIG.
- FIG. 11 is a plan view showing a semiconductor device 200b according to the third embodiment, and only a part of the sealing body 220 is illustrated.
- 12 is a cross-sectional view taken along the line EE ′ of FIG. 13 is a cross-sectional view taken along the line FF ′ of FIG.
- FIG. 14 is a plan view showing a semiconductor device 200c according to the fourth embodiment, and only a part of the sealing body 220 is illustrated.
- 15 is a cross-sectional view taken along the line GG ′ of FIG.
- the semiconductor device 200 includes a wiring substrate 201 having a recess 111 and a plurality of connection pads 223 a, 223 b, 223 c, and 223 d on one surface, and a first semiconductor chip 203 mounted in the recess 111.
- the first semiconductor chip 203 has a plurality of electrode pads 107 a and 107 b on at least one end surface (here, both ends), and at least one end portion (here, both ends) protrudes from the first semiconductor chip 203.
- a plurality of wires 217 (electrically connecting the second semiconductor chip 205 stacked thereon, the plurality of connection pads 223a and 223c of the wiring substrate 201, and the plurality of electrode pads 107a and 107b of the second semiconductor chip 205, respectively.
- One end (here, both ends) of the second semiconductor chip 205 is the inner surface of the recess 111. And is supported on one surface of the wiring board 201.
- the semiconductor device 200 further includes wires 215 that connect the connection pads 223b and 223d of the wiring substrate 201 and the electrode pads 103a and 103b (described later) of the first semiconductor chip 203. Further, the semiconductor device 200 is connected to an external device. Solder balls 216 as external terminals for connection and a sealing body 220 disposed on one surface of the wiring substrate 201 and provided so as to cover one surface side of the wiring substrate 201 are provided.
- the wiring board 201 is composed of, for example, an insulating base material 219a (upper board layer) and an insulating base material 219b (lower board layer) made of a substantially rectangular plate-like glass epoxy, prepreg, and the like, and an upper insulating base material.
- the three wiring layers 123 are electrically connected by vias 124.
- An insulating film 221, for example, a solder resist film is formed on the upper surface of the insulating base material 219 a and the lower surface of the insulating base material 219 b, and a part of the wiring layer 123 is exposed from the insulating film 221.
- the portions exposed from the opening of the insulating film 221 of the wiring layer 123 on the upper surface of the insulating base material 219a form connection pads 223a, 223b, 223c, and 223d, and the opening of the insulating film 221 of the wiring layer 123 on the lower surface of the insulating base material 219b.
- a portion exposed from the surface forms a land 225. As shown in FIG.
- the plurality of connection pads 223a, 223b, 223c, and 223d are arranged in the vicinity of the peripheral portions of the four sides forming the quadrangle on the upper surface of the insulating base material 219a. It is electrically connected to the corresponding land 225 via 124.
- the plurality of lands 225 are arranged in a lattice pattern on the lower surface of the insulating base material 219b.
- the insulating base 219a has a rectangular opening 131 corresponding to the planar shape of the first semiconductor chip 203 formed in the central region, and the opening 131 and the insulating base 219b constitute a recess 111. Yes.
- the first semiconductor chip 203 has a substantially rectangular (rectangular) plate shape, and a predetermined circuit and electrode pads 103a and 103b are formed on one surface side.
- the plurality of electrode pads 103 a and 103 b are arranged along the rectangular short side of the first semiconductor chip 203.
- the first semiconductor chip 203 has a DAF (Die Attached Film) in the recess 111 of the wiring substrate 201 with the back surface side (the surface opposite to the surface on which the electrode pads 103a and 103b are provided) facing the wiring substrate 201.
- an adhesive paste 105 such as an insulating paste.
- the recess 111 is configured with a size that is approximately 100 ⁇ m larger than the chip size of the first semiconductor chip 203 in consideration of the mounting accuracy of the first semiconductor chip 203 and the filling property of the sealing body 220. A gap of about 50 ⁇ m is formed between the chips 203 for each side.
- the recess 111 may be configured to be large enough to support the wiring board 201 below at least electrode pads 107a and 107b (details will be described later) formed in the overhang portion 126 of the second semiconductor chip 205.
- the plurality of electrode pads 103a and 103b of the first semiconductor chip 203 and the corresponding connection pads 223b and 223d of the wiring board 201 are electrically connected by wires 215 such as Au and Cu.
- the second semiconductor chip 205 has a substantially rectangular (rectangular) plate shape, and predetermined circuits and electrode pads 107a and 107b are formed on one side.
- the plurality of electrode pads 107 a and 107 b are formed along the rectangular short side of the second semiconductor chip 205.
- the second semiconductor chip 205 is stacked on the first semiconductor chip 203 such that the back surface side (the surface side opposite to the surface on which the electrode pads 107 a and 107 b are provided) faces the first semiconductor chip 203. More specifically, the second semiconductor chip 205 is stacked via an adhesive member 105 such as DAF or insulating paste while being rotated by 90 degrees with respect to the first semiconductor chip 203.
- Two short sides are arranged so as to overhang from the first semiconductor chip 203.
- the two short-side overhang portions 126 of the second semiconductor chip 205 are bonded and held on one surface of the wiring board 201 via the bonding member 105. That is, the overhang portion 126 of the second semiconductor chip 205 extends beyond the inner surface of the recess 111 and is supported on one surface of the wiring substrate 201.
- the chip thickness of the second semiconductor chip 205 can be reduced (for example, 100 ⁇ m or less). It becomes.
- the plurality of electrode pads 107a and 107b of the second semiconductor chip 205 and the corresponding connection pads 223a and 223c of the wiring board 201 are electrically connected by wires 217 such as Au and Cu.
- a sealing body 220 is formed on one surface of the wiring board 201, and the first semiconductor chip 203, the second semiconductor chip 205, and the wires 215 and 217 mounted on the wiring board 201 are the sealing body 220. Covered.
- the gap between the recess 111 of the wiring substrate 201 and the first semiconductor chip 203 has a size that takes into account the filling properties of the sealing body 220, this gap is also filled with the sealing body 220.
- the semiconductor device 200 has a structure in which the overhang portion 126 of the second semiconductor chip 205 is supported on one surface of the wiring substrate 201, thereby reducing the thickness of the second semiconductor chip 205. Therefore, the sealing body 220 can be thinned by reducing the thickness of the second semiconductor chip 205. Further, solder balls 216 are respectively mounted on the plurality of lands 225 on the other surface of the wiring board 201. This completes the description of the details of the members that make up the semiconductor device 200. Next, a method for manufacturing the semiconductor device 200 will be described with reference to FIGS. First, a wiring mother board 300 shown in FIG.
- the wiring mother board 300 has a plurality of product forming parts 301 arranged in a matrix, and each product forming part 301 corresponds to the wiring board 201.
- the first semiconductor chip 203 is mounted on the product forming portion 301 of the wiring mother board 300 using a chip mounter (not shown) or the like.
- the first semiconductor chip 203 is mounted in the recess 111 so that the short side provided with the electrode pads 103a and 103b faces the connection pads 223b and 223d.
- the first semiconductor chip 203 is bonded and fixed to the wiring mother board 300 by an adhesive member 105 such as DAF provided on the other surface.
- connection pads 103a and 103b of the first semiconductor chip 203 and the corresponding connection pads 223b and 223d are connected by wires 215 (see FIG. 3).
- a wire bonding apparatus to be described later can be used for the connection using the wire 215.
- the connection is performed by, for example, ball bonding using an ultrasonic thermocompression bonding method. Specifically, the tip of the wire 215 on which a ball is formed by melting is subjected to ultrasonic thermocompression bonding on the electrode pads 103a and 103b, and the rear end of the wire 215 corresponds so that the wire 215 draws a predetermined loop shape. Ultrasonic thermocompression bonding is performed on the connection pads 223b and 223d.
- the wires 215 that connect the electrode pads 103a and 103b of the first semiconductor chip 203 and the connection pads 223b and 223d of the wiring board 201 are: Compared with the case where the first semiconductor chip 203 is laminated without providing the recess 111, the wire length can be shortened (see FIG. 3). The cost can be reduced by shortening the wire length. Moreover, by shortening the wire length, it is possible to suppress the occurrence of a wire short and a wire flow at the time of resin injection described later. Next, as shown in FIG.
- the second semiconductor chip 205 is mounted on the first semiconductor chip 203 using a chip mounter (not shown) or the like.
- the second semiconductor chip 205 exposes the electrode pads 103a, 103b (see FIG. 2) of the first semiconductor chip 203, and the wiring board 201 so that the overhang portion 126 faces the connection pads 223a, 223c. Are stacked on one side.
- the second semiconductor chip 205 is fixed to the first semiconductor chip 203 by an adhesive member 105 such as DAF provided on the other surface, and the overhang portion 126 is fixed to one surface of the wiring board 201.
- an adhesive member 105 such as DAF provided on the other surface
- the electrode pads 107 a and 107 b of the second semiconductor chip 205 and the corresponding connection pads 223 a and 223 c are connected by wires 217, respectively.
- the wiring mother board 300 on which the second semiconductor chip 205 is stacked and mounted is held on a stage of a wire bonding apparatus (not shown).
- the tip of the wire 217 led out from the tip of the capillary 41 is melted to form a ball at the tip of the wire 217.
- the tip of the wire on which the ball is formed is crimped by the capillary 41 onto the electrode pads 107a and 107b of the second semiconductor chip 205 by ultrasonic thermocompression bonding as shown in FIG.
- the overhang portion 126 (from the first semiconductor chip 203) of the second semiconductor chip 205 is configured to be bonded and fixed to one surface of the wiring substrate 201, the load from the capillary 41 and the ultrasonic wave Can be transmitted well to the electrode pads 107a and 107b. Thereafter, the capillary 41 is moved so that the wire 217 forms a predetermined loop, and the other end of the wire 217 is subjected to ultrasonic thermocompression bonding to the corresponding connection pads 223a and 223c of the wiring board 201 as shown in FIG. Crimp with.
- Wires 217 are formed to connect to each other.
- the overhang portion 126 (from the first semiconductor chip 203) of the second semiconductor chip 205 is configured to be bonded and fixed to one surface of the wiring substrate 201, the second semiconductor chip. Even when the chip thickness of 205 is reduced to, for example, 100 ⁇ m or less, wire bonding can be performed without generating chip cracks.
- the sealing body 220 is formed on one surface side of the wiring mother board 300 by batch molding. Specifically, first, the wiring mother board 300 is transferred to the molding apparatus 400.
- the molding apparatus 400 includes a molding die having an upper mold 401 and a lower mold 402 as shown in FIG. A cavity 403 is formed in the upper mold 401, and a recess 404 for mounting the wiring mother board 300 is formed in the lower mold 402.
- the wiring mother board 300 is set in the recess 404 of the lower mold 402 of the molding apparatus 400. Thereafter, the wiring mother board 300 is closed with the upper mold 401 and the lower mold 402, so that a cavity 403 and a gate portion 405 having a predetermined size are formed above the wiring mother board 300 as shown in FIG. It is formed.
- the cavity 403 is configured to have a size that covers the plurality of product forming portions 301 in a lump.
- the resin tablet 406 (see FIG. 6B) is supplied to the pot of the lower mold 402 and melted by heating. Next, as shown in FIG.
- the molten sealing resin 211 is injected into the cavity 403 from the gate portion 405 by the plunger 408, and the sealing resin 211 is filled into the cavity 403.
- the second semiconductor chip 205 since the overhang portion 126 of the second semiconductor chip 205 is configured to be bonded and held on one surface of the wiring substrate 201, the second semiconductor chip 205 has the first pressure due to the injection pressure when the sealing resin 211 is injected. The occurrence of bending of the second semiconductor chip 205 to the overhang portion 126 can be suppressed, and the load on the second semiconductor chip 205 can be reduced.
- the sealing resin 211 is filled in the cavity 403, the sealing resin 211 is cured by curing the sealing resin 211 at a predetermined temperature, for example, 180 ° C.
- FIG. 7A a sealing body 220 that collectively covers the sealing region of the wiring motherboard 300 is formed.
- FIG. 6D the gate portion 405, the runner portion 409, and the cull portion 410 connected to the sealing body 220 are removed.
- solder balls 216 are mounted on lands 225 on the other surface side of the wiring mother board 300, respectively.
- the solder balls 216 are held in the suction holes, and the held solder balls 216 are held. Are collectively mounted on the lands 225 of the wiring board 201 via a flux. After the solder balls 216 are mounted on all product forming portions 301, the solder balls 216 are fixed by reflowing the wiring board 201.
- the sealing body 220 is bonded to the dicing tape 251, and the sealing body 220 and the wiring mother board 300 are supported by the dicing tape 251.
- the wiring mother board 300 and the sealing body 220 are cut vertically and horizontally along the dicing line 234 (see FIG. 4A) using a dicing blade (not shown). Thereby, the wiring mother board 300 is separated into pieces for each product forming portion 301. Thereafter, the separated product forming portion 301 and sealing body 220 are picked up from the dicing tape 251 to obtain the semiconductor device 200 as shown in FIG.
- the semiconductor device 200 includes the wiring substrate 201 having the recess 111 and the plurality of connection pads 223a, 223b, 223c, and 223d on one surface, and the first mounted in the recess 111.
- the semiconductor chip 203 has a plurality of electrode pads 107 a and 107 b on the surface of at least one end, and a second stacked on the first semiconductor chip 203 so that at least one end protrudes from the first semiconductor chip 203.
- the semiconductor chip 205 includes a plurality of wires 217 that electrically connect the plurality of connection pads 223a and 223c of the wiring substrate 201 and the plurality of electrode pads 107a and 107b of the second semiconductor chip 205, respectively.
- One end portion (here, both ends) of 205 extends beyond the inner surface of the recess 111 and is supported on one surface of the wiring board 201. It is.
- the overhang portion 126 can be reliably supported by the wiring substrate 201, and wire bonding can be performed without generating a chip crack.
- the load and the ultrasonic wave from the capillary 41 can be transmitted well and the electrode pads 107a and 107b can be satisfactorily connected to each other, so that the reliability of the semiconductor device 200 can be improved.
- the semiconductor device 200 can be thinned.
- the second semiconductor chip 205 is stacked and mounted on the first semiconductor chip 203 using the adhesive member 105a, and the adhesive member 105a. Is filled in the gap between the recess 111 of the wiring substrate 201 and the first semiconductor chip 203.
- the gap between the recess 111 of the wiring board 201 and the first semiconductor chip 203 may be filled in advance with a material different from the sealing body 220 prior to resin sealing. With such a structure, it is possible to suppress the generation of voids in the gap between the recess 111 and the first semiconductor chip 203 when the sealing body 220 is formed.
- the manufacturing method of the semiconductor device 200a is the same as that of the first embodiment except that the gap between the recess 111 and the first semiconductor chip 203 is filled with the adhesive member 105a in advance prior to resin sealing. Is omitted.
- the semiconductor device 200a includes the wiring substrate 201 having the recess 111 and the plurality of connection pads 223a, 223b, 223c, and 223d on one surface, and the first mounted in the recess 111.
- the semiconductor chip 203 has a plurality of electrode pads 107 a and 107 b on the surface of at least one end, and a second stacked on the first semiconductor chip 203 so that at least one end protrudes from the first semiconductor chip 203.
- the semiconductor chip 205 includes a plurality of wires 217 that electrically connect the plurality of connection pads 223a and 223c of the wiring substrate 201 and the plurality of electrode pads 107a and 107b of the second semiconductor chip 205, respectively.
- the semiconductor device 200 a uses the adhesive member 105 a to stack the second semiconductor chip 205 on the first semiconductor chip 203, and attach the adhesive member 105 a to the recess 111 of the wiring board 201. And the first semiconductor chip 203 are filled. Therefore, when forming the sealing body 220, it can suppress that a void generate
- FIG. Next, a third embodiment will be described with reference to FIGS.
- the third embodiment is configured such that in the first embodiment, the recess 111b extends to the two opposing edges of the wiring board 201 (that is, the recess 111b is configured as a groove). .
- elements that perform the same functions as those in the first embodiment are denoted by the same reference numerals, and different portions from the first embodiment will be mainly described.
- the semiconductor device 200 b according to the third embodiment is configured such that the concave portion 111 b formed in the wiring board 201 extends to the edges of two opposing sides of the wiring board 201.
- the recess 111b constitutes a groove that connects two opposing sides of the wiring board 201.
- the side where the recess 111b extends to the edge for example, the F side becomes the gate side when the sealing resin 211 is injected (see FIG. 6) and seals toward the F ′ side which is the air vent side.
- the resin 211 is filled.
- the wiring mother board 300 is configured such that the adjacent product forming portion 301 (see FIG. 4) and the recess 111b are connected.
- the shape of the recess does not necessarily need to be a shape in which the planar shape is annularly closed as in the first embodiment, and may be a shape like a groove.
- the filling property of the sealing resin 211 to the recessed part 111b of the wiring board 201 can be improved, and generation
- the manufacturing method of the semiconductor device 200b is the same as that of the second embodiment, and thus the description thereof is omitted.
- the semiconductor device 200b includes the wiring substrate 201 having the recess 111b and the plurality of connection pads 223a, 223b, 223c, and 223d on one surface, and the first mounted in the recess 111b.
- the semiconductor chip 203 has a plurality of electrode pads 107 a and 107 b on the surface of at least one end, and a second stacked on the first semiconductor chip 203 so that at least one end protrudes from the first semiconductor chip 203.
- the semiconductor chip 205 includes a plurality of wires 217 that electrically connect the plurality of connection pads 223a and 223c of the wiring substrate 201 and the plurality of electrode pads 107a and 107b of the second semiconductor chip 205, respectively.
- the semiconductor device 200b is configured such that the recess 111b formed in the wiring board 201 extends to two opposing edges of the wiring board 201, and the second semiconductor chip.
- One end of 205 protrudes from the first semiconductor chip 203 toward a side different from the two sides of the wiring board 201 (side where the concave portion 111b extends to the edge).
- the filling property of the sealing resin 211 to the recessed part 111b of the wiring board 201 can be improved, and generation
- the first semiconductor chip 203 is flip-chip mounted on the wiring board 201 in the first embodiment. Note that in the fourth embodiment, elements that perform the same functions as those in the first embodiment are denoted by the same reference numerals, and differences from the first embodiment will be mainly described. As shown in FIGS.
- bump electrodes 104 a and 104 b are formed on the electrode pads 103 a and 103 b of the first semiconductor chip 203.
- 203 is flip-chip mounted in the recess 111 of the wiring board 201.
- the first semiconductor chip 203 is electrically connected to connection pads 226a and 226b formed in the recess 111 via bump electrodes 104a and 104b.
- an underfill material 105c is filled between the first semiconductor chip 203 and the wiring substrate 201, and a gap between the recess 111 and the first semiconductor chip 203 is filled with the underfill material 105c.
- the second semiconductor chip 205 is stacked and mounted on the back surface of the first semiconductor chip 203 via the adhesive member 105 so that the two short sides of the first semiconductor chip 203 overhang. Furthermore, the overhang portion 126 of the first semiconductor chip 203 is configured to be bonded and fixed to the upper surface of the wiring substrate 201 via the bonding member 105. As described above, the first semiconductor chip 203 may be flip-chip mounted on the wiring substrate 201. With such a configuration, electrical characteristics can be improved. Moreover, since the underfill material 105c is filled in the gap between the recess 111 and the first semiconductor chip 203, generation of voids in the gap during resin sealing can be suppressed.
- the semiconductor device 200c includes the wiring substrate 201 having the recess 111 and the plurality of connection pads 223a, 223b, 223c, and 223d on one surface, and the first mounted in the recess 111.
- the semiconductor chip 203 has a plurality of electrode pads 107 a and 107 b on the surface of at least one end, and a second stacked on the first semiconductor chip 203 so that at least one end protrudes from the first semiconductor chip 203.
- the semiconductor chip 205 includes a plurality of wires 217 that electrically connect the plurality of connection pads 223a and 223c of the wiring substrate 201 and the plurality of electrode pads 107a and 107b of the second semiconductor chip 205, respectively.
- One end portion (here, both ends) of 205 extends beyond the inner surface of the recess 111 and is formed on one surface of the wiring board 201. It is lifting. Accordingly, the same effects as those of the first embodiment are obtained.
- the first semiconductor chip 203 is flip-chip mounted on the wiring board 201. Therefore, the electrical characteristics can be improved as compared with the first embodiment.
- the gap between the recess 111 and the first semiconductor chip 203 is filled with the underfill material 105c, generation of voids in the gap during resin sealing can be suppressed.
- formed by this inventor was demonstrated based on the Example, this invention is not limited to the said Example, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary.
- the semiconductor device in which two semiconductor chips having the same pad arrangement are cross-stacked has been described.
- any semiconductor device may be used as long as the semiconductor chips having overhang portions are stacked in multiple stages.
- the present invention may be applied to a combination of chips, for example, a combination of a memory chip and a logic chip, or a chip having any pad arrangement.
- the two opposite sides of the second semiconductor chip 205 are stacked so as to overhang from the first semiconductor chip 203, but the two sides of the second semiconductor chip 205 are stacked so as to overhang.
- the adjacent two sides, three sides, or four sides may be stacked so as to overhang from the first semiconductor chip 203.
- the above-mentioned embodiment demonstrated the case where the base material (insulating base material) of the wiring board 201 was two layers, three or more layers may be sufficient.
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- General Physics & Mathematics (AREA)
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- Wire Bonding (AREA)
Abstract
Description
MCPによる半導体装置は、通常、ワイヤボンディングのために、上段の半導体チップの一部が下段の半導体チップからはみ出す、いわゆるオーバーハング部を持つことを要求される。
このようなオーバーハング部は、半導体チップの薄型化と相俟って、以後のワイヤボンディングや樹脂封止の工程においてチップクラックや反り等の発生の原因となるので、オーバーハング部を補強するための構造が必要である。
このような構造としては、オーバーハング部の直下にボンディングワイヤを配置して支持部とする構造が知られている(特許文献1)。
また、オーバーハング部の直下に設けたバンプを支持部とする構造も用いられている(特許文献2、3)。
さらに、配線基板上に接着剤を配置し、第1半導体チップをフリップチップ実装することで、接着剤を第1半導体チップの外部にはみ出させ、はみ出た接着剤で第2半導体チップのオーバーハング部を支持する構造も知られている(特許文献4)。
例えば、特許文献1~3のように、バンプやボンディングワイヤの支持部材でオーバーハング部を支持する構造では、支持部材で支持される部分と支持されない部分がオーバーハング部に存在するため、上段の半導体チップが薄くなるほど、良好にワイヤボンディングできない恐れがあった。
また、特許文献4のように、チップの外部にはみ出た接着剤で、オーバーハング部を支持する構造では、接着剤のはみ出し量が不足すると、上段のチップと基板との隙間を接着剤で埋めることができない恐れがあった。
そのため、オーバーハング部を確実に支持可能な半導体装置が望まれていた。
本発明の第2の態様は、(a)一面に凹部と複数の接続パッドを有する配線基板の前記凹部内に第1半導体チップを搭載し、(b)少なくとも一端部の表面上に複数の電極パッドを有する第2半導体チップを、少なくとも一端部が前記第1半導体チップから突出するように、前記第1半導体チップ上に積層し、(c)前記配線基板の複数の接続パッドと前記第2半導体チップの前記複数の電極パッドとをそれぞれワイヤで電気的に接続する、を有し、前記(b)は、前記第2半導体チップの前記一端部を、前記凹部の内側面を越えて延在させ、前記配線基板の一面に支持させる、半導体装置の製造方法である。
図2は図1のA−A’断面図である。
図3は図1のB−B’断面図である。
図4は半導体装置200の製造の手順を示す図である。
図5は半導体装置200の製造の手順を示す図であって、ワイヤボンディングの詳細を示す図である。
図6は半導体装置200の製造の手順を示す図であって、樹脂封止の詳細を示す図である。
図7は半導体装置200の製造の手順を示す図である。
図8は第2の実施形態に係る半導体装置200aを示す平面図であって、封止体220は一部のみを図示している。
図9は図8のC−C’断面図である。
図10は図8のD−D’断面図である。
図11は第3の実施形態に係る半導体装置200bを示す平面図であって、封止体220は一部のみを図示している。
図12は図11のE−E’断面図である。
図13は図11のF−F’断面図である。
図14は第4の実施形態に係る半導体装置200cを示す平面図であって、封止体220は一部のみを図示している。
図15は図14のG−G’断面図である。
まず、図1~図3を参照して、本発明の第1の実施形態に係る半導体装置200の概略構造について説明する。
ここでは半導体装置200として、メモリチップを搭載した半導体メモリが例示されている。
図1~図3に示すように、半導体装置200は、一面に凹部111と複数の接続パッド223a、223b、223c、223dを有する配線基板201と、凹部111内に搭載された第1半導体チップ203と、少なくとも一端部の表面上(ここでは両端)に複数の電極パッド107a、107bを有し、少なくとも一端部(ここでは両端)が第1半導体チップ203から突出するように、第1半導体チップ203上に積層された第2半導体チップ205と、配線基板201の複数の接続パッド223a、223cと第2半導体チップ205の複数の電極パッド107a、107bとをそれぞれ電気的に接続する複数のワイヤ217(ボンディングワイヤ)を有し、第2半導体チップ205の一端部(ここでは両端)は、凹部111の内側面を越えて延在し、配線基板201の一面に支持されている。
半導体装置200は、また、配線基板201の接続パッド223b、223dと第1半導体チップ203の電極パッド103a、103b(後述)を接続するワイヤ215を有し、さらに、半導体装置200を外部の装置と接続するための外部端子としての半田ボール216、および配線基板201の一方の面上に配置され、配線基板201の一方の面側を覆うように設けられた封止体220を有している。
次に、図1~図3を参照して、本発明の第1の実施形態に係る半導体装置200を構成する部材の詳細について説明する。
配線基板201は、例えば、略四角形の板状のガラスエポキシやプリプレグ等で構成された絶縁基材219a(上側基板層)および絶縁基材219b(下側基板層)と、上側の絶縁基材である絶縁基材219aの上面と、下側の絶縁基材である絶縁基材219bの下面と、前記絶縁基材219aと絶縁基材219bの間に所定のパターンで形成された配線層123(3層)を有しており、3層の配線層123はビア124により電気的に接続されている。また絶縁基材219aの上面及び絶縁基材219bの下面には、絶縁膜221、例えばソルダーレジスト膜が形成されており、配線層123の一部が絶縁膜221から露出される。絶縁基材219aの上面の配線層123の絶縁膜221の開口から露出した部位が接続パッド223a、223b、223c、223dを形成し、絶縁基材219bの下面の配線層123の絶縁膜221の開口から露出した部位がランド225を形成している。複数の接続パッド223a、223b、223c、223dは、図1に示すように、絶縁基材219aの上面の四角形を構成する4つの辺の周縁部近傍にそれぞれ配列されており、配線層123およびビア124を介して、対応するランド225に電気的に接続されている。また、複数のランド225は、絶縁基材219bの下面に格子状に配置されている。
また絶縁基材219aは、中央領域に、第1半導体チップ203の平面形状に対応した長方形状の開口部131が形成されており、開口部131と絶縁基材219bとで凹部111を構成している。
第1半導体チップ203は、略四角形(長方形)の板状で、一面側に所定の回路及び電極パッド103a、103bが形成されている。複数の電極パッド103a、103bは、それぞれ第1半導体チップ203の長方形の短辺に沿って配列されている。第1半導体チップ203は、裏面側(電極パッド103a、103bが設けられた面と反対側の面側)を配線基板201に向けて、配線基板201の凹部111内に、DAF(Die Attached Film)や絶縁ペースト等の接着部材105を介して搭載されている。
凹部111は、第1半導体チップ203の搭載精度及び封止体220の充填性を考慮し、第1半導体チップ203のチップサイズより100μm程度、大きいサイズで構成されており、凹部111と第1半導体チップ203の間には、それぞれの辺に対して50μm程度の隙間が形成される。
なお、凹部111は、少なくとも第2半導体チップ205のオーバーハング部126に形成された電極パッド107a、107b(詳細は後述)の下方を配線基板201が支持できる程度まで、大きく構成しても良い。
また、第1半導体チップ203の複数の電極パッド103a、103bと、配線基板201の対応する接続パッド223b、223dは、Au、Cu等のワイヤ215により電気的に接続される。
第2半導体チップ205は、第1半導体チップ203と同様に、略四角形(長方形)の板状で、一面側に所定の回路及び電極パッド107a、107bが形成されている。複数の電極パッド107a、107bは、第2半導体チップ205の長方形の短辺に沿って形成されている。
第2半導体チップ205は、裏面側(電極パッド107a、107bが設けられた面と反対側の面側)が第1半導体チップ203に向くように、第1半導体チップ203に積層されている。
より詳細には、第2半導体チップ205は、第1半導体チップ203に対して90度回転された状態でDAFや絶縁ペースト等の接着部材105を介して積層されており、第2半導体チップ205の2つの短辺が第1半導体チップ203からオーバーハングするように配置されている。
第2半導体チップ205の2つの短辺のオーバーハング部126は、接着部材105を介して配線基板201の一面に接着保持される。即ち、第2半導体チップ205のオーバーハング部126は、凹部111の内側面を越えて延在し、配線基板201の一面に支持される。
このように、第2半導体チップ205のオーバーハング部126を配線基板201の一面で支持する構造とすることにより、第2半導体チップ205のチップ厚を薄型化(例えば100μm厚以下)することが可能となる。
また、第2半導体チップ205の複数の電極パッド107a、107bと、配線基板201の対応する接続パッド223a、223cとは、Au、Cu等のワイヤ217により電気的に接続されている。
さらに、配線基板201の一面には、封止体220が形成されており、配線基板201上に搭載された第1半導体チップ203、第2半導体チップ205及びワイヤ215、217が封止体220で覆われる。
また、配線基板201の凹部111と第1半導体チップ203との隙間は、封止体220の充填性を考慮したサイズで構成されているため、この隙間も封止体220で充填される。
また、前述のように、半導体装置200は、第2半導体チップ205のオーバーハング部126を配線基板201の一面で支持する構造とすることにより、第2半導体チップ205のチップ厚を薄型化することが可能であるため、第2半導体チップ205のチップ厚を薄型化することで、封止体220も薄型化できる。
さらに、配線基板201の他面の複数のランド225上には、それぞれ半田ボール216が搭載されている。
以上が半導体装置200を構成する部材の詳細についての説明である。
次に、図4~図7を参照して、半導体装置200の製造方法を説明する。
まず、図4(a)に示す配線母基板300を用意する。
配線母基板300は、マトリクス状に配置された複数の製品形成部301を有しており、個々の製品形成部301が配線基板201に対応している。
次に、図4(b)に示すように、図示しないチップマウンター等を用いて、配線母基板300の製品形成部301上に、第1半導体チップ203を搭載する。
第1半導体チップ203は、電極パッド103a、103bが設けられた短辺が接続パッド223b、223dに対向するように、凹部111内に搭載される。第1半導体チップ203は、他面に設けられたDAF等の接着部材105により配線母基板300に接着固定される。
次に、第1半導体チップ203の電極パッド103a、103bと対応する接続パッド223b、223dとの間を、ワイヤ215により接続する(図3参照)。ワイヤ215を用いた結線には、後述するワイヤボンディング装置を用いることができる。結線は、例えば、超音波熱圧着法を用いたボールボンディングにより行われる。具体的には、溶融によりボールが形成されたワイヤ215の先端を電極パッド103a、103b上に超音波熱圧着し、ワイヤ215が所定のループ形状を描くように、ワイヤ215の後端を対応する接続パッド223b、223d上に超音波熱圧着する。
ここで、配線基板201の凹部111に第1半導体チップ203を搭載したことで、第1半導体チップ203の電極パッド103a、103bと配線基板201の接続パッド223b、223dとを接続するワイヤ215は、凹部111を設けずに第1半導体チップ203を積層した場合と比べて、ワイヤ長を短く接続することができる(図3参照)。ワイヤ長を短くすることで、低コスト化できる。またワイヤ長が短くなることで、後述する樹脂注入時のワイヤショート及びワイヤ流れの発生を抑制できる。
次に、図4(c)に示すように、図示しないチップマウンター等を用いて、第1半導体チップ203上に第2半導体チップ205を搭載する。
第2半導体チップ205は、第1半導体チップ203の電極パッド103a、103b(図2参照)を露出させるように、また、オーバーハング部126が、接続パッド223a、223cに対向するように配線基板201の一面に積層される。
第2半導体チップ205は他面に設けられたDAF等の接着部材105により第1半導体チップ203に固定され、さらにオーバーハング部126が配線基板201の一面に固定される。
次に、図4(d)および図5に示すように、第2半導体チップ205の電極パッド107a、107bと対応する接続パッド223a、223cとの間を、それぞれワイヤ217により接続する。
具体的には、まず、第2半導体チップ205が積層搭載された配線母基板300が、図示しないワイヤボンディング装置のステージに保持される。
次に、キャピラリ41の先端から導出されたワイヤ217の先端を溶融させ、ワイヤ217の先端にボールを形成する。その後、キャピラリ41により、前記ボールの形成されたワイヤの先端を、図5(a)に示すように第2半導体チップ205の電極パッド107a、107b上に超音波熱圧着により圧着する。
ここで、第2半導体チップ205の(第1半導体チップ203からの)オーバーハング部126は、配線基板201の一面に接着固定されるように構成されているため、キャピラリ41からの荷重及び超音波を良好に電極パッド107a、107bに伝えることができる。
その後、ワイヤ217が所定のループを形成するようにキャピラリ41を移動させ、ワイヤ217の他端を図5(b)に示すように配線基板201の対応する接続パッド223a、223cに超音波熱圧着により圧着する。
その後、ワイヤ217の後端をキャピラリ41で引き切ることで、図5(c)に示すように、第2半導体チップ205の電極パッド107a、107bと配線基板201の接続パッドと223a、223cを電気的に接続するワイヤ217が形成される。
なお、前述のように、第2半導体チップ205の(第1半導体チップ203からの)オーバーハング部126は、配線基板201の一面に接着固定されるように構成されているため、第2半導体チップ205のチップ厚を例えば100μm以下に薄型化した場合でも、チップクラックを発生させること無く、ワイヤボンディングすることができる。また前述のようにキャピラリ41からの荷重及び超音波を良好に電極パッド107a、107bに伝達し、良好にワイヤ接続できるため、半導体装置200の信頼性を向上できる。
また、第2半導体チップ205を薄型化することが可能となるため、半導体装置200を薄型化できる。
次に、配線母基板300の一面側に、一括モールドによって封止体220を形成する。
具体的には、まず、配線母基板300をモールド装置400に搬送する。
モールド装置400は、図6(a)に示すように上型401と下型402を有する成形金型を有している。上型401にはキャビティ403が形成されており、下型402には配線母基板300を搭載する凹部404が形成されている。
配線母基板300はモールド装置400の下型402の凹部404にセットされる。
その後、上型401と下型402で配線母基板300を型閉めすることで、図6(b)に示すように、配線母基板300の上方に所定の大きさのキャビティ403やゲート部405が形成される。本実施形態ではMAP(Mold Array Package)方式で構成されているため、キャビティ403は複数の製品形成部301を一括で覆う大きさで構成されている。
次に、下型402のポットにレジンタブレット406(図6(b)参照)が供給され、加熱溶融される。
次に、図6(c)に示すように、溶融された封止樹脂211をプランジャー408によりゲート部405からキャビティ403内に注入し、キャビティ403内に封止樹脂211を充填する。
なお、前述のように、第2半導体チップ205のオーバーハング部126は配線基板201の一面に接着保持されるように構成されているため、封止樹脂211を注入する際の注入圧により、第2半導体チップ205のオーバーハング部126への撓みが発生するのを抑えることができ、第2半導体チップ205にかかる負荷を低減できる。
封止樹脂211がキャビティ403に充填されると、封止樹脂211を所定の温度、例えば180℃でキュアすることで、封止樹脂211が硬化される。
その後、上型401と下型402を分離して、配線母基板300を取り出し、所定の温度、例えば240℃でリフローすることで封止樹脂211が完全に硬化され、図6(d)および図7(a)に示すような、配線母基板300の封止領域を一括的に覆う封止体220が形成される。その後、図6(d)に示すような、封止体220に接続されたゲート部405とランナー部409およびカル部410が除去される。
次に、図7(b)に示すように、配線母基板300の他面側のランド225にそれぞれ半田ボール216を搭載する。
具体的には、例えば配線基板201上のランド225の配置に合わせて複数の吸着孔が形成された図示しない吸着機構を用いて、半田ボール216を吸着孔に保持し、保持された半田ボール216を、フラックスを介して配線基板201のランド225に一括搭載する。
全ての製品形成部301への半田ボール216の搭載後、配線基板201をリフローすることで半田ボール216が固定される。
次に、図7(c)に示すように、封止体220をダイシングテープ251に接着し、封止体220及び配線母基板300をダイシングテープ251に支持させる。その後、図示しないダイシングブレードを用いて、配線母基板300及び封止体220をダイシングライン234(図4(a)参照)に沿って縦横に切断する。これにより、配線母基板300は、製品形成部301毎に個片化される。その後、個片化された製品形成部301及び封止体220をダイシングテープ251からピックアップすることで、図1に示すような半導体装置200が得られる。
このように、第1の実施形態によれば、半導体装置200は、一面に凹部111と複数の接続パッド223a、223b、223c、223dを有する配線基板201と、凹部111内に搭載された第1半導体チップ203と、少なくとも一端部の表面上に複数の電極パッド107a、107bを有し、少なくとも一端部が第1半導体チップ203から突出するように、第1半導体チップ203上に積層された第2半導体チップ205と、配線基板201の複数の接続パッド223a、223cと第2半導体チップ205の複数の電極パッド107a、107bとをそれぞれ電気的に接続する複数のワイヤ217を有し、第2半導体チップ205の一端部(ここでは両端)は、凹部111の内側面を越えて延在し、配線基板201の一面に支持されている。
そのため、オーバーハング部126を配線基板201で確実に支持可能であり、チップクラックを発生させること無く、ワイヤボンディングすることができる。また前述のようにキャピラリ41からの荷重及び超音波を良好に電極パッド107a、107b伝達し、良好にワイヤ接続できるため、半導体装置200の信頼性を向上できる。
また、第2半導体チップ205を薄型化することが可能となるため、半導体装置200を薄型化できる。
次に、第2の実施形態について、図8~図10を参照して説明する。
第2の実施形態は、第1の実施形態において、第2半導体チップ205を、FOW(Film On Wire)等の接着部材105aを用いて、第1半導体チップ203上に積層搭載すると共に、接着部材105aを配線基板201の凹部111と第1半導体チップ203との隙間に充填したものである。
なお、第2の実施形態において、第1の実施形態と同様の機能を果たす要素については同一の番号を付し、主に第1の実施形態と異なる部分について説明する。
図8~図10に示すように、第2の実施形態に係る半導体装置200aは、接着部材105aを用いて、第2半導体チップ205を第1半導体チップ203上に積層搭載すると共に、接着部材105aを配線基板201の凹部111と第1半導体チップ203との隙間に充填している。
このように、配線基板201の凹部111と第1半導体チップ203との隙間には、封止体220とは別の材料を樹脂封止に先立ち、予め充填する構造でもよい。
このような構造とすることにより、封止体220を形成する際に、凹部111と第1半導体チップ203との隙間にボイドが発生するのを抑制することができる。
なお、半導体装置200aの製造方法については、樹脂封止に先立ち、予め凹部111と第1半導体チップ203との隙間を接着部材105aで充填する以外は第1の実施形態と同様であるため、説明を省略する。
このように、第2の実施形態によれば、半導体装置200aは、一面に凹部111と複数の接続パッド223a、223b、223c、223dを有する配線基板201と、凹部111内に搭載された第1半導体チップ203と、少なくとも一端部の表面上に複数の電極パッド107a、107bを有し、少なくとも一端部が第1半導体チップ203から突出するように、第1半導体チップ203上に積層された第2半導体チップ205と、配線基板201の複数の接続パッド223a、223cと第2半導体チップ205の複数の電極パッド107a、107bとをそれぞれ電気的に接続する複数のワイヤ217を有し、第2半導体チップ205の一端部(ここでは両端)は、凹部111の内側面を越えて延在し、配線基板201の一面に支持されている。
従って、第1の実施形態と同様の効果を奏する。
また、第2の実施形態によれば、半導体装置200aは、接着部材105aを用いて、第1半導体チップ203上に第2半導体チップ205を積層すると共に、接着部材105aを配線基板201の凹部111と第1半導体チップ203との隙間に充填している。
そのため、封止体220を形成する際に、凹部111と第1半導体チップ203との隙間にボイドが発生するのを抑制することができる。
次に、第3の実施形態について、図11~図13を参照して説明する。
第3の実施形態は、第1の実施形態において、凹部111bが、配線基板201の対向する2辺のエッジまで延在するように構成した(即ち、凹部111bを溝部として構成した)ものである。
なお、第3の実施形態において、第1の実施形態と同様の機能を果たす要素については同一の番号を付し、主に第1の実施形態と異なる部分について説明する。
図11~図13に示すように、第3の実施形態に係る半導体装置200bは、配線基板201に形成される凹部111bが、配線基板201の対向する2辺のエッジまで延在するように構成され、第2半導体チップ205の一端部が、配線基板201の当該2辺(凹部111bがエッジまで延在している辺)と異なる辺に向かって、第1半導体チップ203から突出している。
換言すれば、凹部111bは、配線基板201の対向する2辺を連結するような溝部を構成している。
この構造においては、凹部111bがエッジに延在している側、例えばF側が封止樹脂211の注入時(図6参照)のゲート側となり、エアベント側となるF’側に向かって、封止樹脂211が充填されるように構成されている。さらに配線母基板300は、隣接する製品形成部301(図4参照)と凹部111bがつながるように構成されている。
このように、凹部の形状は、必ずしも第1の実施形態のように、平面形状が環状に閉じた形状である必要はなく、溝部のような形状でもよい。
このような形状とすることにより、配線基板201の凹部111bへの封止樹脂211の充填性を向上でき、樹脂封止の際のボイドの発生を低減できる。
なお、半導体装置200bの製造方法については、第2の実施形態と同様であるため、説明を省略する。
このように、第3の実施形態によれば、半導体装置200bは、一面に凹部111bと複数の接続パッド223a、223b、223c、223dを有する配線基板201と、凹部111b内に搭載された第1半導体チップ203と、少なくとも一端部の表面上に複数の電極パッド107a、107bを有し、少なくとも一端部が第1半導体チップ203から突出するように、第1半導体チップ203上に積層された第2半導体チップ205と、配線基板201の複数の接続パッド223a、223cと第2半導体チップ205の複数の電極パッド107a、107bとをそれぞれ電気的に接続する複数のワイヤ217を有し、第2半導体チップ205の一端部(ここでは両端)は、凹部111bの内側面を越えて延在し、配線基板201の一面に支持されている。
従って、第1の実施形態と同様の効果を奏する。
また、第3の実施形態によれば、半導体装置200bは、配線基板201に形成される凹部111bが、配線基板201の対向する2辺のエッジまで延在するように構成され、第2半導体チップ205の一端部が、配線基板201の当該2辺(凹部111bがエッジまで延在している辺)と異なる辺に向かって、第1半導体チップ203から突出している。
そのため、第1の実施形態と比較して、配線基板201の凹部111bへの封止樹脂211の充填性を向上でき、樹脂封止の際のボイドの発生を低減できる。
次に、第4の実施形態について、図14および図15を参照して説明する。
第4の実施形態は、第1の実施形態において配線基板201に第1半導体チップ203をフリップチップ実装したものである。
なお、第4の実施形態において、第1の実施形態と同様の機能を果たす要素については同一の番号を付し、主に第1の実施形態と異なる部分について説明する。
図14および図15に示すように、第4の実施形態に係る半導体装置200cは、第1半導体チップ203の電極パッド103a、103b上にバンプ電極104a、104bが形成されており、第1半導体チップ203は配線基板201の凹部111内にフリップチップ実装されている。
また、第1半導体チップ203は凹部111内に形成された接続パッド226a、226bにバンプ電極104a、104bを介して、電気的に接続されている。
さらに、第1半導体チップ203と配線基板201の間には、アンダーフィル材105cが充填されており、凹部111と第1半導体チップ203の隙間はアンダーフィル材105cで充填される。
なお、第2半導体チップ205は、第1半導体チップ203から2つの短辺側がオーバーハングするように、第1半導体チップ203の裏面上に接着部材105を介して積層搭載されている。さらに、第1半導体チップ203のオーバーハング部126は、配線基板201の上面に接着部材105を介して接着固定されるように構成されている。
このように、第1半導体チップ203を配線基板201にフリップチップ実装する構成としてもよく、このような構成とすることにより、電気特性を向上できる。また、凹部111と第1半導体チップ203との隙間にアンダーフィル材105cが充填されるため、樹脂封止時の隙間へのボイドの発生を抑制できる。
なお、半導体装置200cの製造方法については、第1の実施形態と同様であるため、説明を省略する。
このように、第4の実施形態によれば、半導体装置200cは、一面に凹部111と複数の接続パッド223a、223b、223c、223dを有する配線基板201と、凹部111内に搭載された第1半導体チップ203と、少なくとも一端部の表面上に複数の電極パッド107a、107bを有し、少なくとも一端部が第1半導体チップ203から突出するように、第1半導体チップ203上に積層された第2半導体チップ205と、配線基板201の複数の接続パッド223a、223cと第2半導体チップ205の複数の電極パッド107a、107bとをそれぞれ電気的に接続する複数のワイヤ217を有し、第2半導体チップ205の一端部(ここでは両端)は、凹部111の内側面を越えて延在し、配線基板201の一面に支持されている。
従って、第1の実施形態と同様の効果を奏する。
また、第4の実施形態によれば、半導体装置200cは、第1半導体チップ203を配線基板201にフリップチップ実装している。
そのため、第1の実施形態と比較して、電気特性を向上できる。また、凹部111と第1半導体チップ203との隙間はアンダーフィル材105cが充填されるため、樹脂封止時の隙間へのボイドの発生を抑制できる。
例えば、上記した実施形態では、同じパッド配置の2つの半導体チップをクロス積層する半導体装置について説明したが、オーバーハング部を有する半導体チップが多段に積層された半導体装置であれば、どのような半導体チップの組合せ、例えばメモリチップとロジックチップの組合せ等、或いはどのようなパッド配置のチップに適用しても良い。
また、上記した実施形態では、第2半導体チップ205の対向する2辺が、第1半導体チップ203からオーバーハングするように積層したが、第2半導体チップ205の1辺がオーバーハングするように積層してもよく、あるいは、隣接する2辺、3辺或いは4辺が第1半導体チップ203からオーバーハングするように積層してもよい。
さらに、上記した実施形態では、配線基板201の基材(絶縁基材)が2層である場合について説明したが、3層以上であっても良い。
本出願は、2012年9月14日に出願された、日本国特許出願第2012−202776号からの優先権を基礎として、その利益を主張するものであり、その開示はここに全体として参考文献として取り込む。
103a、103b :電極パッド
104a、104b :バンプ電極
105、105a :接着部材
105c :アンダーフィル材
107a、107b :電極パッド
111、111b :凹部
123 :配線層
124 :ビア
126 :オーバーハング部
131 :開口部
200、200a、200b、200c :半導体装置
201 :配線基板
203 :第1半導体チップ
205 :第2半導体チップ
211 :封止樹脂
215、217 :ワイヤ
216 :半田ボール
219a、219b :絶縁基材
220 :封止体
221 :絶縁膜
223a、223b、223c、223d、226a、226b :接続パッド
225 :ランド
234 :ダイシングライン
251 :ダイシングテープ
300 :配線母基板
301 :製品形成部
400 :モールド装置
401 :上型
402 :下型
403 :キャビティ
404 :凹部
405 :ゲート部
406 :レジンタブレット
408 :プランジャー
409 :ランナー部
410 :カル部
Claims (10)
- 一面に凹部と複数の接続パッドを有する配線基板と、
前記凹部内に搭載された第1半導体チップと、
少なくとも一端部の表面上に複数の電極パッドを有し、少なくとも一端部が前記第1半導体チップから突出するように、前記第1半導体チップ上に積層された第2半導体チップと、
前記配線基板の複数の接続パッドと前記第2半導体チップの前記複数の電極パッドとをそれぞれ電気的に接続する複数のワイヤと、
を有し、
前記第2半導体チップの前記一端部は、前記凹部の内側面を越えて延在し、前記配線基板の一面に支持される、半導体装置。 - 前記配線基板は、
下側基板層と、
前記下側基板層に積層された上側基板層と、
を有し、
前記上側基板層は、前記第1半導体チップの平面形状に対応した開口部または溝部を有し、
前記開口部または前記溝部と前記下側基板層とで前記凹部を構成している、請求項1に記載の半導体装置。 - 前記凹部には、接着部剤が充填されている、請求項1または2に記載の半導体装置。
- 前記第1半導体チップおよび前記第2半導体チップを覆うように前記配線基板に形成された樹脂製の封止体を有する、請求項1~3のいずれか一項に記載の半導体装置。
- 前記凹部は、前記配線基板の対向する二辺のエッジまで延在し、
前記第2半導体チップの前記一端部が、前記配線基板の前記二辺と異なる辺に向かって、前記第1半導体チップから突出するように構成される、請求項1~4のいずれか一項に記載の半導体装置。 - 前記第1半導体チップは、前記配線基板にフリップチップ接続されている、請求項1~5のいずれか一項に記載の半導体装置。
- (a)一面に凹部と複数の接続パッドを有する配線基板の前記凹部内に第1半導体チップを搭載し、
(b)少なくとも一端部の表面上に複数の電極パッドを有する第2半導体チップを、少なくとも一端部が前記第1半導体チップから突出するように、前記第1半導体チップ上に積層し、
(c)前記配線基板の複数の接続パッドと前記第2半導体チップの前記複数の電極パッドとをそれぞれワイヤで電気的に接続する、
を有し、
前記(b)は、前記第2半導体チップの前記一端部を、前記凹部の内側面を越えて延在させ、前記配線基板の一面に支持させる、半導体装置の製造方法。 - 前記(a)は、
下側基板層に、前記第1半導体チップの平面形状に対応した開口部または溝部を有する上側基板層を積層して前記配線基板を構成し、
前記開口部または前記溝部と前記下側基板層とで構成された前記凹部に前記第1半導体チップを搭載する、請求項7に記載の半導体装置の製造方法。 - (d)前記第1半導体チップおよび前記第2半導体チップを覆うように前記配線基板に封止体を形成する、
を有する、請求項7または8に記載の半導体装置の製造方法。 - 前記凹部は、前記配線基板の対向する二辺のエッジまで延在し、
前記(b)は、前記第2半導体チップの前記一端部が、前記配線基板の前記二辺と異なる辺に向かって、前記第1半導体チップから突出するように前記配線基板の一面に支持させる、請求項7~9のいずれか一項に記載の半導体装置の製造方法。
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WO2019171467A1 (ja) * | 2018-03-06 | 2019-09-12 | 日立化成株式会社 | 半導体装置及びその製造方法 |
CN111819671A (zh) * | 2018-03-06 | 2020-10-23 | 日立化成株式会社 | 半导体装置及其制造方法 |
KR20200128027A (ko) * | 2018-03-06 | 2020-11-11 | 쇼와덴코머티리얼즈가부시끼가이샤 | 반도체 장치 및 그 제조 방법 |
JPWO2019171467A1 (ja) * | 2018-03-06 | 2021-02-12 | 昭和電工マテリアルズ株式会社 | 半導体装置及びその製造方法 |
JP7127680B2 (ja) | 2018-03-06 | 2022-08-30 | 昭和電工マテリアルズ株式会社 | 半導体装置及びその製造方法 |
KR102466149B1 (ko) | 2018-03-06 | 2022-11-11 | 쇼와덴코머티리얼즈가부시끼가이샤 | 반도체 장치 및 그 제조 방법 |
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US11049845B2 (en) | 2021-06-29 |
DE112013004495T5 (de) | 2015-06-11 |
US20150235994A1 (en) | 2015-08-20 |
KR20150056562A (ko) | 2015-05-26 |
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