WO2014119477A1 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
WO2014119477A1
WO2014119477A1 PCT/JP2014/051463 JP2014051463W WO2014119477A1 WO 2014119477 A1 WO2014119477 A1 WO 2014119477A1 JP 2014051463 W JP2014051463 W JP 2014051463W WO 2014119477 A1 WO2014119477 A1 WO 2014119477A1
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semiconductor chip
semiconductor device
wire
substrate
convex member
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PCT/JP2014/051463
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English (en)
French (fr)
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任志 友廣
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ピーエスフォー ルクスコ エスエイアールエル
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Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • a semiconductor device of a type in which a semiconductor chip is mounted on a wiring substrate or a type in which a plurality of semiconductor chips are stacked is known.
  • a semiconductor chip is mounted on each of the product forming portions, a sealing resin that integrally covers a plurality of product forming portions on the wiring substrate is formed, and the wiring substrate is individually connected to each product.
  • a MAP (Mold Array Process) method for dividing each forming unit is used.
  • Patent Document 1 in order to suppress wire short-circuit and wire flow due to entrainment on the air vent side when injecting sealing resin in the MAP method, a connection pad of a wiring board and a semiconductor chip mounted on the wiring board are described. A technique is disclosed in which the wire length of the wire arranged on the air vent side is shorter than the wire arranged on the gate side of the wire connecting the electrode.
  • the wire length of the wire arranged on the air vent side is made shorter than the wire arranged on the gate side, thereby suppressing wire short-circuit and wire flow due to entrainment on the air vent side when injecting sealing resin.
  • the pressure applied to the wires at both ends on the air vent side due to the entrapment of the sealing resin on the air vent side when the sealing resin is injected does not change.
  • An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device capable of suppressing wire shorts and wire flow.
  • a substrate a semiconductor chip which is mounted on one surface of the substrate and has a plurality of electrodes arranged along one side, and the one side of the semiconductor chip, A plurality of connection pads formed on one surface of the substrate, a plurality of bonding wires respectively connecting the plurality of electrodes and the plurality of connection pads, and a bonding wire located at an outermost position among the plurality of bonding wires.
  • a convex member disposed so as to protrude from one surface of the substrate at a position near the outside, and formed on one surface of the substrate so as to cover the semiconductor chip, the bonding wire, and the convex member. And a sealing resin portion.
  • a semiconductor chip having a plurality of electrodes arranged along one side is mounted on a substrate, and a plurality of layers formed on one surface of the substrate along one side of the semiconductor chip.
  • the connection pad and the plurality of electrodes are respectively connected by a plurality of bonding wires, and a convex member protrudes from one surface of the substrate at a position near the outer side of the bonding wire located on the outermost side among the plurality of bonding wires.
  • a sealing resin portion is formed on one surface of the substrate so as to cover the semiconductor chip, the bonding wire, and the convex member.
  • the present invention it is possible to disperse the pressure applied to the wire during the sealing process, and it is possible to reduce the occurrence of wire shorts and wire flow.
  • FIG. 2 is a cross-sectional view of the semiconductor device corresponding to the cross section along line A-A ′ of FIG.
  • FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1 (a), and (a) to (f) are cross-sectional views sequentially showing the flow of the manufacturing process.
  • the top view of the wiring motherboard before sealing with sealing resin is shown.
  • the top view of the wiring mother board after sealing with sealing resin is shown. It is a figure which shows the moving direction of sealing resin formed on a wiring mother board
  • FIG. 6 is a cross-sectional view of the semiconductor device corresponding to the cross section along line B-B ′ of FIG. It is the top view which showed schematic structure of the semiconductor device by the 3rd Example of this invention except a part of sealing resin.
  • FIG. 7 is a cross-sectional view of the semiconductor device corresponding to the cross section taken along line C-C ′ of FIG. It is the top view which showed schematic structure of the semiconductor device by the 4th Example of this invention except a part of sealing resin.
  • FIG. 9 is a cross-sectional view of a semiconductor device corresponding to a cross section taken along line D-D ′ of FIG.
  • FIG. 10 is a plan view illustrating a modification of the semiconductor device illustrated in FIG.
  • a semiconductor device 1 includes a substrate 2, a semiconductor chip 20 that is mounted on one surface of the substrate 2 and has a plurality of electrodes 22 arranged along one side, and along one side of the semiconductor chip 20.
  • the plurality of connection pads 14 formed on one surface of the substrate 2, the plurality of bonding wires 31 respectively connecting the plurality of electrodes 22 and the plurality of connection pads 14, and the outermost position among the plurality of wires 31.
  • the substrate 2 so as to cover the convex member 30 disposed so as to protrude from one surface of the substrate 2 and the semiconductor chip 20, the bonding wire 31, and the convex member 30. And a sealing resin portion 40 formed on one surface.
  • one side of the semiconductor chip 20 is arranged on the air vent side. Furthermore, the convex member 30 is arranged on a straight line substantially parallel to the extending direction of one side from an intermediate position between one side of the semiconductor chip 20 and the connection pad 14. Further, the convex member 30 is formed to be higher than the loop of the bonding wire 31.
  • the convex member 30 so as to protrude from one surface of the substrate 2 at a position near the outside of the bonding wire 31 located at the outermost position among the plurality of bonding wires 31, sealing is achieved.
  • the pressure applied to the outermost bonding wire 31 when the resin 40 is filled can be dispersed, and the occurrence of wire shorts and wire flow of the outermost bonding wire 31 can be reduced. Further, the reliability of the semiconductor device 1 can be improved by reducing wire shorts and wire flow.
  • the convex member 30 is arranged on a straight line substantially parallel to the extending direction of one side from an intermediate position between one side of the semiconductor chip 20 and the connection pad 14, so that the edge of the semiconductor chip 20 on the air vent side is provided.
  • the pressure by the sealing resin 40 due to the entrainment generated along can be dispersed well.
  • the convex member 30 Furthermore, by forming the convex member 30 so as to be higher than the loop height of the wire 31, the sealing resin 40 flowing by the side of the semiconductor chip 20 that flows faster than on the semiconductor chip 20 when the sealing resin 40 is filled.
  • the convex member 30 can be satisfactorily applied to the entrainment.
  • FIG. 1 is a plan view (FIG. 1 (a)) and a cross-sectional view taken along line AA ′ (FIG. 1 (b)) showing a schematic configuration of a semiconductor device 1 according to a first embodiment of the present invention.
  • a semiconductor device 1 projects from a substantially rectangular plate-like wiring board 2, a semiconductor chip 20 mounted on one surface of the wiring substrate 2 via an adhesive member 21, and one surface on the wiring substrate 2.
  • a bonding wire 31 (hereinafter also simply referred to as a wire) for electrically connecting the connection pad 14 and the power supply pad 22, and these members on the wiring board 2. It has a sealing resin 40 for sealing, and solder balls 50 for connecting to other devices as external terminals.
  • the wiring substrate 2 is, for example, a glass epoxy substrate, and includes an insulating base material 11, a wiring layer (not shown) patterned on both surfaces thereof, and insulating films 10 and 12 formed so as to cover the wiring layer, have.
  • a plurality of connection pads 14 are connected to the wiring layer on one side of the wiring substrate 2 along the short sides of the semiconductor chip 20.
  • a plurality of lands 15 are connected to the other surface side of the wiring board 2. As shown in FIG. 1, the plurality of connection pads 14 are arranged in the vicinity of the peripheral edge of one surface of the wiring board 2.
  • the plurality of lands 15 are arranged in a lattice pattern on the other surface of the wiring board 2.
  • the plurality of connection pads 14 and the plurality of lands 15 are connected to each other by a wiring continuous therewith and vias that penetrate the insulating base material 11. Wires 31 are connected to the connection pads 14, and solder balls 50 are mounted on the lands 15.
  • the insulating films 10 and 12 are, for example, solder resist.
  • the insulating films 10 and 12 are formed on both front surfaces of the insulating substrate 11 except for a predetermined region. In other words, the insulating films 10 and 12 are partially removed with respect to a predetermined region, and have one or more openings 13.
  • the opening 13 is formed on one surface side of the wiring board 2.
  • the opening 13 exposes a region where the plurality of connection pads 14 are formed and a peripheral region thereof. Also on the other surface side of the wiring board 2, the openings 13 for exposing the plurality of lands 15 are formed.
  • the semiconductor chip 20 is, for example, a DRAM memory chip, and has a substantially rectangular plate shape.
  • An electrode pad 22 is formed on one surface along a predetermined circuit and a short side.
  • the plurality of electrode pads 22 are arranged along one side of the semiconductor chip 20.
  • the semiconductor chip 20 is arranged so that the number of electrode pads 22 on one end side is larger than the number of electrode pads 22 on the other end side, and one end side with a larger number of electrode pads 22 is the gate side (A side).
  • the other end side with a small number of electrode pads 22 is arranged on the air vent side (A ′ side).
  • the semiconductor chip 20 is mounted at a position near the center on the one surface side of the wiring board 2. Specifically, the semiconductor chip 20 is disposed adjacent to the opening 13 so that one side thereof coincides with one side of the opening 13. The other surface of the semiconductor chip 20 is bonded and fixed to a region where the insulating film 10 of the wiring substrate 2 is formed by an adhesive member 21 such as a diattach film (DAF).
  • DAF diattach film
  • circuit configuration and function of the semiconductor chip 20 are irrelevant to the present invention, and the number and arrangement of the electrode pads 22 are not limited to the above example.
  • a plurality of wires 31 are arranged in the vicinity of the outer side of the outermost wire 31 so as to protrude from one surface of the wiring board 2.
  • a convex bump 30, for example, a wire bump 30 made of Au or the like is disposed.
  • the wire bumps 30 are arranged on a straight line substantially parallel to the extending direction of one side from an intermediate position between one side of the semiconductor chip 20 and the connection pad 14.
  • the convex member 30 has a plurality of wire bumps 30 stacked so as to have substantially the same height as the loop of the wire 31. Note that the height can be easily adjusted simply by changing the number of the stacked wire bumps 30.
  • the convex member 30 is preferably arranged so as to be higher than the loop height of the wire 31.
  • the convex member 30 is formed on the connection pad 14 disposed on the wiring board 2.
  • the wire 31 is made of a conductive metal such as Au.
  • the wire 31 electrically connects the plurality of electrode pads 22 and the corresponding connection pads 14.
  • the sealing resin 40 is an insulating resin and seals the semiconductor chip 20, the power supply pad 22, the convex member 30, the wire 31, and the like so as to cover one surface side of the wiring board 2.
  • 2 (a) to 2 (f) are cross-sectional views showing an assembly flow of the semiconductor device 1 of the first embodiment.
  • 3A and 3B are plan views showing schematic configurations of the wiring mother board 100 before sealing and the wiring mother board 100 after sealing.
  • 4A and 4B are plan views showing the relationship between the enveloping of the sealing resin 40 on the air vent side and the convex member 30 in the sealing step.
  • the wiring mother board 100 has a plurality of product forming portions 200 arranged in a matrix in a region surrounded by the frame portion 60 in which positioning holes are formed.
  • a plurality of connection pads 14 and openings 13 are formed, and the plurality of connection pads 14 and the plurality of power supply pads 22 of the semiconductor chip 20 are connected by wires 31.
  • FIG. 3B batch molding for forming the sealing resin 40 on the one surface side of the wiring mother board 100 shown in FIG. This sealing step will be described in more detail later.
  • These product forming portions 200 are individually cut along the dicing line 16 later to form the semiconductor device 300.
  • insulating films 10 and 12 are formed on both surfaces of the wiring mother board 100.
  • the insulating films 10 and 12 have openings 13 that expose the connection pads 14 and the lands 15.
  • the insulating films 10 and 12 are formed, for example, by applying an insulating film material over the entire surface and curing it by drying and exposure. The portion that becomes the opening 13 is not exposed and is removed by subsequent development. In addition, it is desirable not to arrange a wiring pattern in the opening 13. When a wiring pattern is arranged in the opening 13, it is desirable to form Ni and Au plating on the surface thereof as in the case of the connection pad 14. By applying these platings, the reliability of the wiring can be ensured even when the insulating films 10 and 12 are not covered.
  • the semiconductor chips 20 are sequentially mounted on the wiring mother board 100.
  • the semiconductor chip 20 is mounted adjacent to the opening 13 so that one side thereof overlaps one side of the opening 13.
  • the semiconductor chip 20 is bonded and fixed to the wiring mother board 100 by an adhesive member 21 such as DAF provided on the other surface.
  • an adhesive member 21 such as DAF provided on the other surface.
  • a plurality of power supply pads 22 are arranged on the semiconductor chip 20 on the semiconductor chip 20 on the semiconductor chip 20, a plurality of power supply pads 22 are arranged.
  • the electrode pads 22 of the semiconductor chip 20 and the corresponding connection pads 14 are connected by wires 31 respectively.
  • the wire 31 is made of, for example, Au, and a wire bonding apparatus (not shown) can be used for connection using the wire 31.
  • the connection is performed by, for example, ball bonding using an ultrasonic thermocompression bonding method. Specifically, the tip of the wire 31 on which a ball is formed by melting is ultrasonically thermocompression bonded onto the electrode pad 22, and the rear end of the wire 31 is connected to the corresponding connection pad so that the wire 31 draws a predetermined loop shape. 14 is subjected to ultrasonic thermocompression bonding.
  • the formation of the wire bump 30 is also performed by a wire bonding apparatus. As in the case of connecting with the wire 31, the wire 31 that has been melted and formed with a ball at the tip is connected by ultrasonic thermocompression bonding on the connection pad 14 of the wiring mother board 100, and then the rear end is pulled off. Is formed.
  • the multi-stage wire bumps 30 are formed by further laminating the wire bumps 30 in the same manner on the wire bumps 30 formed on the connection pads 14 of the wiring mother board 100.
  • the convex member 30 is formed after mounting the semiconductor chip 20 on the wiring motherboard 100 has been described.
  • the convex member 30 is formed in any step before the sealing step.
  • the convex member 30 may be formed before the semiconductor chip 20 is mounted.
  • a sealing resin 40 is formed on one side of the wiring mother board 100 by batch molding.
  • the batch molding will be described later with reference to FIGS.
  • solder balls 50 are mounted on the lands 15 on the other surface side of the wiring mother board 100, respectively. These solder balls 50 are used as external terminals of the semiconductor device 300.
  • the mounting of the solder balls 50 can be performed, for example, by using a suction mechanism (not shown) provided with a plurality of suction holes arranged corresponding to the plurality of lands 15.
  • a suction mechanism (not shown) provided with a plurality of suction holes arranged corresponding to the plurality of lands 15.
  • a plurality of solder balls 50 are sucked and held by the suction mechanism, a flux is transferred and formed on the held solder balls 50, and the solder balls 50 are collectively mounted on the lands 15 of the wiring motherboard 100. Thereafter, the solder ball 50 and the land 15 are connected and fixed by a reflow process.
  • the sealing resin 40 is bonded to a dicing tape (not shown), and the sealing resin 40 and the wiring mother board 100 are supported on the dicing tape. Then, using a dicing blade (not shown), the wiring mother board 100 and the sealing resin 40 are cut vertically and horizontally along the dicing line 16. Thereby, the wiring mother board 100 is separated into pieces for each product forming unit 200. Thereafter, the separated product forming part 200 and the sealing resin 40 are picked up from the dicing tape, whereby the semiconductor device 1 as shown in FIG. 1 is obtained.
  • the collective mold for forming the sealing resin 15 will be described.
  • a transfer mold apparatus (not shown) is used for the collective molding.
  • the wiring mother board 100 in which the processes up to the connection by the wire 31 and the formation of the wire pump are completed is placed in the cavity formed by the upper mold and the lower mold of the transfer mold apparatus.
  • a raw material tablet such as a thermosetting epoxy resin is set on the plunger, and the upper mold and the lower mold are clamped.
  • the raw material tablet is pressurized and melted by the plunger, and the sealing resin 40 (molten resin) is pressed into the cavity from the cull part 72 through the runner part 71 and the gate part 70.
  • the molten resin flows from the gate portion 70 toward the air vent.
  • the sealing resin 40 (molten resin) travels substantially straight in the cavity from the gate side toward the air vent side. And as shown in FIG.4 (b), the sealing resin 40 flows toward the area
  • the wire bumps 30 arranged near the outer side of the outermost wire 31 and projecting from one surface of the wiring board 2 are caused by the entrapment of the sealing resin 40.
  • the pressure applied to the outermost wire 31 is dispersed.
  • the convex member 30 can disperse the pressure applied to the outermost wire 31 by the entrapment of the sealing resin 40. Therefore, it is possible to reduce the occurrence of wire shorts and wire flows of the outermost wire 31. Moreover, the reliability of the semiconductor device 1 can be improved as a result of reducing wire shorts and wire flow.
  • the convex member 30 is arranged on a straight line substantially parallel to the extending direction of one side from an intermediate position between one side of the semiconductor chip 20 and the connection pad 14, so that the edge of the semiconductor chip 20 on the air vent side is provided.
  • the pressure by the sealing resin 40 due to the entrainment generated along can be dispersed well.
  • the convex member 30 Furthermore, by forming the convex member 30 so as to be higher than the loop height of the wire 31, the sealing resin 40 flowing by the side of the semiconductor chip 20 that flows faster than on the semiconductor chip 20 when the sealing resin 40 is filled.
  • the convex member 30 can be satisfactorily applied to the entrainment.
  • (Second embodiment) 5A and 5B are a cross-sectional view and a plan view showing a schematic configuration of the semiconductor device 1 according to the second embodiment of the present invention.
  • the same reference numerals are assigned to the same members as those of the semiconductor device 1 according to the first embodiment, and the description thereof is omitted.
  • the semiconductor device 1 according to the second embodiment is configured in the same manner as the first embodiment, and is different from the first embodiment in that the convex member 30 is formed using a bonding wire.
  • a plurality of bonding wires serving as the convex member 30 are formed, for example, to intersect.
  • the bonding wire by disposing the bonding wire on the outside of the air vent-side wire 31, the stress applied to the wires 31 at both ends due to the entrainment on the air vent side when the sealing resin 40 is filled is distributed as in the first embodiment. Therefore, the occurrence of wire shorts and wire flow can be reduced. Further, since the convex member 30 is formed of a bonding wire, the step of forming the wire 31 that connects the electrode pad 22 of the semiconductor chip 20 and the connection pad 14 of the wiring substrate 2 without adding a process is performed. The shaped member 30 can be formed.
  • FIGS. 6A and 6B are a cross-sectional view and a plan view showing a schematic configuration of a semiconductor device 1 according to the third embodiment of the present invention.
  • the same members as those of the semiconductor device 1 according to the first embodiment and the second embodiment are denoted by the same reference numerals, and the description thereof is omitted.
  • the semiconductor device 1 of the third embodiment is configured in the same manner as the first embodiment, and differs from the first and second embodiments in that a small component, for example, a passive component 30 is mounted as the convex member 30.
  • the convex member 30 can be disposed only by changing the arrangement of small components incorporated in the semiconductor device 1.
  • FIG. 7 is a plan view showing a schematic configuration of the semiconductor device 1 according to the fourth embodiment of the present invention.
  • the same members as those of the semiconductor device 1 according to the first embodiment, the second embodiment, and the third embodiment are denoted by the same reference numerals, and the description thereof is omitted.
  • the semiconductor device 1 according to the fourth embodiment uses the semiconductor chip 20 in which a plurality of electrode pads 22 are formed along four sides, and the outside of the wire 31 disposed at both ends of the wire 31 on each side. The difference is that the wire bumps 30 to be the convex members 30 are arranged.
  • the same effects as in the first embodiment can be obtained, and the convex members 30 are arranged corresponding to the wires 31 formed on the respective sides of the semiconductor chip 20, so that they are mounted on the wiring board 2. It is not necessary to consider the orientation of the semiconductor chip 20 to be performed.
  • (Fifth embodiment) 8A and 8B are a sectional view and a plan view showing a schematic configuration of a semiconductor device 1 according to the fifth embodiment of the present invention.
  • the same members as those of the semiconductor device 1 according to the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment are denoted by the same reference numerals, and the description thereof is omitted. .
  • the semiconductor device 1 of the fifth embodiment shows a case where it is applied to MCP (Multi-Chip Package), and is laminated on the semiconductor chip 20 of the first embodiment so that the semiconductor chip 20 ′ having the same configuration rotates 90 degrees. It differs in that it is arranged.
  • MCP Multi-Chip Package
  • the convex members 30 corresponding to the wires 31 on the air vent side by arranging the convex members 30 corresponding to the wires 31 on the air vent side, the same effects as in the first embodiment can be obtained, and a plurality of semiconductor chips 20 and 20 ′ are mounted.
  • the capacity or function of the semiconductor device 1 can be increased.
  • the overhang portion of the upper semiconductor chip 20 ′ is arranged in a direction perpendicular to the filling direction of the sealing resin 40, so that the gap between the overhang portion of the upper semiconductor chip 20 ′ and the wiring board 2 is reduced. Fillability can be improved and the occurrence of voids under the overhang can be reduced.
  • FIG. 9 is a plan view showing a modification of the semiconductor device 1 according to each embodiment of the present invention.
  • the convex member 30 is arranged on the upper semiconductor chip arranged on the air vent side. From a middle position between one side of the chip 20 ′ and the connection pad 14 of the wiring board 2 corresponding to the electrode pad 22 on the air vent side of the upper semiconductor chip 20 ′, on a straight line substantially parallel to the extending direction of one side Placed in.
  • the convex member 30 corresponding to the upper semiconductor chip 20 ′ is arranged and the pressure due to the entanglement on the air vent side is dispersed, the pressure applied to the air vent side wire 31 of the lower semiconductor chip 20 is dispersed.
  • the convex member 30 for the lower semiconductor chip 20 may not be provided.
  • FIG 9 illustrates the configuration in which the upper semiconductor chip 20 ′ having a size smaller than the lower semiconductor chip 20 is stacked on the lower semiconductor chip 20, the wire 31 of the upper semiconductor chip 20 ′ is connected to the air vent side.
  • the semiconductor chip 20 ′ having the same size may be applied to an MCP that is stacked so as to overlap with each other via a spacer or FOW (Film On Wire).
  • one convex member 30 is provided in the vicinity of the outside of the wire 31 located at both ends of the plurality of wires 31 arranged on the air vent side. You may comprise so that the some convex member 30 may be arrange
  • positioned along two opposing sides the semiconductor device 1 incorporating the semiconductor chip 20 in which the electrode pad 22 was arrange
  • the present invention is applied to the MCP type semiconductor device 1 laminated so as to cross the chips 20 and 20 ′ has been described, any semiconductor device may be used as long as the wire 31 is arranged on the air vent side. It may be applied.

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Abstract

　封止工程の際にワイヤに加わる圧力を分散することが可能となる技術を提供する。本発明の半導体装置では、複数の電極と複数の接続パッドとをそれぞれ接続する複数のボンディングワイヤのうち、最外に位置するボンディングワイヤの外側の近傍位置に基板の一面から突出するように凸状部材を配置した構成を備える。

Description

半導体装置及び半導体装置の製造方法
　本発明は、半導体装置及び半導体装置の製造方法に関する。
　半導体装置として、配線基板上に半導体チップを搭載したタイプや、複数の半導体チップを積層したタイプの半導体装置が知られている。この種の半導体装置では、一般的に、製品形成部のそれぞれに半導体チップを搭載し、配線基板上の複数の製品形成部を一体的に覆う封止樹脂を形成し、配線基板を個々の製品形成部毎に分割するＭＡＰ（Mold Array Process）方式が用いられている。
　特許文献１には、ＭＡＰ方式における封止樹脂を注入する際のエアベント側での巻き込みによるワイヤショートやワイヤ流れを抑制するために、配線基板の接続パッドと前記配線基板に搭載される半導体チップの電極とを接続するワイヤを、ゲート側に配置されるワイヤよりもエアベント側に配置されるワイヤのワイヤ長を短くする技術が開示されている。
特開２０１１－２２８６０３号公報
　上記関連技術により、ゲート側に配置されるワイヤよりもエアベント側に配置されるワイヤのワイヤ長を短くすることで、封止樹脂を注入する際のエアベント側の巻き込みによるワイヤショートやワイヤ流れを抑制はできるが、封止樹脂を注入する際のエアベント側での封止樹脂の巻き込みによるエアベント側の両端のワイヤに加わる圧力は変わらない。
　また、半導体チップの表面の電極と配線基板の接続パッドとを、半導体チップのエッジに接触しないようなループ形状で接続するため、ワイヤ長と短くするのには限界もあり、エアベント側のワイヤでのワイヤショートやワイヤ流れの発生する恐れがある。
　本発明は、ワイヤショートやワイヤ流れを抑制可能な半導体装置及び半導体装置の製造方法を提供することを目的とする。
　上述の課題に鑑み、本発明の一態様は、基板と、上記基板の一面に搭載され、一辺に沿って配置された複数の電極を有する半導体チップと、上記半導体チップの一辺に沿って、上記基板の一面に形成された複数の接続パッドと、上記複数の電極と上記複数の接続パッドとをそれぞれ接続する複数のボンディングワイヤと、上記複数のボンディングワイヤのうち、最外に位置するボンディングワイヤの外側の近傍位置であって、上記基板の一面から突出するように配置された凸状部材と、上記半導体チップ、上記ボンディングワイヤ、上記凸状部材を覆うように、上記基板の一面に形成された封止樹脂部と、を備えることを特徴とする半導体装置に関する。
　また、本発明の別の態様は、一辺に沿って配置された複数の電極を有する半導体チップを基板上に搭載し、上記半導体チップの一辺に沿って、上記基板の一面に形成された複数の接続パッドと上記複数の電極とを複数のボンディングワイヤでそれぞれ接続し、上記複数のボンディングワイヤのうち、最外に位置するボンディングワイヤの外側の近傍位置に凸状部材を上記基板の一面から突出するように配置し、上記半導体チップ、上記ボンディングワイヤ、上記凸状部材を覆うように、封止樹脂部を上記基板の一面に形成することを特徴とする半導体装置の製造方法に関する。
　本発明によると、封止工程の際にワイヤに加わる圧力を分散することが可能となり、ワイヤショートやワイヤ流れの発生を低減することができる。
　本発明の更なる利点及び実施形態を、記述と図面を用いて下記に詳細に説明する。
本発明の第１の実施例による半導体装置の概略構成を、封止樹脂の一部を除いて示した平面図である。 図１（ａ）のＡ－Ａ’線断面に対応する半導体装置の断面図である。 図１（ａ）に示す半導体装置の製造工程を示す断面図であり、（ａ）～（ｆ）は製造工程のフローを順に示す断面図である。 封止樹脂による封止前の配線母基板の平面図を示す。 封止樹脂により封止後の配線母基板の平面図を示す。 封止工程において配線母基板上に形成される封止樹脂の移動方向を示す図である。 エアベント側での封止樹脂の巻き込みと凸状部材との関係を示す図である。 本発明の第２の実施例による半導体装置の概略構成を、封止樹脂の一部を除いて示した平面図である。 図５（ａ）のＢ－Ｂ’線断面に対応する半導体装置の断面図である。 本発明の第３の実施例による半導体装置の概略構成を、封止樹脂の一部を除いて示した平面図である。 図６（ａ）のＣ－Ｃ’線断面に対応する半導体装置の断面図である。 本発明の第４の実施例による半導体装置の概略構成を、封止樹脂の一部を除いて示した平面図である。 本発明の第５の実施例による半導体装置の概略構成を、封止樹脂の一部を除いて示した平面図である。 図８（ａ）のＤ－Ｄ’線断面に対応する半導体装置の断面図である。 図８（ａ）に示す半導体装置の変形例を示す平面図である。
　まず、発明を実施するための形態について、詳細に説明する。
　本発明の実施形態によると、半導体装置１は、基板２と、基板２の一面に搭載され、一辺に沿って配置された複数の電極２２を有する半導体チップ２０と、半導体チップ２０の一辺に沿って、基板２の一面に形成された複数の接続パッド１４と、複数の電極２２と複数の接続パッド１４とをそれぞれ接続する複数のボンディングワイヤ３１と、複数のワイヤ３１のうち、最外に位置するボンディングワイヤ３１の外側の近傍位置であって、基板２の一面から突出するように配置された凸状部材３０と、半導体チップ２０、ボンディングワイヤ３１、凸状部材３０を覆うように、基板２の一面に形成された封止樹脂部４０と、を備えることを特徴とする。
　また、半導体チップ２０の一辺は、エアベント側に配置される。さらに、凸状部材３０は、半導体チップ２０の一辺と接続パッド１４との中間位置から、一辺の延在方向と略平行な直線上に配置される。また、凸状部材３０は、ボンディングワイヤ３１のループよりも高くなるように形成される。
　このように、複数のボンディングワイヤ３１のうち、最外に位置するボンディングワイヤ３１の外側の近傍位置であって、基板２の一面から突出するように凸状部材３０を設けたことにより、封止樹脂４０の充填時に最外に位置するボンディングワイヤ３１に加わる圧力を分散することができ、最外に位置するボンディングワイヤ３１のワイヤショート及びワイヤ流れの発生を低減できる。またワイヤショート及びワイヤ流れを低減できることで、半導体装置１の信頼性を向上できる。
　また、凸状部材３０を、半導体チップ２０の一辺と接続パッド１４との中間位置から、一辺の延在方向と略平行な直線上に配置されることで、エアベント側の半導体チップ２０のエッジに沿って発生する巻き込みによる封止樹脂４０による圧力を良好に分散できる。
　さらに、凸状部材３０を、ワイヤ３１のループ高さより高くなるように形成したことで、封止樹脂４０の充填時に半導体チップ２０上よりも早く流れる半導体チップ２０の脇を流れる封止樹脂４０による巻き込みに凸状部材３０を良好に当てることができる。
　次に、本発明の各実施例について図面を参照しつつ説明する。但し、以下の説明ははんだボールが搭載されたＢＧＡ（Ball Grid Array）型の半導体装置１を例にとって説明するが、例えばＬＧＡ（Land Grid Array）型の半導体装置１にも適宜適用することができるため、本発明の技術的範囲は何ら限定解釈されないことは云うまでもない。
　（第１の実施例）
　図１は、本発明の第１の実施例である半導体装置１の概略構成を示す平面図（図１（ａ））及びＡ－Ａ’間断面図（図１（ｂ））である。
　同図において、半導体装置１は、略四角形の板状の配線基板２と、配線基板２の一面に接着部材２１を介して搭載された半導体チップ２０と、配線基板２上の一面から突出するように配置された凸状部材（流れ防止部材）３０と、接続パット１４と電源パット２２を電気的に接続するボンディングワイヤ３１（以下、単にワイヤとも言う）と、これらの部材を配線基板２上に封止する封止樹脂４０と、及び外部端子として他の装置と接続するためのはんだボール５０などを有している。
　配線基板２は、例えばガラスエポキシ基板であって、絶縁基材１１と、その両面にパターン形成された配線層（図示せず）と、配線層を覆うように形成された絶縁膜１０、１２とを有している。配線基板２の一面側の配線層には半導体チップ２０のそれぞれの短辺に沿って複数の接続パッド１４が接続形成されている。また、配線基板２の他面側には複数のランド１５が接続形成されている。複数の接続パッド１４は、図１に示す通り、配線基板２の一面の周縁部近傍に配列形成されている。また、複数のランド１５は、配線基板２の他面に格子状に配置されている。複数の接続パッド１４と複数のランド１５とは、それらに連続する配線と絶縁基材１１を貫くビア等により互いに接続されている。接続パッド１４にはワイヤ３１が接続され、ランド１５にははんだボール５０が搭載される。
　絶縁膜１０、１２は、例えばソルダーレジストである。絶縁膜１０、１２は、あらかじめ定められた所定の領域を除いて絶縁基板１１の両面前面に形成される。換言すると、絶縁膜１０、１２は、その一部が所定の領域に関して除去されており、一つ以上の開口部１３を有している。例えば、配線基板２の一面側には、開口部１３が形成される。開口部１３は、複数の接続パッド１４が形成された領域及びその周辺領域を露出させる。配線基板２の他面側においても、複数のランド１５をそれぞれ露出させる開口１３が形成される。
　半導体チップ２０は、例えばＤＲＡＭのメモリチップであって、略矩形の板状で、一面側に所定の回路及び短辺に沿って電極パッド２２が形成されている。複数の電極パッド２２は、半導体チップ２０の一辺に沿って配列形成されている。図１においては、半導体チップ２０は一端側の電極パッド２２数が、他端側の電極パッド２２数より多くなるように配置されており、電極パッド２２数が多い一端側がゲート側（Ａ側）、電極パッド２２数の少ない他端側がエアベント側（Ａ’側）に配置されるように構成されている。ゲート側よりもエアベント側に配置される電極パッド２２数が少なくなるように配置することによっても、エアベント側での巻き込みによるワイヤショート及びワイヤ流れの発生を低減できる。
　また、半導体チップ２０は、配線基板２の一面側の中央付近の位置に搭載されている。具体的には、半導体チップ２０は、その一辺が開口部１３の一辺に一致するように開口部１３に隣接して配置されている。半導体チップ２０の他面は、ダイアッタチフィルム（ＤＡＦ）等の接着部材２１により配線基板２の絶縁膜１０が形成されている領域に接着固定される。
　なお、半導体チップ２０の回路構成や機能は、本願発明とは無関係であり、電極パッド２２の数や配置は、上記例に限定されるものではない。
　エアベント側となる他端側の配線基板２上には、複数のワイヤ３１のうち、最外に位置するワイヤ３１の外側の近傍位置であって、配線基板２の一面から突出するように配置された凸状部材３０、例えばＡｕ等からなるワイヤバンプ３０が配置されている。ワイヤバンプ３０は、半導体チップ２０の一辺と接続パッド１４との中間位置から、一辺の延在方向と略平行な直線上に配置される。そして、凸状部材３０は、ワイヤ３１のループと略同じ高さとなるように、複数のワイヤバンプ３０が積層されている。尚、ワイヤバンプ３０の積層数を変更するだけで、容易に高さを調整できる。凸状部材３０は、ワイヤ３１のループ高さよりも高くなるように配置する方が好ましい。また、凸状部材３０は、配線基板２に配置された接続パッド１４上に形成される。
　ワイヤ３１は、例えばＡｕ等の導電性金属からなる。ワイヤ３１は、複数の電極パッド２２とこれらに対応する接続パッド１４との間を電気的に接続する。
　封止樹脂４０は、絶縁性樹脂であって、配線基板２の一方の面側を覆うように、半導体チップ２０、電源パッド２２、凸状部材３０及びワイヤ３１などを封止する。
　図２（ａ）から（ｆ）は、第１の実施例の半導体装置１の組立フローを示す断面図である。図３（ａ）、（ｂ）は、封止前の配線母基板１００と封止後の配線母基板１００の概略構成を示す平面図である。図４（ａ）、（ｂ）は、封止工程でのエアベント側での封止樹脂４０の巻き込みと凸状部材３０との関係を示す平面図である。
　図３（ａ）を参照すると、配線母基板１００は、位置決め穴が形成された枠部６０に囲まれた領域に、マトリクス状に配置された複数の製品形成部２００を有している。製品形成部２００の各々には、複数の接続パッド１４や開口部１３が形成され、複数の接続パット１４と半導体チップ２０の複数の電源パット２２とがワイヤ３１により接続されている。図３（ｂ）で分かるように、図３（ａ）で示した配線母基板１００の一面側に対して封止工程において封止樹脂４０を形成する一括モールドを行う。この封止工程については後でより詳しく説明する。これら製品形成部２００が後にダイシングライン１６に沿って個々に切断されて半導体装置３００となる。
　図２に戻って、配線母基板１００を用いた半導体装置３００の製造方法を工程順に説明する。
　まず、図２（ａ）に示すように、配線母基板１００の両面に絶縁膜１０、１２を形成する。絶縁膜１０、１２は、接続パッド１４及びランド１５を露出させる開口部１３を有している。
　絶縁膜１０、１２は、例えば、絶縁膜材料を全面に塗布し、乾燥及び露光によって硬化させて形成される。開口部１３となる部分は、露光されず、その後の現像により除去される。なお、開口部１３内には、配線パターンを配置しないことが望ましい。開口部１３内に配線パターンを配置する場合には、接続パッド１４と同様に、その表面にＮｉ及びＡｕメッキを形成することが望ましい。これらメッキを施しておくことにより、絶縁膜１０、１２で覆われていない場合でも、配線の信頼性を確保することができる。
　次に、図２（ｂ）のように、配線母基板１００上に、半導体チップ２０を順番に搭載する。半導体チップ２０は、開口部１３に隣接し、その一辺が開口部１３の一辺に重なるように搭載される。半導体チップ２０は、他面に設けられたＤＡＦ等の接着部材２１により配線母基板１００に接着固定される。半導体チップ２０上には、複数の電源パッド２２が配置されている。
　そして、図２（ｃ）のように、半導体チップ２０の電極パッド２２と対応する接続パッド１４との間をそれぞれワイヤ３１により接続する。ワイヤ３１は例えばＡｕからなり、ワイヤ３１を用いた結線には、図示しないワイヤボンディング装置を用いることができる。結線は、例えば、超音波熱圧着法を用いたボールボンディングにより行われる。具体的には、溶融によりボールが形成されたワイヤ３１の先端を電極パッド２２上に超音波熱圧着し、ワイヤ３１が所定のループ形状を描くように、ワイヤ３１の後端を対応する接続パッド１４上に超音波熱圧着する。
　また、ワイヤバンプ３０の形成は、同じくワイヤボンディング装置により形成される。ワイヤ３１で接続するときと同様に、溶融され先端にボールが形成されたワイヤ３１を、配線母基板１００の接続パッド１４上に超音波熱圧着することで接続し、その後、後端を引き切ることで形成される。本実施例では、配線母基板１００の接続パッド１４上に形成されたワイヤバンプ３０上に、さらに同様にワイヤバンプ３０を積層形成することで、多段のワイヤバンプ３０が形成される。
　尚、本実施例では、配線母基板１００へ半導体チップ２０を搭載した後、凸状部材３０を形成する場合について説明したが、封止工程の前であればどの工程で凸状部材３０を形成してもよく、例えば半導体チップ２０の搭載前に凸状部材３０を形成しても良い。
　図２（ｄ）に示すように、配線母基板１００の一面側に、一括モールドによって封止樹脂４０を形成する。一括モールドについては、図３及び４を参照して後述する。
　次に、図２（ｅ）に示すように、配線母基板１００の他面側のランド１５にそれぞれはんだボール５０を搭載する。これらのはんだボール５０が、半導体装置３００の外部端子として利用される。
　はんだボール５０の搭載は、例えば、複数のランド１５に対応して配列形成された複数の吸着孔を備える図示しない吸着機構を用いて行うことができる。この場合、吸着機構に複数のはんだボール５０を吸着保持させ、保持されたはんだボール５０にフラックスを転写形成して、配線母基板１００のランド１５に一括搭載する。その後、リフロー処理により、はんだボール５０とランド１５との間を接続固定する。
　次に、図２（ｆ）に示すように、封止樹脂４０を図示しないダイシングテープに接着し、封止樹脂４０及び配線母基板１００をダイシングテープに支持させる。それから図示しないダイシングブレードを用いて、配線母基板１００及び封止樹脂４０をダイシングライン１６に沿って縦横に切断する。これにより、配線母基板１００は、製品形成部２００毎に個片化される。その後、個片化された製品形成部２００及び封止樹脂４０をダイシングテープからピックアップすることで、図１に示すような半導体装置１が得られる。
　次に、図３及び４を参照して、封止樹脂１５を形成する一括モールドについて説明する。一括モールドには、例えば、図示しないトランスファーモールド装置が用いられる。
　まず、トランスファーモールド装置の上型と下型とにより形成されるキャビティ内にワイヤ３１による結線とワイヤパンプの形成までの工程が終了した配線母基板１００を配置する。次に、プランジャーに、熱硬化性のエポキシ樹脂等の原料タブレットをセットし、上型と下型とを型締めする。次に、プランジャーにより原料タブレットを加圧、溶融させ、カル部７２からランナー部７１及びゲート部７０を通してキャビティ内に封止樹脂４０（溶融樹脂）を圧入する。溶融樹脂は、ゲート部７０からエアベントへ向かって流動する。
　このとき、図４（ａ）に示すように、封止樹脂４０（溶融樹脂）は、キャビティ内でゲート側からエアベント側に向かって略真っ直ぐに進む。そして、図４（ｂ）に示すように、エアベント側で封止樹脂４０は、接続パット１４の領域に向かって、両側から中央に向かって流動する。このとき、複数のワイヤ３１のうち、最外に位置するワイヤ３１の外側の近傍位置であって、配線基板２の一面から突出するように配置されたワイヤバンプ３０が、封止樹脂４０の巻き込みにより最外に位置するワイヤ３１に加わる圧力を分散させることとなる。
　このように、複数のワイヤ３１のうち、最外に位置するワイヤ３１の外側の近傍位置であって、配線基板２の一面から突出するように凸状部材３０を設けたことにより、図４に例示するように封止樹脂４０の巻き込みにより最外に位置するワイヤ３１に加わる圧力を凸状部材３０が分散させることができる。そのため、最外に位置するワイヤ３１のワイヤショート及びワイヤ流れの発生を低減できる。また、ワイヤショート及びワイヤ流れを低減できる結果、半導体装置１の信頼性を向上できる。
　また、凸状部材３０を、半導体チップ２０の一辺と接続パッド１４との中間位置から、一辺の延在方向と略平行な直線上に配置されることで、エアベント側の半導体チップ２０のエッジに沿って発生する巻き込みによる封止樹脂４０による圧力を良好に分散できる。
　さらに、凸状部材３０を、ワイヤ３１のループ高さより高くなるように形成したことで、封止樹脂４０の充填時に半導体チップ２０上よりも早く流れる半導体チップ２０の脇を流れる封止樹脂４０による巻き込みに凸状部材３０を良好に当てることができる。
（第２の実施例）
　図５（ａ）及び（ｂ）は、本発明の第２の実施例に係る半導体装置１の概略構成を示す断面図及び平面図である。ここで、第１の実施例に係る半導体装置１と同一の部材には同一の参照符号を付与し、その説明を省略する。
　実施例２の半導体装置１は、実施例１と同様に構成されており、凸状部材３０がボンディングワイヤを用いて形成されている点で実施例１と異なる。凸状部材３０となるボンディングワイヤは複数本からなり、例えば交差するように形成されている。
　実施例２においても、ボンディングワイヤをエアベント側のワイヤ３１の外側に配置したことで、実施例１と同様に封止樹脂４０の充填時のエアベント側の巻き込みによる両端のワイヤ３１にかかる応力を分散させることができ、ワイヤショート及びワイヤ流れの発生を低減できる。さらに、凸状部材３０をボンディングワイヤで構成したことで工程を追加することなく、半導体チップ２０の電極パッド２２と配線基板２の接続パッド１４を接続するワイヤ３１を形成する工程で合わせて、凸状部材３０を形成できる。
（第３の実施例）
　図６（ａ）及び（ｂ）は、本発明の第３の実施例に係る半導体装置１の概略構成を示す断面図及び平面図である。ここで、第１の実施例及び第２の実施例に係る半導体装置１と同一の部材には同一の参照符号を付与し、その説明を省略する。
　実施例３の半導体装置１は、実施例１と同様に構成されており、凸状部材３０として小型部品、例えば受動部品３０を搭載した点で実施例１及び２と異なる。
　実施例３においても、実施例１と同様な効果が得られると共に、半導体装置１に組み込まれる小型部品の配置を変更するだけで、凸状部材３０を配置することができる。
（第４の実施例）
　図７は、本発明の第４の実施例に係る半導体装置１の概略構成を示す平面図である。ここで、第１の実施例、第２の実施例及び第３の実施例に係る半導体装置１と同一の部材には同一の参照符号を付与し、その説明を省略する。
　実施例４の半導体装置１は、４つの辺に沿ってそれぞれ複数の電極パッド２２が形成された半導体チップ２０を用いており、それぞれの辺のワイヤ３１の両端に配置されるワイヤ３１の外側に凸状部材３０となるワイヤバンプ３０が配置されている点で異なる。
　実施例４においても、実施例１と同様な効果が得られると共に、半導体チップ２０のそれぞれの辺に形成されるワイヤ３１に対応して凸状部材３０が配置されるため、配線基板２に搭載する半導体チップ２０の向きを考慮する必要がなくなる。
（第５の実施例）
　図８（ａ）及び（ｂ）は、本発明の第５の実施例に係る半導体装置１の概略構成を示す断面図及び平面図である。ここで、第１の実施例、第２の実施例、第３の実施例及び第４の実施例に係る半導体装置１と同一の部材には同一の参照符号を付与し、その説明を省略する。
　実施例５の半導体装置１は、ＭＣＰ（Multi Chip Package）に適用した場合を示しており、実施例１の半導体チップ２０の上に、同じ構成の半導体チップ２０’が９０度回転するように積層配置されている点で異なる。
　実施例５においても、エアベント側のワイヤ３１に対応して凸状部材３０を配置したことで、実施例１と同様な効果が得られると共に、複数の半導体チップ２０、２０’を搭載したことで半導体装置１の大容量化又は高機能化ができる。また上側の半導体チップ２０’のオーバーハング部が、封止樹脂４０の充填方向と垂直な方向に配置されることで、上段の半導体チップ２０’のオーバーハング部と配線基板２との隙間への充填性を向上し、オーバーハング下へのボイドの発生を低減できる。
　図９は、本発明の各実施例に係る半導体装置１の変形例を示す平面図である。この半導体装置１では、ＭＣＰにおいて、上段の半導体チップ２０’の電極パッド２２が、同図に示すようにエアベント側に配置される場合、凸状部材３０は、エアベント側に配置された上段の半導体チップ２０’の一辺と、該上段の半導体チップ２０’のエアベント側の電極パッド２２に対応した配線基板２の接続パッド１４との間の中間位置から、一辺の延在方向と略平行な直線上に配置される。
　上段の半導体チップ２０’に対応した凸状部材３０を配置し、エアベント側での巻き込みによる圧力を分散することで、下段の半導体チップ２０のエアベント側のワイヤ３１にかかる圧力が分散されるので、下段の半導体チップ２０用の凸状部材３０は設けなくても良い。
　尚、図９では、下段の半導体チップ２０上に、下段の半導体チップ２０より小さいサイズの上段の半導体チップ２０’を積層する構成について説明したが、上段の半導体チップ２０’のワイヤ３１がエアベント側に配置される構成であれば同じサイズの半導体チップ２０’をスペーサやＦＯＷ(Film On Wire)を介して重なるように積層したＭＣＰに適用しても良い。
　以上、本発明者によってなされた発明を実施例に基づき説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
　例えば上記実施例では、エアベント側に配置される複数のワイヤ３１のうち、両端に位置するワイヤ３１の外側の近傍位置にそれぞれ一つの凸状部材３０を設けた場合について説明したが、エアベント側の両端のワイヤ３１の外側の近傍位置にそれぞれ複数の凸状部材３０を配置するように構成しても良い。
　また、上記実施例では、対向する２辺に沿って電極パッド２２が配置された半導体チップ２０、４辺に沿って電極パッド２２が配置された半導体チップ２０を組み込んだ半導体装置１、２つの半導体チップ２０、２０’をクロスするように積層したＭＣＰタイプの半導体装置１に適用した場合について説明したが、エアベント側にワイヤ３１が配置される構成を有するものであれば、どのような半導体装置に適用しても良い。
　本出願は、２０１３年１月２９日に出願された、日本国特許出願第２０１３－１３９１１号からの優先権を基礎として、その利益を主張するものであり、その開示はここに全体として参考文献として取り込む。
１、３００　半導体装置
２　配線基板
１０　絶縁膜
１１　絶縁基材
１２　絶縁膜
１３　開口部
１４　接続パッド
１５　ランド
１６　ダイシングライン
２０、２０’　半導体チップ
２１　接着部材
２２　電源パッド
３０　凸状部材（ワイヤバンプ、ボンディングワイヤ、受動部品）
３１　ワイヤ
４０　封止樹脂（封止体）
５０　はんだボール
６０　枠部
７０　ゲート部
７１　ランナー部
７２　カル部
１００　配線母基板（絶縁膜、絶縁基材、絶縁膜）
２００　製品形成部

Claims (10)

  1. 　基板と、
    　前記基板の一面に搭載され、一辺に沿って配置された複数の電極を有する半導体チップと、
    　前記半導体チップの一辺に沿って、前記基板の一面に形成された複数の接続パッドと、
    　前記複数の電極と前記複数の接続パッドとをそれぞれ接続する複数のボンディングワイヤと、
    　前記複数のボンディングワイヤのうち、最外に位置するボンディングワイヤの外側の近傍位置であって、前記基板の一面から突出するように配置された凸状部材と、
    　前記半導体チップ、前記ボンディングワイヤ、前記凸状部材を覆うように、前記基板の一面に形成された封止樹脂部と、を備えることを特徴とする半導体装置。
  2. 　前記半導体チップの一辺は、エアベント側に配置されることを特徴とする請求項１に記載の半導体装置。
  3. 　前記凸状部材は、前記半導体チップの前記一辺と前記接続パッドとの中間位置から、前記一辺の延在方向と略平行な直線上に配置されることを特徴とする請求項１又は２に記載の半導体装置。
  4. 　前記凸状部材は、前記ボンディングワイヤのループ高さよりも高くなるように形成されることを特徴とする請求項１から３の何れか一項に記載の半導体装置。
  5. 　前記基板上の半導体チップにおいて、エアベント側に配置される電極の数はゲート側に配置される電極の数よりも少なくなるように形成されたことを特徴とする請求項１から４の何れか一項に記載の半導体装置。
  6. 　一辺に沿って配置された複数の電極を有する半導体チップを基板上に搭載し、
    　前記半導体チップの一辺に沿って、前記基板の一面に形成された複数の接続パッドと前記複数の電極とを複数のボンディングワイヤでそれぞれ接続し、
    　前記複数のボンディングワイヤのうち、最外に位置するボンディングワイヤの外側の近傍位置に凸状部材を前記基板の一面から突出するように配置し、
    　前記半導体チップ、前記ボンディングワイヤ、前記凸状部材を覆うように、封止樹脂部を前記基板の一面に形成することを特徴とする半導体装置の製造方法。
  7. 　前記半導体チップの一辺をエアベント側に配置することを特徴とする請求項６に記載の半導体装置の製造方法。
  8. 　前記半導体チップの前記一辺と前記接続パッドとの中間位置から、前記一辺の延在方向と略平行な直線上に、前記凸状部材を配置することを特徴とする請求項６又は７に記載の半導体装置の製造方法。
  9. 　前記ボンディングワイヤのループ高さよりも高くなるように前記凸状部材を形成することを特徴とする請求項６から８の何れか一項に記載の半導体装置の製造方法。
  10. 　前記基板上の半導体チップにおいて、エアベント側に配置される電極の数をゲート側に配置される電極の数よりも少なくなるように形成することを特徴とする請求項６から９の何れか一項に記載の半導体装置の製造方法。
PCT/JP2014/051463 2013-01-29 2014-01-24 半導体装置及び半導体装置の製造方法 WO2014119477A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653266A (ja) * 1992-08-03 1994-02-25 Yamaha Corp 半導体装置
JPH11176865A (ja) * 1997-11-21 1999-07-02 Samsung Electron Co Ltd 半導体集積回路素子
JPH11330128A (ja) * 1998-05-19 1999-11-30 Fujitsu Ltd 半導体装置
JP2000058578A (ja) * 1998-08-04 2000-02-25 Texas Instr Japan Ltd 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653266A (ja) * 1992-08-03 1994-02-25 Yamaha Corp 半導体装置
JPH11176865A (ja) * 1997-11-21 1999-07-02 Samsung Electron Co Ltd 半導体集積回路素子
JPH11330128A (ja) * 1998-05-19 1999-11-30 Fujitsu Ltd 半導体装置
JP2000058578A (ja) * 1998-08-04 2000-02-25 Texas Instr Japan Ltd 半導体装置

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