WO2014203739A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2014203739A1
WO2014203739A1 PCT/JP2014/064924 JP2014064924W WO2014203739A1 WO 2014203739 A1 WO2014203739 A1 WO 2014203739A1 JP 2014064924 W JP2014064924 W JP 2014064924W WO 2014203739 A1 WO2014203739 A1 WO 2014203739A1
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Prior art keywords
wire
semiconductor device
semiconductor chip
electrode
wiring
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PCT/JP2014/064924
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English (en)
French (fr)
Inventor
晋 稲川
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
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Priority to US14/899,514 priority Critical patent/US20160141272A1/en
Publication of WO2014203739A1 publication Critical patent/WO2014203739A1/ja

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Definitions

  • the electrode pad 21 and the relay pad 16 are connected by a first wire 22, and the relay pad 16 and the connection pad 15 are connected by a second wire 23. At this time, the second wire 23 is disposed so as to straddle the wiring 12.
  • a sealing body (sealing resin) 24 is formed on the upper surface of the wiring substrate 10 so as to cover at least the semiconductor chip 19.
  • FIG. 8 is a plan view showing a schematic configuration of the semiconductor device 300 of the third embodiment.
  • FIGS. 9A and 9B are cross-sectional views showing schematic configurations between CC ′ and DD ′ in FIG. 8, respectively.

Abstract

　第１の領域と、第１の領域の外側に配置された中継パッド及び接続パッドを有する配線基板と、一面に電極パッドが形成され配線基板の第１の領域に搭載された第１の半導体チップと、電極パッドと中継パッドを接続する第１ワイヤと、中継パッドと接続パッドとを接続する第２ワイヤとを備える半導体装置。

Description

半導体装置及びその製造方法
　本発明は、半導体装置及びその製造方法に関し、特に、ＢＧＡ（Ball Grid Array）型の半導体装置及びその製造方法に関する。
　一般的なＢＧＡ型半導体装置は、配線基板に搭載された半導体チップと、半導体チップの電極パッドと配線基板の接続パッドとを電気的に接続するボンディングワイヤを有する。
　これに関連する技術として、例えば、特開２０１３－３８２９６号（特許文献１）、特開２０００－１２４３９１号（特許文献２）がある。
　特許文献１には、複数の半導体チップを搭載したMCP（Multi Chip　Package）型の半導体装置が開示されている。また、特許文献２には、第１及び第２の半導体チップの電極と配線基板とを連続的にワイヤ接続する構成が開示されている。
特開２０１３－３８２９６号公報 特開２０００－１２４３９１号公報
　上記従来技術では、配線基板に搭載される半導体チップの一辺に配置される電極パッドの数が多い場合、或いは複数の半導体チップで同じ辺側に電極パッドが多く配置される場合に、配線基板上の配線パターンの引き回しが困難となる、或いは遠回りの配線となるという問題がある。
　そこで、本発明は、配線基板上の配線パターンの引き回しを容易に行うことが可能な半導体装置及びその製造方法を提供する。
　本発明の一態様に係る半導体装置は、
　第１の領域と、該第１の領域の外側に配置された第１及び第２の接続パッドを有する配線基板と、
　一面に第１の電極が形成され、前記配線基板の前記第１の領域に搭載された第１の半導体チップと、
　前記第１の電極と前記第１の接続パッドを接続する第１のワイヤと、
　前記第１の接続パッドと第２の接続パッドとを接続する第２のワイヤと、を備えることを特徴とする。
　また、本発明の一態様に係る半導体装置の製造方法は、
　一面に第１の領域と、該第１の領域の外側に配置された第１及び第２の接続パッドを有する配線基板を準備する工程と、
　一面に第１の電極が形成された第１の半導体チップを、前記配線基板の前記第１の領域に搭載する工程と、
　第１のワイヤにより、前記第１の電極と前記第１の接続パッドを接続する工程と、
　第２のワイヤにより、前記第１の接続パッドと第２の接続パッドとを接続する工程と、
を有することを特徴とする。
　本発明によれば、配線基板上の配線パターンの引き回しを容易に行うことができる。
本発明の第１の実施形態に係る半導体装置の概略構成を示す平面図である。 図１のＡ－Ａ’間の概略構成を示す断面図である。 本発明の第１の実施形態に係る半導体装置の変形例の概略構成を示す断面図である。 本発明の第１の実施形態に係る半導体装置の組立フローを示す断面図である。 ワイヤボンディングの処理フローを示す断面図である。 本発明の第２の実施形態の半導体装置の概略構成を示す平面図である。 図６のB-B’間の概略構成を示す断面図である。 本発明の第３の実施形態の半導体装置の概略構成を示す平面図である。 （a)、(b)は、それぞれ図８のC-C‘間、Ｄ－Ｄ’間の概略構成を示す断面図である。 本発明の第３の実施形態のワイヤボンディングの処理フローを示す断面図である。 本発明の実施形態に係る半導体装置の変形例の概略構成を示す平面図である。
　以下、図面を参照しながら、本発明の好ましい実施の形態について詳細に説明する。
（第１の実施形態）
　図１、図２を参照して、本発明の第１の実施形態に係る半導体装置の構成について説明する。
　ここで、図１は、本発明の第１の実施形態に係る半導体装置の概略構成を示す平面図である。図２は、図１のＡ－Ａ’間の概略構成を示す断面図である。
　第１の実施形態の半導体装置１００は、図１及び図２に示すように、略四角形の板状で、所定の配線パターンが形成された配線基板１０を有している。配線基板１０は、例えば、ガラスエポキシ基材やプリプレグからなる絶縁基材１１を有している。そして、絶縁基材１１の上面（一面）と下面（他面）には所定のパターンで配線（配線層）１２が形成されており、２層の配線１２はビア１３により電気的に接続されている。
　また、絶縁基材１１の上面及び下面には、絶縁膜１４（例えば、ソルダーレジスト膜）が形成されており、配線１２の一部が絶縁膜１４から露出される。配線基板１０の上面側の配線１２の絶縁膜１４の開口（SR開口２５）から露出した部位が接続パッド１５、中継パッド１６となり、配線基板１０の他面側の配線１２の絶縁膜１４の開口（SR開口２５）から露出した部位がランド１７となる。そして、このランド１７にはんだボール１８が搭載されている。
　また、配線基板１０の上面には、半導体チップ１９が接着部材（DAF）２０を介して搭載されている。半導体チップ１９は、例えばメモリ回路が形成されたメモリチップであり、例えば長方形の短辺に沿ってそれぞれ複数の電極パッド２１が配置されている。そして、一方の短辺には主にDQ系の電極パッド２１が配置され、他方の短辺にはコマンドアドレス系の電極パッド２１が配置されており、DQ系側の短辺の電極パッド２１の数はコマンドアドレス系側の電極パッド２１の数よりも多くなるように構成されている。
　電極パッド２１と中継パッド１６とは第１ワイヤ２２により接続され、中継パッド１６と接続パッド１５とは第２ワイヤ２３により接続されている。この際、第２ワイヤ２３は配線１２を跨ぐように配置されている。そして、少なくとも半導体チップ１９を覆うように配線基板１０の上面に封止体（封止樹脂）２４が形成されている。
　このような構成の下、電極パッド２１の数が多いDQ側が配置される配線基板１０の一面（上面）において、一部の配線１２が横切るように配置され、配線１２の引き回しが困難となったり、遠回りの配線となる場合に、半導体チップ１９の電極パッド２１と接続パッド１５との間に中継パッド１６を配置し、他の横切る配線１２を第２ワイヤ２３によって跨ぐように構成している。
　このような配線１２の引き回しの問題は、配線基板１０を２層の配線層から、３層以上の配線層にすることで対策することが可能ではあるが、配線基板１０の製造コストが上がり（半導体装置１００のコストアップ）、さらには層数が増えることで配線基板１０の厚さ（半導体装置１００の厚さ）も大きくなってしまう。しかしながら、第１の実施形態のように、配線１２の密集する領域に中継パッド１２を配置し、第２ワイヤ２３で他の配線１２を跨ぐように構成することで、配線基板１０のコストアップ及び基板厚が増えることなく、配線１２の引き回しの課題を容易に解決できる。
　さらに、配線基板１０に中継パッド１６を設けることで、配線基板１０のレイアウト設計の自由度を向上できる。また、引き回しせずに、第２ワイヤ２３で他の配線１２を飛び越えて接続することで、配線長を短くできる。
　また、中継パッド１６を使わずに、離間した接続パッド１５にワイヤ接続する場合には、ワイヤ長が長くなり、モールド時にワイヤ流れやワイヤショートを発生するリスクが大きくなるが、第１の実施形態では、中継パッド１６にも第１ワイヤ２２及び第２ワイヤ２３が接続されるため、ワイヤ長は同等であるが、ループしている部分の長さは短いため、ワイヤ流れやワイヤショートが発生するリスクを低減できる。
　さらに、ワイヤを中継パッド１６に接続させるため、中継パッド１６を介して電極パッド２１と接続パッド１５とを屈曲するようにワイヤを張設できるため、ワイヤショートの発生するリスクをさらに低減できる。
　また、第１の実施形態では、半導体チップ１９の電極パッド２１と配線基板１０の中継パッド１６を接続する第１ワイヤ２２と、配線基板１０の中継パッド１６と接続パッド１５を接続する第２ワイヤ２３を、一つのワイヤで連続的に構成している。そのため、ワイヤボンディングの時にワイヤ先端にボールを形成する回数を減らすことができ、ワイヤの使用量を低減できる。例えば、Auワイヤが用いられるため、Auの使用量を低減しコストを低減できる。
　尚、図２では、半導体チップ１９の電極パッド２１と配線基板１０の中継パッド１６を接続する第１ワイヤ２２と、配線基板１０の中継パッド１６と接続パッド１５を接続する第２ワイヤ２３を、一つのワイヤによって形成した場合について説明した。
　しかし、図３に示すように、半導体チップ１９の電極パッド２１と配線基板１０の中継パッド１６を接続する第１ワイヤ２２と、配線基板１０の中継パッド１６と接続パッド１５を接続する第２ワイヤ２３を、それぞれ別々のワイヤによって形成しても良い。別々のワイヤによって形成する場合には、中継パッド１６を配置する位置の自由度を向上できる。
　次に、図４を参照して、本発明の第１の実施形態に係る半導体装置の製造方法について図１、図２をも使用して説明する。ここで、図４は、第１の実施形態に係る半導体装置１００の組立フローを示す断面図である。
　まず、図４（ａ）に示すように、配線基板１０が準備される。配線基板１０は絶縁基材１１で形成されており、一面（上面）に絶縁膜１４と接続パッド１５、中継パッド１６が形成されている。一方、配線基板１０の他面（下面）には、絶縁膜１４とランド１７が形成されている。さらに、配線基板１０にはダイシングライン４０が設けられている。
　次に、図４（ｂ）に示すように、裏面に接着部材（DAF）２０が形成された半導体チップ１９が配線基板１０に搭載される。
　次に、図４（ｃ）に示すように、半導体チップ１９の電極パッド２１と配線基板１０の中継パッド１６とを第１ワイヤ２２により電気的に接続する。さらに、配線基板１０の中継パッド１６と接続パッド１５を第２ワイヤ２３により電気的に接続する。この際、第２ワイヤ２３は配線１２を跨ぐように配置される。
　ここで、図５を参照して、第１ワイヤ２２及び第２ワイヤ２３の接続方法について説明する。図５は、ワイヤボンディングの処理フローを示す断面図である。
　まず、図５（a）に示すように、第１ワイヤ２２及び第２ワイヤ２３は例えばＡｕ等からなり、キャピラリ５０の溶融された先端にボール部５２が形成されたワイヤ５１を半導体チップ１９の電極パッド２１上に超音波熱圧着する。
　次に、図５（ｂ）に示すように、キャピラリ５０を移動させて所定のループ形状を描きながらワイヤ５１の後端を中継パッド１６上に超音波熱圧着する。これにより、第１ワイヤ２２により半導体チップ１９の電極パッド２１と中継パッド１６とが接続される。
　次に、図５（ｃ）に示すように、キャピラリ５０をさらに移動させて、ワイヤ５１の後端を接続パッド１５上に超音波熱圧着する。これにより、第２ワイヤ２３により半導体チップ１９の中継パッド１６と接続パッド１５とが接続される。このようにして、ワイヤボンディングの処理が完了する。
　次に、図２（ｄ）に示すように、一括モールドすることで、配線基板１０の一面上に封止体２４（封止樹脂）が形成される。封止体２４は、例えば、図示しないトランスファーモールド装置の上型と下型からなる成形金型で、配線基板１０を型締めし、ゲートから上型と下型によって形成されたキャビティ内に熱硬化性のエポキシ樹脂を圧入させ、キャビティ内に充填された後、熱硬化させることで形成される。
　次に、図２（e）に示すように、配線基板１０の他面のランド１７上にはんだボール１８を搭載して外部端子（バンプ電極）を形成する。ボールマウント工程では、配線基板１０上のランド１７の配置に合わせて複数の吸着孔が形成された図示しない吸着機構を用いて、はんだボール１８を吸着孔に保持し、保持されたはんだボール１８にフラックスを転写形成し、配線基板１０のランド１７に一括搭載する。ボール搭載後、リフローすることで外部端子が形成される。
　次に、図２（ｆ）に示すように、外部端子の形成された配線基板１０は、ダイシングライン４０で切断・分離し個片化する。基板ダイシングは、配線基板１０の封止体２４をダイシングテープに接着し、ダイシングテープによって配線基板１０を支持する。配線基板１０を図示しないダイシングブレードにより縦横にダイシングライン４０を切断して配線基板１０を個片化する。個片化完了後、ダイシングテープからピックアップすることで、図２に示すような半導体装置１００が得られる。
（第２の実施形態）
　次に、図６、図７を参照して、本発明の第２の実施形態に係る半導体装置２００の構成について説明する。ここで、図６は、第２の実施形態の半導体装置２００の概略構成を示す平面図である。図７は、図６のB-B’間の概略構成を示す断面図である。尚、説明の便宜上、図１、図２に示す第１の実施形態の半導体装置１００と同じ部位には同じ参照符号が付されており、その説明は省略する。
　本発明の第２の実施形態の半導体装置２００が第１の実施形態の半導体装置１００と異なる点は、配線基板１０と第１の半導体チップ１９（上段半導体チップ）との間に、他の半導体チップ７０（下段半導体チップ）が配置されている点である。他の半導体チップ７０（下段半導体チップ）は、第１の半導体チップ１９と略同じ構成を有する。
　図６及び図７に示すように、第２の実施形態の半導体装置２００では、配線基板１０上に２つの半導体チップ１９、７０が搭載されている。上述のように、第１の半導体チップ１９は上段半導体チップを構成し、他の半導体チップ７０は下段半導体チップを構成している。
　ここで、半導体チップ７０は、第１の実施形態の半導体チップ１９と同様な、メモリ回路が形成されたメモリチップであり、例えば長方形の短辺に沿ってそれぞれ複数の電極パッド２１が配置されている。上段の半導体チップ１９（メモリチップ）は下段の半導体チップ７０（メモリチップ）に対して９０°回転するように積層搭載されている。そして、半導体チップ１９、７０の一方の短辺には主にDQ系の複数の電極パッド２１が配置され、他方の短辺にはコマンドアドレス系の複数の電極パッド２１が配置されており、DQ系側の短辺の電極パッド２１の数はコマンドアドレス系側の電極パッド２１の数よりも多くなるように構成されている。
　それぞれの半導体チップ１９、７０は、電極パッド２１の数が多い短辺と配線基板１０の端部との間隔が、対向する電極パッド２１の数の少ない短辺と配線基板１０の端部との間隔よりも広くなるように配線基板１０上に搭載されている。
　そして、第１の実施形態と同様に、図６及び図７に示すように、それぞれの半導体チップ１９、７０の電極パッド２１の数が多いDQ側が配置される配線基板１０において、配線１２が密集する箇所に中継パッド１６を配置する。そして、半導体チップ１９、７０の電極パッド２１と接続パッド１５との間の中継パッド１６を介在させて、第２ワイヤ２３によって他の配線１２を跨ぐように構成している。
　第２の実施形態においても、第１の実施形態と同様な効果が得られると共に、２つの半導体チップ１９、７０をクロス積層して、配線１２の密集する領域が広くなるようにずらして配線基板１０に搭載したことで、半導体装置２００の大容量化を図ると共に、配線レイアウトの自由度を向上できる。
（第３の実施形態）
　次に、図８、図９を参照して、本発明の第３の実施形態に係る半導体装置３００の構成について説明する。ここで、図８は、第３の実施形態の半導体装置３００の概略構成を示す平面図である。図９(a)、(b)は、それぞれ図８のC-C‘間、Ｄ－Ｄ’間の概略構成を示す断面図である。
　尚、説明の便宜上、図１、図２に示す第１の実施形態の半導体装置１００と同じ部位には同じ参照符号が付されており、その説明は省略する。
　本発明の第３の実施形態の半導体装置３００は、第１の実施形態の半導体装置１００と同様に構成されているが、図８及び図９に示すように、配線基板１０上に複数の半導体チップ１９、９０が搭載され、それぞれの半導体チップ１９、９０の共通ピンとなる電極パッド２１と電極パッ９２の間を第３ワイヤ９１で接続するように構成した点が第１の実施形態と異なる。それぞれの半導体チップ１９、９０の独立ピン、例えばチップセレクトピン等の電極パッド２１、９２は、それぞれ配線基板１０の接続パッド１５に接続される。
　このように、第３の実施形態では、半導体チップ１９上に、電極パッド９２が形成され半導体チップ９０を積層する。ここで、半導体チップ１９は下段半導体チップを構成し、半導体チップ９０は上段半導体チップを構成している。また、下段の半導体チップ１９の電極パッド２１上には、Au等からなるスタッドバンプ９３が設けられている。
　第３の実施形においても、第１の実施形態と同様な効果が得られると共に、半導体チップ１９と半導体チップ９０と間の接続も含めて１つのワイヤで接続できるため、共通ピンとなる電極パッド２１、９２を１つのワイヤで接続できる。さらに、一つのワイヤで、複数の半導体チップ１９、９０と、配線基板１０の接続パッド１５と、中継パッド１６とを接続することで、ワイヤへのボール形成回数とワイヤカットの回数を減らし、ワイヤボンディング工程の処理効率を向上できる。
　次の、図１０を参照して、第３の実施形態のワイヤボンディングの処理フローについて説明する。ここで、図１０は、第３の実施形態のワイヤボンディングの処理フローを示す断面図である。
　下段の半導体チップ１９の電極パッド２１上には、Au等からなるスタッドバンプ９３が予め形成されている。
　そして、図１０（ａ）に示すように、上段の半導体チップ９０の電極パッド９２上に、キャピラリ５０のワイヤ５１のボール部５２を超音波熱圧着にてボンディングする。
　次に、図１０（ｂ）に示すように、所定のループを描き、下段の半導体チップ１９の電極パッド２１上のスタッドバンプ９３に超音波熱圧着により他端側をボンディングする。
　次に、図１０（ｃ）に示すように、ワイヤ５１を切断せずに、さらにループを描くようにキャピラリ５０を移動させて、次の他端側を配線基板１０の中継パッド１６に超音波熱圧着によりボンディングする。
　その後、図１０（ｄ）に示すように、ワイヤ５１を切断せずに、キャピラリ５０を移動させて、配線１２を跨ぐように、次の他端側を配線基板１０の接続パッド１５に超音波熱圧着によりボンディングする。このようにして、図９（ａ）に示すように、第１、第２及び第３のワイヤ２２、２３、９１を連続的に形成する。
　以上、本発明者によってなされた発明を実施形態に基づき説明したが、本発明は上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
　上記実施形態では、配線基板１０上に中継パッド１６を設けた場合について説明したが、半導体チップ１９上に中継パッド１６を設けるように構成しても良い。
　また、配線基板１０上に１つの中継パッド１６を配置した場合について説明したが、図１１に示すように、複数の中継パッド１６を経由して半導体チップ１９の電極パッド２１と配線基板１０の接続パッド１５を接続するように構成しても良い。
　また、メモリチップを搭載した場合について説明したが、配線基板１０上の配線１２が密集する構成となる半導体装置であれば、どのような半導体チップおよびチップの組合せ、例えばメモリチップとロジックチップの組合せ等、或いはどのようなパッド配置のチップに適用しても良い。
　本出願は、２０１３年６月１８日に出願された、日本国特許出願第２０１３－１２７２１６号からの優先権を基礎として、その利益を主張するものであり、その開示はここに全体として参考文献として取り込む。
１０　配線基板
１１　絶縁基材
１２　配線
１３　ビア
１４　絶縁膜
１５　接続パッド
１６　中継パッド
１７　ランド
１８　はんだボール
１９　半導体チップ
２０　接着部材
２１　電極パッド
２２　第１ワイヤ
２３　第２ワイヤ
２４　封止体
２５　SR開口
４０　ダイシングライン
５０　キャピラリ
５１　ワイヤ
５２　ボール部
７０　半導体チップ（下段）
９０　半導体チップ（上段）
９１　第３ワイヤ
９２　電極パッド
９３　スタッドバンプ
１００　半導体装置
２００　半導体装置
３００　半導体装置

Claims (18)

  1. 　第１の領域と、該第１の領域の外側に配置された第１及び第２の接続パッドを有する配線基板と、
    　一面に第１の電極が形成され、前記配線基板の前記第１の領域に搭載された第１の半導体チップと、
    　前記第１の電極と前記第１の接続パッドを接続する第１のワイヤと、
    　前記第１の接続パッドと第２の接続パッドとを接続する第２のワイヤと、を備えることを特徴とする半導体装置。
  2. 　前記第１のワイヤと前記第２のワイヤは、一つのワイヤで連続的に構成されることを特徴とする請求項１に記載の半導体装置。
  3. 　前記第１のワイヤと前記第２のワイヤは、別々のワイヤで構成されることを特徴とする請求項１に記載の半導体装置。
  4. 　前記第１の領域の外側には、さらに配線が設けられており、
    　前記第２のワイヤは、前記配線を跨ぐように配置されていることを特徴とする請求項１から３のいずれか１項に記載の半導体装置。
  5. 　前記第１の半導体チップは、略長方形に構成されており、
    　前記第１の電極は、前記略長方形の第１及び第２の短辺に沿って複数個配置されており、
    　前記第１の短辺に配置される前記第１の電極の数は、前記第２の短辺に配置される前記第１の電極の数よりも多く、
    　前記第１の短辺側において、前記第２のワイヤを介して前記第１の接続パッドと前記第２の接続パッドとが接続されていることを特徴とする請求項４に記載の半導体装置。
  6. 　前記第１の短辺側は、前記配線が密集している配線密集領域であることを特徴とする請求項５に記載の半導体装置。
  7. 　前記第１の接続パッドは、前記配線密集領域において中継パッドを構成し、
    　前記中継パッドを経由して、前記第２のワイヤが前記配線を飛び越えて前記第２の接続パッドと接続されることを特徴とする請求項６に記載の半導体装置。
  8. 　前記第１のワイヤは、前記第１の電極と前記中継パッドとの間で屈曲した状態で接続されることを特徴とする請求項７に記載の半導体装置。
  9. 　前記配線基板と前記第１の半導体チップとの間には、前記第１の半導体チップと略同じ構成を有する他の半導体チップが配置されており、
    　前記第１の半導体チップは前記他の半導体チップに対して９０°回転するように積層搭載されており、
    　前記第１の短辺と前記配線基板の端部との間隔は、前記第２の短辺と前記配線基板の端部との間隔よりも広いことを特徴とする請求項５から８のいずれか１項に記載の半導体装置。
  10. 　一面に第２の電極が形成され、前記第１の半導体チップ上に積層された第２の半導体チップと、
    　前記第１の電極と前記第２の電極を接続する第３のワイヤを、さらに備えることを特徴とする請求項１から８のいずれか１項に記載の半導体装置。
  11. 　前記中継パッドは、前記第１の電極と前記第２の接続パッドとの間に複数個設けられていることを特徴とする請求項７から１０のいずれか１項に記載の半導体装置。
  12. 　一面に第１の領域と、該第１の領域の外側に配置された第１及び第２の接続パッドを有する配線基板を準備する工程と、
    　一面に第１の電極が形成された第１の半導体チップを、前記配線基板の前記第１の領域に搭載する工程と、
    　第１のワイヤにより、前記第１の電極と前記第１の接続パッドを接続する工程と、
    　第２のワイヤにより、前記第１の接続パッドと第２の接続パッドとを接続する工程と、
    を有することを特徴とする半導体装置の製造方法。
  13. 　少なくとも前記第１の半導体チップを覆うように、前記配線基板の前記一面に封止樹脂を形成する工程をさらに有することを特徴とする請求項１２に記載の半導体装置の製造方法。
  14. 　前記第１のワイヤと前記第２のワイヤは、一つのワイヤで連続的に形成することを特徴とする請求項１２又は１３に記載の半導体装置の製造方法。
  15. 　前記第１のワイヤと前記第２のワイヤは、別々のワイヤで形成することを特徴とする請求項１２又は１３に記載の半導体装置の製造方法。
  16. 　前記第１の領域の外側に配線を形成する工程をさらに有し、
    　前記第２のワイヤは前記配線を跨ぐように形成されることを特徴とする請求項１２から１５のいずれか１項に記載の半導体装置の製造方法。
  17. 　前記第１の半導体チップ上に、一面に第２の電極が形成された第２の半導体チップを積層する工程と、
    　第３のワイヤにより、前記第１の電極と前記第２の電極を接続する工程をさらに有することを特徴とする請求項１２から１６のいずれか１項に記載の半導体装置の製造方法。
  18. 　前記第１の半導体チップの前記第１の電極上に、スタッドバンプを予め形成する工程と、
    　前記第２の半導体チップの前記第２の電極上に、キャピラリのワイヤのボール部を超音波熱圧着にてボンディングする工程と、
    　前記キャピラリを移動させて、前記ワイヤが所定のループを描くように前記スタッドバンプに超音波熱圧着により前記ボール部をボンディングする工程と、
    　前記ワイヤを切断せずに、さらにループを描くように前記キャピラリを移動させて、前記配線基板の前記第１及び第２の接続パッドに超音波熱圧着によりボンディングする工程と、をさらに有し、これにより、前記第１、第２及び第３のワイヤを連続的に形成することを特徴とする請求項１７に記載の半導体装置の製造方法。
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