JP5972539B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5972539B2 JP5972539B2 JP2011174576A JP2011174576A JP5972539B2 JP 5972539 B2 JP5972539 B2 JP 5972539B2 JP 2011174576 A JP2011174576 A JP 2011174576A JP 2011174576 A JP2011174576 A JP 2011174576A JP 5972539 B2 JP5972539 B2 JP 5972539B2
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- semiconductor chip
- semiconductor device
- wire
- electrode pads
- electrode
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/3862—Sweep
Description
図4を参照して、本発明の第1の実施例の第1の変形例に係るMCP型半導体装置10Aについて説明する。図4はMCP型半導体装置10Aを示す要部断面図である。図1及び図2に示したMCP型半導体装置10と同様の機能を有するものには同一の参照符号を付し、説明の簡略化のために以下では相違点についてのみ説明する。
図5を参照して、本発明の第1の実施例の第2の変形例に係るMCP型半導体装置10Bについて説明する。図5はMCP型半導体装置10Bを示す要部断面図である。図1及び図2に示したMCP型半導体装置10と同様の機能を有するものには同一の参照符号を付し、説明の簡略化のために以下では相違点についてのみ説明する。
12 配線基板
12a 配線基板の主面(上面)
12b 配線基板の裏面(下面)
121 絶縁基材
122 第1の絶縁膜(SR)
123 第2の絶縁膜(SR)
124 第1の接続パッド
125 第2の接続パッド
126 ランド部
14 第1の半導体チップ
14a 第1の半導体チップの主面(上面)
141 第1の電極パッド
16 第2の半導体チップ
16a 第2の半導体チップの主面(上面)
161 第2の電極パッド
18 第1の接着部材(DAF)
20 第2の接着部材(DAF)
22 第1のワイヤ
221 幅広部
24 第2のワイヤ
241 幅広部
26 封止樹脂層
28 半田ボール
30 バンプ電極(ワイヤバンプ)
40 スペーサ
42 第3の接着部材(DAF)
44 接着部材(FOW)
Claims (10)
- 主面上に複数個の第1の接続パッドと複数個の第2の接続パッドとを有する配線基板と、
該配線基板の主面上に搭載され、複数個の第1の電極パッドを有する第1の半導体チップと、
前記配線基板の主面上に搭載され、前記複数個の第1の電極パッドより小さいサイズの複数個の第2の電極パッドを有する第2の半導体チップと、
前記複数個の第1の電極パッドと前記複数個の第1の接続パッドとをそれぞれ接続する複数本の第1のワイヤと、
前記複数個の第2の電極パッドと前記複数個の第2の接続パッドとをそれぞれ接続し、一端に幅広部を有する複数本の第2のワイヤと、
を含む半導体装置であって、
前記複数個の第1の電極パッドは前記複数本の第2のワイヤの幅広部より大きく、前記複数個の第2の電極パッドは前記複数本の第2のワイヤの幅広部より小さく構成され、
前記複数本の第2のワイヤは、前記幅広部が前記複数個の第2の接続パッドに接続されると共に、他端が前記複数個の第2の電極パッド上に前記複数個の第2の電極パッドより小さい複数個のバンプ電極を介して接続される、
ことを特徴とする半導体装置。 - 前記第1の半導体チップと前記第2の半導体チップとが、前記配線基板の主面上に積層されている、請求項1に記載の半導体装置。
- 前記第2の半導体チップが前記配線基板の主面上に搭載され、前記第1の半導体チップが前記第2の半導体チップ上に積層されている、ことを特徴とする請求項2に記載の半導体装置。
- 前記第1の半導体チップは、前記複数個の第2の電極パッドを露出させるように、ずらして前記第2の半導体チップ上に積層されている、請求項3に記載の半導体装置。
- 前記複数個の第1の電極パッドの中の特定の第1の電極パッドと、前記複数個の第2の電極パッドの中の特定の第2の電極パッドとが同電位である場合、前記複数本の第1のワイヤの中の特定の第1のワイヤは、前記特定の第1の電極パッドと前記特定の第2の電極パッドとを接続する、請求項4に記載の半導体装置。
- 前記第1の半導体チップは、スペーサを介して、前記第2の半導体チップ上に積層されている、請求項3に記載の半導体装置。
- 前記第1の半導体チップは、前記複数個の第2のワイヤを埋め込み可能な接着部材を介して、第2の半導体チップ上に積層されている、請求項3に記載の半導体装置。
- 前記第1の半導体チップが前記配線基板の主面上に搭載され、前記第2の半導体チップが前記第1の半導体チップ上に積層されている、ことを特徴とする請求項2に記載の半導体装置。
- 前記第2の半導体チップは、前記複数個の第1の電極パッドを露出させるように、ずらして前記第1の半導体チップ上に積層されている、請求項8に記載の半導体装置。
- 前記第1の半導体チップと前記第2の半導体チップとが、前記配線基板の主面上に並置されている、請求項1に記載の半導体装置。
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JP2011174576A JP5972539B2 (ja) | 2011-08-10 | 2011-08-10 | 半導体装置 |
EP12176963.2A EP2557594B1 (en) | 2011-08-10 | 2012-07-18 | Semiconductor device reducing risks of a wire short-circuit and a wire flow |
US13/561,793 US8975760B2 (en) | 2011-08-10 | 2012-07-30 | Semiconductor device reducing risks of a wire short-circuit and a wire flow |
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JP2015115522A (ja) * | 2013-12-13 | 2015-06-22 | ソニー株式会社 | 固体撮像装置および製造方法、並びに電子機器 |
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