JP6142800B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6142800B2 JP6142800B2 JP2013557394A JP2013557394A JP6142800B2 JP 6142800 B2 JP6142800 B2 JP 6142800B2 JP 2013557394 A JP2013557394 A JP 2013557394A JP 2013557394 A JP2013557394 A JP 2013557394A JP 6142800 B2 JP6142800 B2 JP 6142800B2
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Description
図1は、本実施形態に係る半導体装置を示す断面図である。
また、第1の外部電極114の配置場所は、図1に示す再配線層113における第1の樹脂112の表面上に延伸した領域に限定されるものではない。例えば、図2に示すように、第1の半導体チップ101上およびその周囲の第1の樹脂112上の全面に配置しても構わない。
また、図3に示すように、平面視における第1の外部電極114の配置場所を、第1の半導体チップ101と重畳しない第1の樹脂112上に限定して配置しても良い。
また、図4に示すように、少なくともシリコン貫通電極105と重畳しない第1の半導体チップ101上およびその周囲の第1の樹脂112上に限定して配置しても良い。
また、図5に示すように、第2の半導体チップ108の裏面、側面を露出させても構わない。これは、封止形成後に裏面研削する、あるいは、封止形成時にあらかじめ裏面をシートで保護してから封止後にシートを引き剥がす等の処理により容易に実現することができる。なお、図1〜4においても、第2の半導体チップ108の裏面を露出させても構わない。
また、図6に示すように、第1の半導体チップ101のうち、向かい合う2つの側面を第1の樹脂112から露出させることも可能である。このとき、露出される向かい合う2辺とは異なる向かい合う2つの側面は第1の樹脂112によって覆われている。図6では、第2の半導体チップ108の裏面を第1の樹脂112で覆い、第2の半導体チップ108の側面を露出させている。しかし、第1変形例のように、第2の半導体チップ108の裏面を露出させても構わない。(図示せず)また、第2の半導体チップ108の側面を第1の樹脂112で覆っていても構わない(図示せず)。
また、図7に示すように、図1における接着剤111は、第2の樹脂116としてもよい。このとき、第1の樹脂112と第2の樹脂116とは同一の材料で、かつ、同時に形成しても良い。また、第1の樹脂112と第2の樹脂とは同一の材料とし、別々に形成しても良い。また、第1の樹脂112と第2の樹脂116は、異なる材料で、別々に形成しても良い。
また、図8に示すように、第1の半導体チップ101の裏面にも再配線層117が施されていてもよい。再配線層117は、第1の半導体チップ101の裏面の貫通電極部からCu配線で再配線するものである。再配線の端部上に第2の外部電極118が形成され、第2の外部電極118が第2の半導体チップ108の外部電極と接合されている。Cu配線上ではポリイミドやソルダーレジスト等の保護用絶縁膜が形成されていても良い。
また、図9に示すように、例えば、第1の外部電極114のピッチが150μm以上の場合には、その半導体装置を実装する基板としては、例えばサブトラクト法のような低コストプロセスで製造される比較的安価な基板、また、表面処理に電解めっきが施された基板を配線基板119として用いることができる。配線基板119は、表面と裏面をつなぐ電気配線を有する。表面では、第1の外部電極114が電気配線と接続され、裏面では、電気配線と接続された外部接続電極を有する。外部接続電極の間の最小ピッチが300μm以上である。その際には、線膨張係数が低い基板、例えばα=3〜15ppm/℃の基板を用いればよい。
図10〜図19は、本実施形態に係る第1の半導体装置の製造方法を示す工程断面図である。
図10〜図14および図20、図21は、本実施形態に係る第2の半導体装置の製造方法を示す工程断面図である。図10〜図14については第2の実施形態と同様の製造方法であるため、ここでの説明は省略する。
102 配線
103 層間絶縁膜
104 配線層
105 シリコン貫通電極
106 絶縁膜
107 第1の電極
108 第2の半導体チップ
109 第2の電極
110 第1の積層体
111 接着剤
112 第1の樹脂
113 再配線層
114 第1の外部電極
116 第2の樹脂
117 再配線層
118 第2の外部電極
119 配線基板
201 第1のシリコン基板
202 シリコン貫通電極
203 絶縁膜
204 第1の電極
206 第2のシリコン基板
208 第2の電極
209 第1の半導体チップ
210 接着剤
211 第1の積層体
212 第2の半導体チップ
213 接着層
214 支持基板
215 第1の樹脂
216 第1の再構成ウエハ
217 第1の再配線層
218 第1の外部電極
219 第2の再構成ウエハ
220 第1の樹脂
221 第2の再配線層
222 第3の外部電極
223 第2の積層体
301 再配線
Claims (20)
- 素子および配線層が形成された主面と、前記主面に対向する裏面と、前記主面と前記裏面との間を貫通する貫通電極とを有する第1の半導体チップと、
素子が形成された主面と、前記主面に対向する裏面とを有する第2の半導体チップとを備え、
前記第1の半導体チップと前記第2の半導体チップとは、前記第1の半導体チップの裏面側と前記第2の半導体チップの主面側が互いに対向するように接合部を介して積層されており、
前記第1の半導体チップの側面の少なくとも一部は第1の樹脂で覆われており、
前記第1の半導体チップの主面の最表面となる前記配線層の表面と前記第1の樹脂の表面とで形成される平面上に再配線層が形成され、
前記再配線層は前記配線層に含まれる配線と直接接続されており、
前記第2の半導体チップの主面内にある電極の少なくとも一部は、前記第1の半導体チップを貫通する前記貫通電極を介して、前記配線層上に形成された第1の外部電極の少なくとも一部に電気的に接続されており、
前記貫通電極は、前記第1の外部電極のうちで最も内側に配置された第1の外部電極よりも更に内側に配置されている半導体装置。 - 前記第1の半導体チップの主面の面積は、前記第2の半導体チップの主面の面積と異なる請求項1に記載の半導体装置。
- 前記第1の半導体チップの主面の面積は、前記第2の半導体チップの主面の面積よりも小さい請求項1に記載の半導体装置。
- 前記第1の半導体チップと前記第2の半導体チップとは厚さが異なる請求項1〜3のいずれか1項に記載の半導体装置。
- 前記第1の半導体チップは前記第2の半導体チップよりも薄い請求項1〜3のいずれか1項に記載の半導体装置。
- 前記第1の外部電極は、前記配線層における前記第1の半導体チップの主面上および前記第1の樹脂の表面上のいずれの領域にも配置されている請求項1〜5のいずれか1項に記載の半導体装置。
- 前記第1の外部電極は、前記配線層における前記第1の樹脂の表面上のみに配置されている請求項1〜5のいずれか1項に記載の半導体装置。
- 前記第1の半導体チップと前記第2の半導体チップとの接合部の接合ピッチと前記貫通電極の電極間ピッチとは同じである請求項1〜7のいずれか1項に記載の半導体装置。
- 前記第1の樹脂は、更に、前記第1の半導体チップの裏面の一部および前記第2の半導体チップの周囲を覆うように形成されている請求項1〜8のいずれか1項に記載の半導体装置。
- 前記第1の樹脂は、前記第1の半導体チップの裏面の一部および前記第2の半導体チップの主面を覆い、前記第2の半導体チップの裏面もしくは側面の少なくとも一部を露出するように形成されている請求項1〜8のいずれか1項に記載の半導体装置。
- 前記第1のチップの向かい合う2つの側面は、前記第1の樹脂から露出されている請求項1〜10のいずれか1項に記載の半導体装置。
- 前記第1の半導体チップと前記第2の半導体チップとの接合部の周辺領域を覆う第2の樹脂をさらに備える請求項1〜11のいずれか1項に記載の半導体装置。
- 前記第1の半導体チップの裏面に再配線層が形成されている請求項1〜12のいずれか1項に記載の半導体装置。
- 前記第1の外部電極の間の最小ピッチが150μm以上である請求項1〜13のいずれか1項に記載の半導体装置。
- 表裏面をつなぐ電気配線を有し、
表面側において、前記第1の外部電極が前記電気配線に接続され、
裏面側において、外部接続電極を有する配線基板をさらに有し、
前記外部接続電極の間の最小ピッチが300μm以上である請求項1〜14のいずれか1項に記載の半導体装置。 - 前記第2の半導体チップが複数層積層して形成されている請求項1〜15のいずれか1項に記載の半導体装置。
- 積層された前記第2の半導体チップのうち、最上層に形成された前記第2の半導体チップの裏面側が前記第1の樹脂から露出している請求項16に記載の半導体装置。
- 前記第1の半導体チップは素子領域にロジック回路が搭載されたロジックチップであり、前記第2の半導体チップは素子領域にメモリ回路が搭載されたメモリチップである請求項1〜17のいずれか1項に記載の半導体装置。
- 第1の半導体基板の主面上に素子領域を形成するとともに、主面側から裏面側に前記第1の半導体基板を貫通する貫通電極を形成する工程(a)と、
前記第1の半導体基板の裏面側に露出した前記貫通電極の端部と電気的に接続された第1の電極を形成する工程(b)と、
前記第1の半導体基板を切断して個片化し、第1の半導体チップとする工程(c)と、
第2の半導体基板の主面上に素子領域を形成する工程(d)と、
前記第1の半導体チップの裏面側に形成された前記第1の電極と、前記第2の半導体基板の主面側の前記素子領域に形成された第2の電極とを接合して第1の積層体を形成する工程(e)と、
前記第1の積層体における前記第2の半導体基板を切断して個片化し、第3の積層体とする工程(f)と、
前記第3の積層体における前記第1の半導体チップの主面側を、支持基板上に貼り合わせる工程(g)と、
前記支持基板上に貼り合わせた前記第3の積層体の周囲を、樹脂を用いてモールドする工程(h)と、
前記第3の積層体をその周囲の前記樹脂とともに前記支持基板から剥がす工程(i)と、
前記第3の積層体における前記第1の半導体チップの主面と前記樹脂の表面とで形成される平面上に、配線層と前記配線層に接続された外部電極とを形成する工程(j)とを備える半導体装置の製造方法。 - 第1の半導体基板の主面上に素子領域を形成するとともに、主面側から裏面側に前記第1の半導体基板を貫通する貫通電極を形成する工程(a)と、
前記第1の半導体基板の裏面側に露出した前記貫通電極の端部と電気的に接続された第1の電極を形成する工程(b)と、
前記第1の半導体基板を切断して個片化し、第1の半導体チップとする工程(c)と、
第2の半導体基板の主面上に素子領域を形成する工程(d)と、
前記第1の半導体チップの裏面側に形成された前記第1の電極と、
前記第2の半導体基板の主面側の前記素子領域に形成された第2の電極とを接合して第1の積層体を形成する工程(e)と、
前記第1の積層体の周囲を、樹脂を用いてモールドする工程(k)と、
前記樹脂の上部を除去して、前記第1の積層体における前記第1の半導体チップの主面を露出するとともに、前記第1の半導体チップの主面と前記樹脂の表面とで平面を形成する工程(l)と、
前記第1の積層体における前記第1の半導体チップの主面と前記樹脂の表面とで形成される平面上に、配線層と前記配線層に接続された外部電極とを形成する工程(m)と、
前記第1の積層体における前記第2の半導体基板を切断して個片化し、第2の積層体とする工程(n)とを備える半導体装置の製造方法。
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2013
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US9917066B2 (en) | 2018-03-13 |
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