JP2006032871A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2006032871A
JP2006032871A JP2004213696A JP2004213696A JP2006032871A JP 2006032871 A JP2006032871 A JP 2006032871A JP 2004213696 A JP2004213696 A JP 2004213696A JP 2004213696 A JP2004213696 A JP 2004213696A JP 2006032871 A JP2006032871 A JP 2006032871A
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Japan
Prior art keywords
electrode
semiconductor device
semiconductor chip
lead frame
laminated
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JP2004213696A
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English (en)
Inventor
Shuji Kamata
周次 鎌田
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Toshiba Corp
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Toshiba Corp
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Priority to JP2004213696A priority Critical patent/JP2006032871A/ja
Priority to US11/185,777 priority patent/US20060017159A1/en
Priority to CNB2005100849673A priority patent/CN100401487C/zh
Publication of JP2006032871A publication Critical patent/JP2006032871A/ja
Pending legal-status Critical Current

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Abstract

【課題】 半導体チップの表面に形成された電極に配線接続手段を十分な強度で接続するのに最適な構造を有する半導体装置を提供することを目的とする。
【解決手段】 半導体チップ１４の主面にＡｌ電極１１とＣｕ電極１２が積層された積層電極１３を形成し、積層電極１３の一部にＡｌ電極１１が露出した接続パッド１９、２２を設ける。
接続パッド１９、２２を少なくとも表面がＣｕを主に含まない材料で構成された接続導体１７、２０を介してリードフレームのリード端子１８、２１に接続する。
【選択図】 図１

Description

本発明は、半導体装置に係り、特に半導体チップの表面に形成された電極に配線接続手段を十分な強度で接続するのに最適な構造を有する半導体装置に関する。
従来、半導体チップの配線とパッケージの配線とを接続した半導体装置では半導体チップの接続パッドに対してワイヤーボンデインクをおこなって半導体装置が製造されていた。
近年、半導体装置の高度化に伴い、Ａｌ（アルミニウム）よりも導電性の良いＣｕ（銅）が配線材料として用いられている。例えば、パワーＭＯＳトランジスタでは大電力化に伴い、電極の抵抗による電力損失を減らすために、Ａｌの上にＣｕを積層した構造の電極が用いられている。
然しながら、Ｃｕ電極の接続パットにＡｌまたはＡｕ（金）ワイヤーを接続する場合に、例えばＣｕを加熱して還元雰囲気中で接合させるなどの方法がおこなわれるが、ＣｕはＡｌまたはＡｕと合金層を形成し難いため十分な接続強度が得られない問題がある。
これに対して、Ｃｕ電極の上にＡｌまたはＡｕと合金層を形成しやすい金属の接続パッドを形成し、この接続パッドに接続導体を接続する方法が知られている（例えば、特許文献１参照。）。
特許文献１に開示されたＣｕ電極と接続導体の接続方法では、回路基板の電極、例えばプリント配線板のＣｕ電極上に厚さ０．３〜１．２μｍのＳｎ（錫）メッキ層を形成し、半導体チップの電極上に形成した金バンプとＳｎメッキ層とをＳｎの融点以下の加熱状態で加圧して、固層反応によってＡｕ−Ｓｎ合金層を形成させ、プリント配線板上に半導体チップをフリップチップ実装している。
また、Ｃｕ電極の上に形成したＮｉバリア層を介してＡｕバンプを形成した半導体装置が知られている（例えば、特許文献２参照。）。
特許文献２に開示された半導体装置では、Ｃｕ電極の接続パッド上に、無電界メッキ法により形成された厚さ１μｍ程度のＣｕ層と、無電界メッキ法により形成された厚さ０．５〜５μｍ程度のＮｉバリア層とが積層され、Ｎｉバリア層上には、Ａｕバンプが形成されている。
然しながら、特許文献１または特許文献２に開示された方法では、Ｃｕ電極の上にＳｎまたはＮｉを無電界メッキ法により形成しているので、製造工程が増加し、メッキ層が厚くなるほどその形成コストが高くなる問題がある。
特開平１１−１９１５７５号公報（３頁、図１） 特開２０００−９１３６９号公報（４頁、図１）
本発明は、半導体チップの表面に形成された電極に配線接続手段を十分な強度で接続するのに最適な構造を有する半導体装置を提供する。
上記目的を達成するために、本発明の一態様の半導体装置では、リードフレームと、主面と反対面側が前記リードフレーム上に載置された半導体チップと、前記半導体チップの主面に形成されたアルミニウムを主成分とする第１電極と、一端部が前記第１電極に接続され、他端部が前記リードフレームのリード端子に接続され、少なくとも表面が銅を主に含まない材料で構成された線または帯状の配線接続手段と、前記第１電極上に少なくとも前記一端部が接続された領域を除いて選択的に形成された銅を主成分とする第２電極とを有することを特徴としている。
また、本発明の別態様の半導体装置では、リードフレームと、主面側が前記リードフレーム上に載置された半導体チップと、前記半導体チップの主面に形成されたアルミニウムを主成分とする第１電極と、一端部が前記第１電極に接続され、他端部が前記リードフレームのリード端子に接続され、少なくとも表面が銅を主に含まない材料で構成された突起状の配線接続手段と、前記第１電極上に少なくとも前記一端部が接続された領域を除いて選択的に形成された銅を主成分とする第２電極とを有することを特徴としている。
本発明によれば、Ａｌ電極の上にＣｕ電極を積層した積層電極の一部にＡｌ電極が露出した接続パッドを設けたので、少なくとも表面がＣｕを主に含まない材料で構成された配線接続手段を十分な強度で接続することができる。
その結果、十分な接続信頼性が得られ、信頼性の高い半導体装置を提供することができる。
以下、本発明の実施例について図面を参照しながら説明する。
本発明の実施例１に係る半導体装置について、図１および図２を参照して説明する。図１は本発明の実施例１に係る半導体装置の構成を示す図で、図１（ａ）はその外囲器の一部が切り欠きされた平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し、矢印の方向に眺めた断面図、図２は半導体チップの構成を示す図で、図２（ａ）はその平面図、図２（ｂ）は図２（ａ）のＢ−Ｂ線に沿って切断し、矢印の方向に眺めた断面図、図２（ｃ）は図２（ａ）のＣ−Ｃ線に沿って切断し、矢印の方向に眺めた断面図である。
図１に示すように、本実施の形態の半導体装置１０は、表面にＡｌ電極１１と、Ａｌ電極１１の上にＣｕ電極１２が積層された積層電極１３を有する半導体チップ１４、例えば表面に複数の積層電極１３、例えばゲート電極Ｇとソース電極Ｓ、および裏面に単一の電極、例えばドレイン電極Ｄ（図示せず）を有するｎチャンネル縦型絶縁ゲート電界効果トランジスタ、例えばパワーＭＯＳトランジスタを８ピンのスモールアウトラインパッケージ（ＳＯＰ：Small Outline Package）に収納した場合の例である。
即ち、半導体チップ１４はニッケルまたは半田メッキされた銅製のリードフレーム１５上にドレイン電極Ｄを下向きにして載置されている。
ドレイン電極Ｄは、リードフレーム１５のアイランド部１５ａに導電性接着剤で固着され、複数のリード端子１６に接続されている。
ソース電極Ｓは、複数の接続導体１７を介して複数のリード端子１８に接続されている。即ち、複数の接続導体１７の一端部１７ａがソース電極Ｓの一部にＡｌ電極１１を露出させた接続パッド１９に接続され、複数の接続導体１７の他端部１７ｂが複数のリード端子１８に接続されている。
同様に、ゲート電極Ｇは、接続導体２０を介してリード端子２２に接続されている。即ち、接続導体２０の一端部がゲート電極Ｇの一部にＡｌ電極１１を露出させた接続パッド２１に接続され、接続導体２０の他端部がリード端子２２に接続されている。
そして、これら全体が樹脂２３でモールドされて、ＳＯＰ型の半導体装置１０を構成している。
次に、図２に示すように、半導体チップ１４は、半導体チップ１４の表面の中央部に角部が切り欠きされた方形状のソース電極Ｓと、半導体チップ１４の表面の外周部にソース電極Ｓを取り囲む方形状のゲート電極Ｇと、半導体チップ１４の裏面の全面にドレイン電極Ｄを有している。
ソース電極Ｓおよびゲート電極Ｇは、例えば厚さ２〜６μｍ程度のＡｌ電極１１と、例えば厚さ５〜１０μｍ程度のＣｕ電極１２との積層電極１３で、Ａｌ電極１１とＣｕ電極１２の間にはＡｌとＣｕの密着性を向上させるために、例えば厚さ１〜５μｍ程度のＮｉ（ニッケル）中間層２５が形成されている。ドレイン電極Ｄには、例えば厚さ２〜６μｍ程度のＡｌ電極２６が形成されている。
そして、ソース電極Ｓおよびゲート電極Ｇの一部にＡｌ電極１１を露出させた接続パッド１９、２２が形成されている。
Ａｌ電極１１とＣｕ電極１２が積層された積層電極１３では、その電極抵抗は周知のようにＡｌ電極１１の抵抗とＣｕ電極１２の抵抗を並列接続した抵抗で表されるので、Ａｌ電極１１とＣｕ電極１２の厚さに応じた電極抵抗が得られる。
即ち、図３に示すように、積層電極１３の比抵抗として、Ｃｕ電極１２の比率Ｘに応じてＡｌの比抵抗２．６５Ｅ−６Ω・ｃｍからＣｕの比抵抗１．６７３Ｅ−６Ω・ｃｍまでの範囲が得られる。
次に、半導体装置１０の製造方法について詳しく説明する。図４は半導体チップ１４にソースの積層電極１３と接続パッド１８を形成する工程を順に示す断面図である。
始に、図４（ａ）に示すように、半導体チップ１４上にＡｌ電極１１を、例えばスパッタ法により厚さ２〜６μｍ程度形成した後、図４（ｂ）に示すように、接続パッド１９が配置される位置にレジスト膜３１を、例えば厚さ１〜２μｍ程度形成する。
次に、図４（ｃ）に示すように、レジスト膜３１をマスクとしてＡｌ電極１１上にＮｉ中間層２５を、例えばＮｉメッキ液に浸漬して無電界メッキ法により、選択的に１〜５μｍ程度形成する。
次に、図４（ｄ）に示すように、レジスト膜３１をマスクとしてＮｉ中間層２５上にＣｕ電極１２を、例えばＣｕメッキ液に浸漬して無電界メッキ法により、選択的に５〜１０μｍ程度形成する。
次に、図４（ｅ）に示すように、レジスト膜３１を除去することにより、Ｎｉ中間層２５を介してＡｌ電極１１とＣｕ電極１２が積層された積層電極１３、および積層電極１３のＡｌ電極１１が露出した接続パッド１９が得られる。この接続パッド１９には、接続導体１７の一端部１７ａが接続される。
ゲートの積層電極１３と接続パッド２２も同様にして形成される。
次に、半導体チップ１４をリードフレーム１５のアイランド部１５ａに導電性接着剤で固着した後、ソース電極Ｓの接続パッド１９およびゲート電極Ｇの接続パッド２２を、接続導体１７、２０、例えばＡｕワイヤーを介してリード端子１８、２１にそれぞれ接続し、これら全体を樹脂２３でモールドすることにより、図１に示した半導体装置１０が完成する。
従って、Ａｌ電極１１とＣｕ電極１２が積層された積層電極１３の一部にＡｌ電極１１が露出した接続パッド１９、２２を設けることにより、積層電極１３に接続導体を十分な強度で接合することが可能である。
図５は、Ａｌの接続パッド１９、２２とＡｕワイヤーの接合強度を、Ｃｕ電極とＡｕワイヤーの接合強度と比較して示したもので、Ａｌ−Ａｕ接続ではＣｕ−Ａｕ接続に対して、５％程度接合強度が向上している。
以上説明したように、実施例１に係る半導体装置１０では、Ａｌ電極１１の上にＣｕ電極１２を積層した積層電極１３の一部にＡｌ電極１１が露出した接続パッド１９、２２を設けたので、少なくとも表面がＣｕを主に含まない材料で構成された接続導体を十分な強度で接続することができる。
その結果、十分な接続信頼性が得られ、信頼性の高い半導体装置を提供することができる。
ここでは、Ｃｕ電極１２を無電解メッキ法により形成する場合について説明したが、目的の厚さが得られる範囲内であれば別の方法、例えば真空蒸着法あるいはスパッタリング法などでも構わない。その場合、Ｎｉ中間層は無くても構わない。
また、ソース電極Ｓおよびゲート電極Ｇをともに積層電極１３とした場合について説明したが、ゲートには電流が殆ど流れないので動作に支障を及ぼさない範囲内であれば積層電極１３以外の電極、例えばＡｌ電極１１だけでも構わない。
図６は本発明の実施例２に係る半導体装置の構成を示す図で、図６（ａ）はその外囲器の一部が切り欠きされた平面図、図６（ｂ）は図６（ａ）のＤ−Ｄ線に沿って切断し、矢印の方向に眺めた断面図ある。
本実施例において上記実施例１と同一の構成部分には同一符号を付してその説明は省略し、異なる部分についてのみ説明する。
本実施例が実施例１と異なる点は、Ａｌ電極とＣｕ電極が積層された積層電極を有する２つのパワーＭＯＳトランジスタが集積された半導体チップをスモールアウトラインパッケージに収納したことにある。
即ち、図６に示すように、本実施の形態の半導体装置４０の半導体チップ４１は、半導体チップ４１の表面の中央部に対向して配置され、角部が切り欠きされた櫛の歯状のソース電極Ｓ１、Ｓ２と、外周部にソース電極Ｓ１、Ｓ２をそれぞれ取り囲む枠状のゲート電極Ｇ１、Ｇ２と、裏面の全面に共通のドレイン電極Ｄ（図示せず）を有している。
ソース電極Ｓ１およびＳ２には櫛の歯の根元部にＡｌ電極１１を露出させた接続パッド４２、および４３が形成され、同じく、ゲート電極Ｇ１、Ｇ２には、ソース電極Ｓ１およびＳ２の角部が切り欠きされた領域に接続パッド４４、４５が形成されている。
半導体チップ４１はニッケルまたは半田メッキされた銅製のリードフレーム４６上にドレイン電極Ｄを下向きにして載置されている。
ドレイン電極Ｄは、リードフレーム４６のアイランド部４６ａに導電性接着剤で固着され、複数のリード端子４７、４８に接続されている。
ソース電極Ｓ１は、複数の接続導体４９、例えばＡｕワイヤーを介して複数のリード端子５０に接続されている。即ち、複数の接続導体４９の一端部４９ａがソース電極Ｓ１のＡｌ電極１１を露出させた接続パッド４２に接続され、複数の接続導体４９の他端部４９ｂが複数のリード端子５０に接続されている。
ゲート電極Ｇ１は、接続導体５１を介してリード端子５２に接続されている。即ち、接続導体５１の一端部がゲート電極Ｇ１の一端部にＡｌ電極１１を露出させた接続パッド４４に接続され、接続導体５１の他端部がリード端子５２に接続されている。
同様に、ソース電極Ｓ２は、複数の接続導体５３を介して複数のリード端子５４に接続され、ゲート電極Ｇ２は、接続導体５５を介してリード端子５６に接続されている。
そして、これら全体が樹脂５７でモールドされて、ＳＯＰ型の半導体装置４０を構成している。
従って、Ａｌ電極１１とＣｕ電極１２が積層された積層電極１３の一部にＡｌ電極１１が露出した接続パッド４２〜４５を設けることにより、積層電極１３に接続導体を十分な強度で接合することが可能である。
以上説明したように、実施例２に係る半導体装置４０では、２つのパワーＭＯＳトランジスタが集積された半導体チップ４１上にＡｌ電極１１とＣｕ電極１２が積層された積層電極１３のＡｌ電極１１が露出した接続パッド４２〜４５を設けたので、十分な接続強度を有する小型の半導体装置を提供することができる。
図７は本発明の実施例３に係る半導体装置の構成を示す図で、図７（ａ）はその外囲器の一部が切り欠きされた平面図、図７（ｂ）は図７（ａ）のＥ−Ｅ線に沿って切断し、矢印の方向に眺めた断面図、図７（ｃ）は図７（ｂ）の要部を拡大した断面図である。
本実施例において上記実施例１と同一の構成部分には同一符号を付してその説明は省略し、異なる部分についてのみ説明する。
本実施例が実施例１と異なる点は、Ａｌ電極とＣｕ電極が積層された積層電極を有する２つのパワーＭＯＳトランジスタが集積された半導体チップのＡｌ電極が露出した接続パッドの上に金属バンプを形成し、リードフレームにフリップチップ接続したことにある。
即ち、図７に示すように、本実施の形態の半導体装置７０の半導体チップ７１はソース電極Ｓ１の接続パッド４２上に金属バンプ７２と、ソース電極Ｓ２の接続パッド４３上に金属バンプ（図示せず）を有している。
同様に、ゲート電極Ｇ１の接続パッド４４上に金属バンプ７３と、ゲート電極Ｇ２の接続パッド４５上に金属バンプ（図示せず）を有している。
金属バンプ７２、７３は、例えばＡｕバンプで、Ａｕバンプはボンディング装置を使用して、キャピラリ先端にＡｕ線のボールを形成し、このＡｕボールを加熱しながら超音波を印加してＡｌの接続パッド上にボンディングし、更にこの接続パッド上のＡｕボールを押し潰してＡｕバンプを形成するスタッドバンプ法により形成することができる。
半導体チップ７１はニッケルまたは半田メッキされた銅製のリードフレーム７４上にソース電極Ｓ１、Ｓ２およびゲート電極Ｇ１、Ｇ２側を下向きにして載置される。
ソース電極Ｓ１は複数の金属バンプ７２を介してリード端子７５にフリップチップ接続され、ゲート電極Ｇ１はＡｕバンプ７３を介してリード端子７６にフリップチップ接続されている。
同様に、ソース電極Ｓ２は、複数のＡｕバンプ（図示せず）を介してリード端子７７にフリップチップ接続され、ゲート電極Ｇ１は、Ａｕバンプ（図示せず）を介してリード端子７８にフリップチップ接続されている。
そして、これら全体が樹脂７９でモールドされて、ＳＯＰ型の半導体装置７０を構成している。
従って、Ａｌ電極１１とＣｕ電極１２が積層された積層電極１３の一部にＡｌ電極１１が露出した接続パッドに金属バンプを設けることにより、積層電極１３をリードフレームに十分な強度でフリップチップ接合することが可能である。
以上説明したように、実施例３に係る半導体装置７０では、２つのパワーＭＯＳトランジスタが集積された半導体チップ７１上にＡｌ電極１１とＣｕ電極１２が積層された積層電極１３のＡｌ電極１１が露出した接続パッド上に金属バンプ７２、７３を形成して、リードフレーム７４にフリップチップ接続しているので、十分な接続強度を有する小型の半導体装置を提供することができる。
ここでは、リードフレームにフリップチップ接続する場合について説明したが、プリント配線基板の接続パッドにフリップチップ接続しても構わない。
また、プリント配線基板の接続パッドがＡｌ配線とＣｕ配線が積層された積層配線のＡｌ配線が露出した接続パッドであっても構わない。
本発明の実施例１に係る半導体装置の構成を示す図で、図１（ａ）はその外囲器の一部が切り欠きされた平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し、矢印の方向に眺めた断面図。 本発明の実施例１に係る半導体チップの構成を示す図で、図２（ａ）はその平面図、図２（ｂ）は図２（ａ）のＢ−Ｂ線に沿って切断し、矢印の方向に眺めた断面図、図２（ｃ）は図２（ａ）のＣ−Ｃ線に沿って切断し、矢印の方向に眺めた断面図である。 本発明の実施例１に係るＡｌ電極と疎な電極を積層した積層電極の比抵抗の範囲を示す図。 本発明の実施例１に係る半導体チップ積層電極と接続パッドを形成する工程を順に示す断面図である。 本発明の実施例１に係る接続パッドと接続導体の接合強度を示す図。 本発明の実施例２に係る半導体装置の構成を示す図で、図６（ａ）はその外囲器の一部が切り欠きされた平面図、図６（ｂ）は図６（ａ）のＤ−Ｄ線に沿って切断し、矢印の方向に眺めた断面図。 本発明の実施例３に係る半導体装置の構成を示す図で、図７（ａ）はその外囲器の一部が切り欠きされた平面図、図７（ｂ）は図７（ａ）のＥ−Ｅ線に沿って切断し、矢印の方向に眺めた断面図、図７（ｃ）は図７（ｂ）の要部を拡大した断面図。
符号の説明
１０、４０、７０ 半導体装置
１１、２６ Ａｌ電極
１２ Ｃｕ電極
１３ 積層電極
１４、４１、７１ 半導体チップ
１５、４６、７４ リードフレーム
１６、１８、２１、４７、４８、５０、５２、５４、５６、７５、７６、７７、７８ リード端子
１７、２０、４９、５１、５３、５５ 接続導体
１７ａ、４９ａ 接続導体の一端部
１７ｂ、４９ｂ 接続導体の他端部
１９、２２、４２、４３、４４、４５ 接続パッド
２３、５７、７９ 樹脂
２５ Ｎｉ中間層
３１ レジスト膜
７２、７３ 金属バンプ

Claims (5)

  1. リードフレームと、
    主面と反対面側が前記リードフレーム上に載置された半導体チップと、
    前記半導体チップの主面に形成されたアルミニウムを主成分とする第１電極と、
    一端部が前記第１電極に接続され、他端部が前記リードフレームのリード端子に接続され、少なくとも表面が銅を主に含まない材料で構成された線または帯状の配線接続手段と、
    前記第１電極上に少なくとも前記一端部が接続された領域を除いて選択的に形成された銅を主成分とする第２電極と、
    を有することを特徴とする半導体装置。
  2. リードフレームと、
    主面側が前記リードフレーム上に載置された半導体チップと、
    前記半導体チップの主面に形成されたアルミニウムを主成分とする第１電極と、
    一端部が前記第１電極に接続され、他端部が前記リードフレームのリード端子に接続され、少なくとも表面が銅を主に含まない材料で構成された突起状の配線接続手段と、
    前記第１電極上に少なくとも前記一端部が接続された領域を除いて選択的に形成された銅を主成分とする第２電極と、
    を有することを特徴とする半導体装置。
  3. 前記アルミニウムを主成分とする第１電極と前記第１導電層上に形成された銅を主成分とする前記第２電極が積層された積層電極の前記アルミニウムを主成分とする第１電極が露出した領域を接続パッドとしたことを特徴とする請求項１または請求項２に記載の半導体装置。
  4. 前記配線接続手段がアルミニウムまたは金を主成分とする接続導体であることを特徴とする請求項１乃至請求項２のいずれか１項に記載の半導体装置。
  5. 前記アルミニウムを主成分とする第１電極と前記銅を主成分とする第２電極の間にニッケルを主成分とする中間層を更に有することを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体装置。
JP2004213696A 2004-07-22 2004-07-22 半導体装置 Pending JP2006032871A (ja)

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JP2004213696A JP2006032871A (ja) 2004-07-22 2004-07-22 半導体装置
US11/185,777 US20060017159A1 (en) 2004-07-22 2005-07-21 Semiconductor device and method of manufacturing a semiconductor device
CNB2005100849673A CN100401487C (zh) 2004-07-22 2005-07-22 半导体器件及半导体器件的制造方法

Applications Claiming Priority (1)

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JP2012001746A (ja) * 2010-06-14 2012-01-05 Tanaka Electronics Ind Co Ltd 高温半導体素子用平角状パラジウム（Ｐｄ）又は白金（Ｐｔ）被覆銅リボン
JP2017011129A (ja) * 2015-06-23 2017-01-12 三菱電機株式会社 半導体装置
WO2021181747A1 (ja) * 2020-03-11 2021-09-16 株式会社日立パワーデバイス 半導体装置

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US8921986B2 (en) * 2013-03-15 2014-12-30 Microchip Technology Incorporated Insulated bump bonding
JP6875642B2 (ja) * 2016-04-22 2021-05-26 株式会社ソシオネクスト 半導体チップおよびこれを備えた半導体装置

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KR0174983B1 (ko) * 1996-05-10 1999-02-01 김광호 유체상태의 접착제를 이용한 반도체 칩 실장 방법 및 그에 이용되는 loc형 반도체 칩 패키지의 리드 프레임
JPH10284529A (ja) * 1997-04-08 1998-10-23 Hitachi Ltd 半導体装置およびその製造方法
JP2000049184A (ja) * 1998-05-27 2000-02-18 Hitachi Ltd 半導体装置およびその製造方法
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JP2001196529A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 半導体装置及びその配線方法
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JP2004111885A (ja) * 2002-07-23 2004-04-08 Toshiba Corp 半導体装置
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012001746A (ja) * 2010-06-14 2012-01-05 Tanaka Electronics Ind Co Ltd 高温半導体素子用平角状パラジウム（Ｐｄ）又は白金（Ｐｔ）被覆銅リボン
JP2017011129A (ja) * 2015-06-23 2017-01-12 三菱電機株式会社 半導体装置
WO2021181747A1 (ja) * 2020-03-11 2021-09-16 株式会社日立パワーデバイス 半導体装置

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CN1725462A (zh) 2006-01-25
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