JP4353935B2 - リードレスパッケージ型半導体装置 - Google Patents
リードレスパッケージ型半導体装置 Download PDFInfo
- Publication number
- JP4353935B2 JP4353935B2 JP2005321697A JP2005321697A JP4353935B2 JP 4353935 B2 JP4353935 B2 JP 4353935B2 JP 2005321697 A JP2005321697 A JP 2005321697A JP 2005321697 A JP2005321697 A JP 2005321697A JP 4353935 B2 JP4353935 B2 JP 4353935B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- electrodes
- electrode
- leadless package
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
MC(MC1,MC2) MOSチップ(半導体チップ)
DC ダイオードチップ(半導体チップ)
L1 第1のリードフレーム
L2 第2のリードフレーム
TG,TS,TD,TK 外部電極
HG,HS,HD,HK,HA 電極配線部
R 封止樹脂
201,211,221,231,241 実装基板
Claims (3)
- 一方の面に1つの電極が設けられ、他方の面に複数の電極が設けられた複数の半導体チップと、前記一方の面に設けられた全ての電極が直接接続された1つの共通外部電極と、前記他方の面に設けられた全ての電極の各々に独立して直接接続された複数の個別外部電極と、前記共通外部電極と前記個別外部電極とで挟まれる領域に充填されて、前記複数の半導体チップを封止する封止樹脂とを備えることを特徴とするリードレスパッケージ型半導体装置。
- 前記個別外部電極は、前記封止樹脂から露呈された電極部と、当該電極部の面積よりも大きい面積を有する電極配線部とを有し、当該電極配線部が前記他方の面に設けられた電極に直接接続されていることを特徴とする請求項1に記載のリードレスパッケージ型半導体装置。
- 前記電極配線部は前記封止樹脂によって被覆されていることを特徴とする請求項2に記載のリードレスパッケージ型半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005321697A JP4353935B2 (ja) | 2005-11-07 | 2005-11-07 | リードレスパッケージ型半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005321697A JP4353935B2 (ja) | 2005-11-07 | 2005-11-07 | リードレスパッケージ型半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003283264A Division JP3759131B2 (ja) | 2003-07-31 | 2003-07-31 | リードレスパッケージ型半導体装置とその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006060255A JP2006060255A (ja) | 2006-03-02 |
JP4353935B2 true JP4353935B2 (ja) | 2009-10-28 |
Family
ID=36107406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005321697A Expired - Fee Related JP4353935B2 (ja) | 2005-11-07 | 2005-11-07 | リードレスパッケージ型半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4353935B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4749181B2 (ja) * | 2006-03-06 | 2011-08-17 | パナソニック株式会社 | 半導体装置とその製造方法 |
JP2008066655A (ja) * | 2006-09-11 | 2008-03-21 | Matsushita Electric Ind Co Ltd | 半導体装置、半導体装置の製造方法、及び電気機器システム |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59143348A (ja) * | 1983-02-07 | 1984-08-16 | Hitachi Ltd | 電子部品 |
JPS59211252A (ja) * | 1983-05-17 | 1984-11-30 | Nec Corp | 半導体装置 |
JPH04129233A (ja) * | 1990-09-19 | 1992-04-30 | Fujitsu Ltd | 半導体hブリッジ回路 |
JP2911265B2 (ja) * | 1991-09-27 | 1999-06-23 | 三洋電機株式会社 | 表面実装型半導体装置 |
JP4651153B2 (ja) * | 1999-10-28 | 2011-03-16 | ローム株式会社 | 半導体装置 |
JP3601432B2 (ja) * | 2000-10-04 | 2004-12-15 | 株式会社デンソー | 半導体装置 |
JP3596388B2 (ja) * | 1999-11-24 | 2004-12-02 | 株式会社デンソー | 半導体装置 |
JP2001291823A (ja) * | 2000-04-05 | 2001-10-19 | Toshiba Digital Media Engineering Corp | 半導体装置 |
JP2001313362A (ja) * | 2000-04-28 | 2001-11-09 | Mitsui High Tec Inc | 半導体装置 |
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2005
- 2005-11-07 JP JP2005321697A patent/JP4353935B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2006060255A (ja) | 2006-03-02 |
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