CN1725462A - 半导体器件及半导体器件的制造方法 - Google Patents

半导体器件及半导体器件的制造方法 Download PDF

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CN1725462A
CN1725462A CNA2005100849673A CN200510084967A CN1725462A CN 1725462 A CN1725462 A CN 1725462A CN A2005100849673 A CNA2005100849673 A CN A2005100849673A CN 200510084967 A CN200510084967 A CN 200510084967A CN 1725462 A CN1725462 A CN 1725462A
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electrode
semiconductor device
semiconductor chip
leadframe
semiconductor
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CN100401487C (zh
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镰田周次
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明提供一种半导体器件，包括：引脚框；与主面相反面侧被载置于所述引脚框上的半导体芯片；在所述半导体芯片的主面形成的以铝为主成分的第一电极；一端部与所述第一电极连接，另一端部与所述引脚框的引脚端子连接的布线；以及在所述第一电极上至少除了连接有所述布线的一端部的区域以外选择性地形成的、以铜为主成分的第二电极。

Description

半导体器件及半导体器件的制造方法
技术领域
本发明涉及一种半导体器件，特别涉及为了以充分的强度将布线连接单元连接到在半导体芯片的表面上形成的电极上而具有最适结构的半导体器件。
背景技术
以往，在通过布线来连接半导体芯片和封装(package)的半导体器件的制造工序中，对半导体芯片内的连接焊盘应用引线接合(wire bonding)法。
近年，随着半导体器件的高度化，导电性比铝优良的铜被用作布线材料。例如，在功率MOS晶体管中，随着大功率化，为了减少由电极的电阻引起的功率损失，使用将铜层叠在铝之上的结构的电极。
在将铝或金线与铜电极的连接焊盘(pad)连接时，例如进行加热铜并在还原气氛中使其接合等方法。但是，由于铜与铝或金难以形成合金层，存在不能得到充分的连接强度的问题。
对此，已知在铜电极上形成与铝或金容易形成合金层的金属的连接焊盘，并将连接导体与该连接焊盘连接的方法。
在日本特开平11-191575号公报所公开的铜电极和连接导体的连接方法中，在电路板的电极、例如印制布线板的铜电极上形成厚度0.3～1.2μm(微米)的镀锡层。接着，在半导体芯片的电极上形成的金凸块(bump)与镀锡层在锡的融点以下的加热状态下加压，通过固相反应形成金—锡合金层。作为结果，通过倒装片(flip chip)法，在印制布线板上安装半导体芯片。
此外，已知的有隔着形成在铜电极之上的镍阻挡层形成有金凸块的半导体器件。
在日本特开2000-91369号公报所公开的半导体器件中，在铜电极的连接焊盘上层叠通过无电解电镀法形成的厚度1μm左右的铜层、和通过无电解电镀法形成的厚度0.5～5μm左右的镍阻挡层。在Ni阻挡层上形成有金凸块(bump)。
但是，在专利文献1或专利文献2公开的方法中，由于通过无电解电镀法在铜电极之上形成了锡或镍，增加制造工序。存在电镀层变得越厚制造成本也就变得越高的问题。
发明内容
按照本发明一种方式，提供一种半导体器件，包括：引脚框；与主面相反面侧被载置于所述引脚框上的半导体芯片；在所述半导体芯片的主面形成的、以铝为主成分的第一电极；一端部与所述第一电极连接，另一端部与所述引脚框的引脚端子连接的布线；以及在所述第一电极上至少除了连接有所述布线的一端部的区域以外选择性地形成的、以铜为主成分的第二电极。
按照本发明的另一种方式，提供一种半导体器件，包括：引脚框；主面侧载置于所述引脚框上的半导体芯片；在所述半导体芯片的主面形成的、以铝为主成分的第一电极；一端部与所述第一电极连接，另一端部与所述引脚框的引脚端子连接的突起状的布线；以及在所述第一电极上至少除了连接有所述一端部的区域以外选择性地形成的、以铜为主成分的第二电极。
按照本发明的再一种方式，提供一种半导体器件的制造方法，包括：准备半导体芯片；在所述半导体芯片上形成以铝为主成分的第一电极；在所述第一电极上选择性地形成掩蔽膜，将所述掩蔽膜作为掩膜，在第一电极上形成以铜为主成分的第二电极；去除所述掩蔽膜；在引脚框固定所述半导体芯片；将连接导体的一端部与被去除所述掩蔽膜而露出所述第一电极表面的连接焊盘连接；以及将所述连接导体的另一端部与所述引脚框内的引脚端子连接。
附图说明
图1是表示本发明的实施例1的半导体器件的结构的图。图1A是其外围器的一部分欠缺俯视图。图1B是沿着图1A的A-A线截断并向箭头的方向看的截面图。
图2是表示本发明的实施例1的半导体芯片的结构的图。图2A是其俯视图。图2B是沿着图2A的B-B线截断并向箭头的方向看的截面图。图2C是沿着图2A的C-C线截断并向箭头的方向看的截面图。
图3是表示本发明的实施例1的铝电极和稀疏的电极层叠的层叠电极的电阻率的范围的图表。
图4是按顺序表示形成本发明的实施例1的半导体芯片层叠电极和连接焊盘的工序的截面图。
图5是表示本发明的实施例1的连接焊盘和连接导体的接合强度的图表。
图6是表示本发明的实施例2的半导体器件的结构的图。图6A是其外围器的一部分欠缺俯视图。图6B是沿着图6A的D-D线截断并向箭头的方向看的截面图。
图7是表示本发明的实施例3的半导体器件的结构的图。图7A是其外围器的一部分欠缺俯视图。图7B是沿着图7A的E-E线截断并向箭头的方向看的截面图。图7C是将图7B的主要部分放大的截面图。
具体实施方式
以下，参照附图说明本发明的实施例。
实施例1
参照图1及图2说明本发明的实施例1的半导体器件。图1是表示本发明的实施例1的半导体器件的结构的图。图1A是其外围器的一部分欠缺的俯视图。图1B是沿着图1A的A-A线截断并向箭头的方向看的截面图。图2是表示半导体芯片的结构的图。图2A是其俯视图。图2B是沿着图2A的B-B线截断并向箭头的方向看的截面图。
如图1所示，本实施方式的半导体器件10，将半导体芯片14收容在八引脚的小外型封装(SOP：Small Outline Package)中，该半导体芯片14在表面具有铝电极11、以及在铝电极11上层叠铜电极12的层叠电极13。半导体芯片14是例如在表面具有多个层叠电极13、栅电极G和源电极S，在背面具有单一的电极、漏电极D(未图示)的n沟道纵型绝缘栅场效应晶体管，即功率MOS晶体管。
半导体芯片14在进行了镀镍或焊锡的铜制的引脚框15上向下载置着漏电极D。漏电极D由导电性粘接剂固定在引脚框15的岛(island)部15a，并与多个引脚端子16连接。
源电极S通过多个连接导体17与多个引脚端子18连接。即，多个连接导体17的一端部17a与使源电极S的一部分即铝电极11露出的连接焊盘19连接。多个连接导体17的另一端部17b与多个引脚端子18连接。同样地，栅电极G通过连接导体20与引脚端子21连接。即，连接导体20的一端部与使栅电极G的一部分即铝电极11露出的连接焊盘22连接，连接导体20的另一端部与引脚端子21连接。用树脂23塑封这些整体，构成了SOP型的半导体器件10。
接着，如图2所示，半导体芯片14，其在半导体芯片14的表面的中央部具有角部欠缺的方形的源电极S，在半导体芯片14的表面的外周部具有包围源电极S的方形的栅电极G，以及在半导体芯片14的背面的整个面上具有漏电极D。
源电极S和栅电极G是例如厚度2～6μm程度的铝电极11和例如厚度5～10μm程度的铜电极12的层叠电极13。在铝电极11和铜电极12之间，为了提高铝和铜的粘接性，形成有例如厚度1～5μm程度的镍(Ni)中间层25。在漏电极D上形成有例如厚度2～6μm程度的铝电极26。源电极S及栅电极G的一部分形成有使铝电极11露出的连接焊盘19、22。
在层叠了铝电极11和铜电极12的层叠电极13中，众所周知，其电极电阻表示为将铝电极11的电阻和铜电极12的电阻并联的电阻。因此，得到与铝电极11和铜电极12的厚度相对应的电极电阻。即，如图3所示，层叠电极13的电阻率根据铜电极12的比率X，得到从铝的电阻率2.65E-6Ω·cm(欧姆·厘米)到铜的电阻率1.673E-6Ω·cm(欧姆·厘米)的范围。
接着，详细说明半导体器件10的制造方法。图4是按顺序表示在半导体芯片14上形成源的层叠电极13和连接焊盘19的工序的截面图。
首先，如图4A所示，在半导体芯片14上例如通过溅射法形成厚度2～6μm程度的铝电极11。接着，如图4B所示，在配置连接焊盘19的位置，形成例如厚度1～2μm程度的抗蚀剂31。
并且，如图4C所示，将抗蚀剂31作为掩膜，例如在镍镀液中浸渍并通过无电解电镀法，在铝电极11上选择性地形成1～5μm程度的镍中间层25。接着，如图4D所示，将抗蚀剂31作为掩膜，例如在铜镀液中浸渍并通过无电解电镀法，在镍中间层25上选择性地形成5～10μm程度的铜电极12。
接着，如图4E所示，通过去除抗蚀剂31，得到隔着镍中间层25层叠了铝电极11和铜电极12的层叠电极13、以及层叠电极13的铝电极11露出的连接焊盘19。连接导体17的一端部17a与该连接焊盘19连接。栅极的层叠电极13和连接焊盘22也同样地形成。
接着，用导电性粘接剂在引脚框15的岛部15a粘接半导体芯片14。接着，通过连接导体17、20例如金线，将源电极S的连接焊盘19和栅电极G的连接焊盘22与引脚端子18、21分别连接。并且，通过用树脂23塑封这些整体，完成图1所示的半导体器件10。
因此，在被层叠了铝电极11和铜电极12的层叠电极13的一部分，设置使铝电极11露出的连接焊盘19、22，由此可以以充分的强度在层叠电极13上接合连接导体。图5是表示铝的连接焊盘19、22和金线的接合强度、与铜电极和金线的接合强度进行比较的图表，铝-金连接相对于铜-金连接，提高了5％左右的接合强度。
如以上说明，在实施例1的半导体器件10中，在铝电极11之上层叠铜电极12的层叠电极13的一部分，设置使铝电极11露出的连接焊盘19、22，因此，可以以充分的强度连接至少表面由不包含铜为主的材料构成的连接导体。其结果，可得到充分的连接可靠性，可提供可靠性高的半导体器件。
在此，说明了通过无电解电镀法形成铜电极12的情况，但只要在可以得到目标厚度的范围内，也可以是其它方法例如真空蒸镀法或溅射法等。该情况下，也可以没有镍中间层。
此外，说明了将源电极S和栅电极G一起作为层叠电极13的情况，但只要是在栅极几乎没有电流流过而对动作不产生妨碍的范围内，可以是层叠电极13以外的电极，例如只有铝电极11。
实施例2
图6是表示本发明的实施例2的半导体器件的结构的图。图6A是其外围器的一部分欠缺的俯视图。图6B是沿着图6A的D-D线截断并向箭头的方向看的截面图。在本实施例中，与上述实施例1相同的结构部分赋予相同符号并省略其说明，仅说明不同的部分。
本实施例与实施例1不同点在于，集成了两个功率MOS晶体管的半导体芯片被收容在小外型封装(SOP)中，该功率MOS晶体管具有层叠铝电极和铜电极的层叠电极。
即，如图6所示，本实施方式的配置在半导体器件40内的半导体芯片41，在半导体芯片41的表面的中央部具有相对配置的角部欠缺的梳齿状的源电极S1、S2，在外周部具有分别包围源电极S1、S2的框形的栅电极G1、G2，以及在整个背面具有公共的漏电极D(未图示)。源电极S1和S2形成有在梳齿状的根部使铝电极11露出的连接焊盘42和43，相同地，在栅电极G1、G2上源电极S1和S2的角部欠缺的区域形成有连接焊盘44、45。
半导体芯片41在进行了镀镍或锡的铜制的引脚框46上向下载置有漏电极D。漏电极D由导电性粘接剂固定在引脚框46的岛部46a，与多个引脚端子47、48连接。
源电极S1通过多个连接导体49例如金线与多个引脚端子50连接。即，多个连接导体49的一端部49a与使源电极S1的铝电极11露出的连接焊盘42连接，多个连接导体49的另一端49b与多个引脚端子50连接。
栅电极G1通过连接导体51与引脚端子52连接。即，将连接导体51的一端部与在栅电极G1的一端部使铝电极11露出的连接焊盘44连接，连接导体51的另一端部与引脚端子52连接。同样地，源电极S2通过多个连接导体53与多个引脚端子54连接，栅电极G2通过连接导体55与引脚端子56连接。用树脂57塑封这些整体，构成了SOP型的半导体器件40。
因此，在层叠铝电极11和铜电极12的层叠电极13的一部分，设置铝电极11露出的连接焊盘42～45，由此可以以充分的强度将连接导体与层叠电极13接合。
如以上说明，在实施例2的半导体器件40中，在集成了两个功率MOS晶体管的半导体芯片41上，设置了层叠有铝电极11和铜电极12的层叠电极13的铝电极11露出的连接焊盘42～45，因此，可提供具有充分的连接强度的小型的半导体器件。
实施例3
图7是表示本发明的实施例3的半导体器件的结构的图。图7A是其外围器的一部分欠缺的俯视图。图7B是沿着图7A的E-E线截断并向箭头的方向看的截面图。图7C是将图7B的主要部分放大的截面图。
在本实施例中，对与上述实施例1相同的结构部分赋予相同符号并省略其说明，仅说明不同的部分。
本实施例与实施例1不同点在于，在集成了具有层叠了Al电极和Cu电极的层叠电极的两个功率MOS晶体管的半导体芯片的、铝电极露出的连接焊盘上形成金属凸块，倒装连接到引脚框上。
即，如图7所示，本实施方式的半导体器件70的半导体芯片71在源电极S1的连接焊盘42上具有金属凸块72，以及在源电极S2的连接焊盘43上具有金属凸块(未图示)。同样地，栅电极G1的连接焊盘44上具有金属凸块73，以及在栅电极G2的连接焊盘45上具有金属凸块(未图示)。金属凸块72、73例如为金凸块。金凸块使用压焊(bonding)装置，在劈刀(capillary)前端形成金线的球，一边加热该金球一边施加超声波，在铝的连接焊盘上进行压焊。并且，可以通过压坏该连接焊盘上的金球形成金凸块的柱型凸块(stud bump)法形成。
在进行了镀镍或锡的铜制的引脚框74上，将源电极S1、S2及栅电极G1、G2向下来载置半导体芯片71。源电极S1通过多个金属凸块72与引脚端子75倒装连接，栅电极G1通过金凸块73与引脚端子76倒装连接。
同样地，源电极S2通过多个金凸块(未图示)与引脚端子77倒装连接，栅电极G1通过金凸块(未图示)与引脚端子78倒装连接。并且，用树脂79塑封这些整体，构成了SOP型的半导体器件70。
因此，在层叠了铝电极11和铜电极12的层叠电极13的一部分，在铝电极11露出的连接焊盘上设置金属凸块，由此，能以充分的强度将层叠电极13与引脚框倒装片接合。
如以上说明，在实施例3的半导体器件70中，在集成了两个功率MOS晶体管的半导体芯片71上的、层叠了铝电极11和铜电极12的层叠电极13的铝电极11露出的连接焊盘上，形成金属凸块72、73，并与引脚框74倒装片连接，因此，可提供具有充分的连接强度的小型的半导体器件。
对于本领域技术人员而言，依据对这里公开的说明书和本发明的实现方式的考虑，本发明的其它实施例是显而易见的。说明书和例示性的实施例趋向于被视为示例性的，而本发明的范围和主旨由随后的权利要求指明。在不偏离本发明要旨的范围内可对本发明进行各种修改。
在此，说明了与引脚框倒装片连接的情况，但也可以倒装连接在印制布线基板的连接焊盘上。此外，印制布线基板的连接焊盘也可以是铝布线和铜布线层叠的层叠布线的铝布线露出的连接焊盘。

Claims (18)

1.一种半导体器件，其特征在于具有：
引脚框；
与主面相反面侧被载置于所述引脚框上的半导体芯片；
在所述半导体芯片的主面形成的、以铝为主成分的第一电极；
一端部与所述第一电极连接，另一端部与所述引脚框的引脚端子连接的布线；以及
在所述第一电极上至少除了连接有所述布线的一端部的区域以外选择性地形成的、以铜为主成分的第二电极。
2.如权利要求1所述的半导体器件，其中，将由所述第一电极和形成在所述第一电极上的所述第二电极构成的层叠电极的所述第一电极露出的区域作为连接焊盘。
3.如权利要求1所述的半导体器件，其中，所述布线以铝或金为主成分。
4.如权利要求1所述的半导体器件，其中，在所述第一电极和所述第二电极之间，还具有以镍为主成分的中间层。
5.如权利要求1所述的半导体器件，其中，在所述引脚框上载置有多个所述半导体芯片。
6.如权利要求1所述的半导体器件，其中，所述半导体芯片具有功率半导体。
7.如权利要求6所述的半导体器件，其中，在所述半导体芯片的主面形成有所述功率半导体的栅电极及漏电极。
8.一种半导体器件，其特征在于包括：
引脚框；
主面侧被载置于所述引脚框上的半导体芯片；
在所述半导体芯片的主面形成的、以铝为主成分的第一电极；
一端部与所述第一电极连接，另一端部与所述引脚框的引脚端子连接的突起状的布线；以及
在所述第一电极上至少除了连接有所述一端部的区域以外选择性地形成的、以铜为主成分的第二电极。
9.如权利要求8所述的半导体器件，其中，将由所述第一电极和形成在所述第一电极上的所述第二电极构成的层叠电极的第一电极露出的区域作为连接焊盘。
10.如权利要求8所述的半导体器件，其中，所述突起状的布线以铝或金为主成分。
11.如权利要求8所述的半导体器件，其中，在所述第一电极和所述第二电极之间，还具有以镍为主成分的中间层。
12.如权利要求8所述的半导体器件，其中，在所述引脚框上载置有多个所述半导体芯片。
13.如权利要求8所述的半导体器件，其中，所述半导体芯片具有功率半导体。
14.如权利要求13所述的半导体器件，在所述半导体芯片的主面形成有所述功率半导体的栅电极和漏电极。
15.一种半导体器件的制造方法，其特征在于包括以下工序：
准备半导体芯片；
在所述半导体芯片上形成以铝为主成分的第一电极；
在所述第一电极上选择性地形成掩蔽膜，
将所述掩蔽膜作为掩膜，在第一电极上形成以铜为主成分的第二电极；
去除所述掩蔽膜；
在引脚框上固定所述半导体芯片；
将连接导体的一端部与被去除所述掩蔽膜且露出所述第一电极表面的连接焊盘连接；以及
将所述连接导体的另一端部与所述引脚框内的引脚端子连接。
16.如权利要求15所述的半导体器件的制造方法，还包括：在所述第一电极和所述第二电极之间形成金属中间层的工序。
17.如权利要求15所述的半导体器件的制造方法，其中，通过无电解电镀法形成所述第二电极。
18.如权利要求15所述的半导体器件的制造方法，其中，所述连接导体具有突起状的形状。
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