CN1043828A - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
- Publication number
- CN1043828A CN1043828A CN90100191A CN90100191A CN1043828A CN 1043828 A CN1043828 A CN 1043828A CN 90100191 A CN90100191 A CN 90100191A CN 90100191 A CN90100191 A CN 90100191A CN 1043828 A CN1043828 A CN 1043828A
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- Prior art keywords
- chip
- lead
- lead portion
- wire
- inner lead
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 25
- 229920005989 resin Polymers 0.000 claims abstract description 25
- 238000002360 preparation method Methods 0.000 claims abstract description 5
- 238000003466 welding Methods 0.000 claims description 36
- 229920001721 polyimide Polymers 0.000 claims description 7
- 229920002379 silicone rubber Polymers 0.000 claims description 4
- 239000011368 organic material Substances 0.000 claims 2
- 238000007789 sealing Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 18
- 238000004382 potting Methods 0.000 abstract description 14
- 241000446313 Lamella Species 0.000 description 38
- 230000000694 effects Effects 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- 238000007747 plating Methods 0.000 description 7
- 230000005260 alpha ray Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005381 potential energy Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002659 electrodeposit Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 210000003041 ligament Anatomy 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
一种半导体器件的制造方法,制备一包含多根引线的引线框架,使其内引线部分在芯片的电路形成面上延伸(在内引线部分与电路形成面之间固定有绝缘片),或使内引线部分在芯片主要非电路形成面上延伸,从而延长内引线在芯片之上或其附近的长度来改进树脂封装半导体器件中引线与封装树脂间的粘结力,而提高半导体器件的可靠性。
Description
本发明是关于一种半导体器件的制造方法,更具体地说是关于能有效应用于树脂封装式半导体器件的连接技术。
图8为普通引线框架的平面图,该引线框架用于普通树脂封装式半导体器件,特别是树脂封装型64 KSRAM大规模集成电路的生产中。图中,数码100表示框架,101为外引线,102为内引线,103为连接杆,104为台面,105为台面的引线。
在树脂封装式半导体器件生产中有这样一种趋势,即管壳边缘与固定芯片的台面之间的距离随着芯片尺寸增大的趋势而变得越来越窄。其原因是由于对于芯片来说,管壳的尺寸是标准化了的,尽管芯片的尺寸在增大,管壳的尺寸却不能变大。
因此,可以预料这必然会大大降低所谓短引线的粘着性,因为在结构上,作为外电极的这些导线埋在构成管壳的树脂中的那部分长度较短,所以引线很容易脱落,而且在引线弯曲过程中,引线与树脂之间很易产生剥离。
本发明的发明人发现这可能导致低劣的电接触、降低抗湿性等,从而降低半导体器件的可靠性。
1980年1月15日,株式会社工业调查会发行、日本微电子学协会编写的《集成电路安装技术》一书的149-150页上对树脂封装式半导体器件作了描述。
本发明的目的是提供一种改进的半导体器件的制造方法,特别是安装大芯片的半导体器件的制造方法。
本发明的目的以及新颖特征将由下面的说明及附图表达清楚。
确切地说,本发明是这样来改善内引线与构成管壳的树脂间的粘结力的,即,在树脂封装的半导体器件中使引线延伸到待安装芯片的电路形成面上或其附近,或者延伸到此芯片主要的非电路形成面上或其附近,这样就能使引线的内引线部分延长。
图1为沿图2中Ⅰ-Ⅰ线的剖面图,它表示用本发明的实施例1的方法制造的半导体器件;
图2为表示实施例1的半导体器件的芯片与引线关系的平面图;
图3为实施例1的方法中所用引线框架的部分平面图,它表示了电渡过程中框架的状态;
图4为表示用本发明的实施例2的方法制造的半导体器件的芯片与引线关系的平面图;
图5为沿图4中Ⅴ-Ⅴ线的部分剖面图,它表示出实施例2的半导体器件的内部结构;
图6为沿图7Ⅵ-Ⅵ线的剖面图,图7表示用本发明的实施例3的方法制造的半导体器件;
图7为表示实施例3的半导体器件的芯片与引线间关系的平面图;
图8为普通树脂封装的半导体器件生产中所用的引线框架的平面图。
〔实施例1〕
图1为沿图2中Ⅰ-Ⅰ线的剖面图,它为用本发明实施例1的方法制造的半导体器件。图2为表示实施例1的芯片与引线关系的平面图。
实施例1的半导体器件是一个所谓的树脂封装式半导体器件。即,半导体芯片1与起外引线作用的引线2的内引线部分一起埋在构成管壳3的树脂当中,如环氧树脂(以下称为“封装树脂”),引线2在管壳外面的外部引线在靠近管壳3的边上向下弯曲。
在普通的树脂封装式半导体器件中,芯片与一个起安装板作用的台面相接触,台面的尺寸实质上与芯片相同,而起芯片电极作用的压焊块则通过起压焊线作用的细金属丝与布置在台面外围的引线的内端部分形成电连接。
而在实施例1的半导体器件中,引线延伸到芯片1的背面(即不形成半导体集成电路的主要非电路形成面)。芯片靠粘结剂6与聚酰亚胺树脂的绝缘薄片5相连,该薄片与这些引线粘连在一起。在这种情况下,引线框架上没有安装芯片用的台面。绝缘薄片使引线之间达到电绝缘。在本实施例中,如果没有绝缘薄片5,引线之间就会通过导电的芯片1产生短路。为了避免短路,在芯片1和引线之间放置了该绝缘薄片5。
如图2所示,上述芯片1与引线2的位置关系是这样的,引线2a的外引线沿芯片1上不准备形成压焊块7的两边(以下,称“无压焊块形成边”)排列,引线2a的内引线在该芯片1的背面(主要的非电路形成面)延伸,而其端部2b则一直从该芯片打算形成压焊块7的边上延伸出来。绝缘薄片5粘接到引线2a上,芯片1用其为主要非电路形成面的下表面与绝缘薄片5的上表面相接。
在普通的树脂封装式半导体器件中,具有在芯片1下面延伸的内引线的引线2a被封装树脂埋置的地方只有从管芯边缘到台面附近的非常有限的长度,只能提供很短的引线。
普通的短引线通常有一个问题,即由于与封装树脂只有很小的粘接面积,其抗拉强度较低,所以引线容易从管壳上脱落。由于短引线和封装树脂间的粘接面积随着芯片尺寸的增大而减少,因此,这个问题随着芯片尺寸的增大变得严重起来。
相反,在实施例1的半导体器件中与上述短引线相应位置上提供的内引线很长,因此引线2a与封装树脂的粘接面积很大。这样,引线和封装树脂间的粘接强度能得到大的改进。因此,即使在用大芯片的半导体器件中,也能有效地防止引线和封装树脂之间交界面处的剥离(这种剥离可能在进行弯折外引线或类似的工作时发生),这样,可以避免水从外面通过剥离部分侵入封装树脂中的芯片。因此能改善半导体器件的抗湿性。而且,由于绝缘薄片5与引线2a粘得很牢,引线2a就有很高的抗拉强度。
此外,因为热导率与散热能力比封装树脂高的金属引线2a在芯片1表面的很大范围上与之接触,尽管接触是通过绝缘薄片5进行的,芯片在工作状态时产生的热能也能够通过引线直接向外散发。因此,用本发明的方法制造的半导体器件具有散热能力很好的结构。
除此之外,由于芯片1与引线2a的电连接是靠把芯片上的压焊块7a与分布在压焊块附近并靠近芯片边缘的导线2a端部2b用导线焊接在一起而达到的,所以压焊线8可以弄得很短。因此,可以防止互相贴近的压焊线之间、压焊线与邻近的引线之间或压焊线与芯片之间的偶然接触。换句话说,可以防止短路故障。再则,由于压焊线短而减少了压焊线8的总量,因此降低了成本。
实施例1中的半导体器件是易于制造的,其方法是:做一个预先确定好形状的引线框架,把绝缘薄片5粘接在引线的内引线预定部位,用粘合剂把芯片1粘在绝缘薄片5上,把芯片1的压焊块与引线的键合部分用压焊线连结起来,再用与普通树脂封装式半导体器件生产中相同的步骤装配。在这种情况下,绝缘薄片5不仅起到防止引线间偶然短路的绝缘体的作用,而且起到在机械强度上加强引线框架的作用。
上述引线的导线键合部分可以用,例如,局部电镀方法淀积金来形成。
图3是带有绝缘薄片5的引线框架的局部平面图,薄片5事实上粘结在连接杆9以内的部分。图中没有画出的引线框架部分,如,框架部分和外引线部分,其形状与图8所示的那些部分相似。在用实施例1的方法制造的半导体器件中,由于绝缘薄片本身起着局部电镀掩模的作用,所以只使用一块带有一个窗口(如图3中带点部分所示)的局部电镀掩模,就能够用有良好导线键合能力的材料(如金)只在引线2的端部2b处进行选择性局部电镀。从而简化了掩模制备方法,使键合部分的形成容易实现。
图3中,只示出沿芯片短边提供间隙的掩模。但是,使用具有沿平行于连接杆9的芯片长边提供间隙的窗口的掩模就能够容易地在所有围绕绝缘薄片5的引线上进行局部电镀。用这种方法,能够容易地制备芯片周围都具有压焊块的半导体器件。
〔实施例2〕
图4是表明用本发明另一个实施例的方法制造的半导体器件中芯片与引线关系的平面图。
实施例2中的半导体器件与实施例1中的不同,它没有绝缘薄片5,但采用了一个比芯片1小的台面。
准确地说,在实施例2的半导体器件中,芯片1用绝缘材料制成的粘合剂11粘在台面和引线2a的内引线上,引线2a的外引线沿着芯片的无压焊块的边排列。可用的绝缘材料粘合剂包括聚酰亚胺树脂、硅橡胶以及陶瓷。
在实施例2中,由于没有绝缘薄片5,热能够从芯片1直接散发出去。因此与实施例1相比,热阻又有所降低,因而可靠性相应地更高。
此外,由于加上了台面10,芯片的连接强度也有了保障。
图5为沿图4Ⅴ-Ⅴ面的局部剖面图,它表示出芯片1与引线2的尖端部分的电连接状态。在引线2a的尖端部分2b上做出一个凹槽2c。在用粘合剂粘连芯片1时,由于粘合剂11可能流出来弄脏键合部分12的表面,有时用导线8不能完成芯片1的压焊块7和键合部分12之间的连接。上述凹槽2c用作阻断粘合剂11流动的屏障,以避免发生键合失效。
〔实施例3〕
图6为用本发明又一个实施例的方法制造的半导体器件的剖面图图。图7为表示上述半导体器件中芯片与引线关系的平面图。
本实施例的半导体器件与实施例1与2中的器件不同在于,内引线是在芯片的电路形成面上面延伸的。
特别是,如图6所示,芯片1借助于电路形成面上的粘合剂6连接到聚酰亚胺树脂绝缘薄片5上,该薄片5粘接在内引线的背面。在这种情况下,绝缘薄片5起到防止引线间发生偶然短路的绝缘体作用。除此之外,绝缘薄片5还起到增强引线在那里的机械强度的作用。
如图7所示,绝缘薄片5的大小不能盖过与之粘接的芯片1上的压焊块。引线2a的外引线沿芯片无压焊块的边分布,其内引线在绝缘薄片的上表面延伸。引线2a的内引线粘连在上述绝缘薄片5上,其端部置于压焊块的附近。
由于本实施例中的半导体器件具有焊接在芯片1的电路形成面一侧的内引线,所以它的散热能力比实施例1中的器件要优越。
聚酰亚胺绝缘薄片5用于防止半导体器件在受到外来α射线照射时失效。也就是说,绝缘薄片5起到阻止α射线从外面侵入该器件的作用。由于绝缘薄片覆盖在电路形成面上,也就使在α射线条件下工作的可靠性得到了改善。
在具有保护芯片1之电路形成面上布线和电路的钝化绝缘薄膜的半导体器件中,可能不太需要防止引线间短路的绝缘薄片,或者不仅可以用绝缘材料也可以用导电材料作为粘接芯片与引线的粘接剂。
在实施例3中,引线2a的端部放置在靠近压焊块7的内部位置上,它们之间的位置关系和实施例1中的情况相反。因此,焊接方向也相反。不过,焊接距离基本上与实施例1相同。
本发明的功效如下。
(1)、在树脂封装式半导体器件中,内引线在安放于器件内的芯片的电路形成面上或在其附近,或者在该芯片的主要非电路形成面上或在其附近延伸,能够大大改善内引线与封装树脂的粘接力。因此,即使安放大的芯片,也能防止引线从封装树脂中脱落。
在本发明中,至少有一根引线在芯片上面或下面延伸。结果,大大改善了内引线与封装树脂的粘接力。因此,即使安放大的芯片,也能防止引线从封装树脂中脱落。
(2)、能防止在进行外引线弯折时发生引线与封装树脂间粘接面的剥离。
(3)、即使半导体器件的管壳很小,其中安放的芯片很大,也能提供抗湿性很好的高可靠性半导体器件。
(4)、当内引线固定在芯片的主要非电路形成面上时,工作状态下产生的热量能通过这些引线有效地向外散发。
(5)、当在上述(4)所述的器件中在芯片与内引线间安放一绝缘薄片时,能够改善芯片的连接强度。
(6)制备一个在预定部位粘有绝缘薄片的引线框架并把芯片固定在绝缘薄片上,就能容易地形成(5)中所述结构。
(7)、由于通过把绝缘薄片粘接在引线框架的预定部位能加固引线,所以即使框架含有大量的细引线,引线框架也很容易加工。
(8)、由于引线框架具有粘连在预定部位上的绝缘薄片,而且局部电镀掩模具有一个其大小可为绝缘薄片四周或局部提供空隙的窗口,由于绝缘薄片也起到局部电镀掩模的作用,故这些技术的组合使相应于上述空隙的导线部位能容易地受到局部电镀。
(9)、内引线固定在芯片的电路形成面上,使电路在工作状态时产生的热量能更直接地通过引线散发出去。
(10)、在内引线和芯片之间提供用于阻止α射线对半导体元件辐射的绝缘薄片能保护半导体元件和包含这一元件的电路免受α射线的辐射。因此能改善半导体器件抗α射线的可靠性。
(11)、在固定于芯片电路形成面或非电路形成面上的引线的靠近芯片安放部分地方提供凹槽或凸起,能防止用来把引线粘在芯片或与芯片连接的绝缘薄片上的粘合剂流出来沾污键合部分的表面。因此,能防止发生低劣的导线键合。
上面已用实施例对本发明作了具体说明。不过,本发明并不只局限于上述实施例,无需多说,本发明能够在不偏离本发明主要方法的范围内产生各种各样的变换型式。
例如,所有实施例谈到的情况都是内引线直接或间接固定在芯片的主表面上。不过,本发明并不只限于这种情况、全部或部分内引线可以在电路形成面或主要非电路形成面附近延伸。
所有实施例涉及的情况中引线只在与所谓短引线位置相应的芯片一侧延伸。然而,本发明不只限于这种情况,它还包括具有长的内引线的引线在普通半导体器件中延伸的情况。绝缘薄片不只限于聚酰亚胺一种,还可以是一种硅橡胶。当然,还可以把象碳化硅(SiC)粉这样的填料加进粘合剂和/或绝缘薄片,以便改进散热能力。
在实施例1和3中,可以不一定使用绝缘薄片。相反,实施例2可以用绝缘薄片。
防止引线粘合剂象实施例2中所说的那样外流的屏障也不只限于凹槽,还可以用突起部分达到屏障的作用。这种屏障当然也可以在实施例1和3中使用。
以上的说明主要涉及到本发明应用于所谓DIP(双列直插塑料)式半导体器件,这种器件与作为本发明背景的应用领域有关。不过,本发明不只限于这种器件。本发明的技术能有效地应用于具有各种形式的管壳结构的半导体器件,例如扁平管壳结构,只要管壳是用树脂封装的。
Claims (4)
1、一种半导体器件的制造方法,包括下列步骤:
(1)制备一包含多根引线的引线框架,每根引线均有一个内引线部分和一个外引线部分;
(2)把一绝缘片固定在所述引线的一个或几个内引线部分上一
(3)将一其上具有多个压焊块的芯片固定在所述绝缘片上;
(4)用压焊线使所述内引线部分和相应的压焊块之间实现电连接;
(5)把所述芯片、所述内引线部分和所述压焊线密封在树脂内。
2、如权利要求1所述的半导体器件的制造方法,其中,所述绝缘片至少是由硅橡胶、聚酰亚胺薄膜或有机材料中的一种制成的。
3、一种制造半导体器件的工艺过程,包括下列步骤:
(1)制备一包含多根引线的引线框架,每根引线均有一个内引线部分和一个端部,这些内引线部分基本在一个平面内延伸并分成第一、第二、第三和第四组,各组均有多根内引线部分;
(2)把一绝缘片固定在所述引线的内引线部分上;
(3)将一矩形半导体芯片固定在所述绝缘片上,所述芯片上至少有一个电子器件和多个压焊块,该芯片有第一、第二、第三和第四侧边;
(4)用压焊线使所述内引线部分和相应的压焊块实现电连接;
(5)将所述芯片、内引线部分和压焊线密封在树脂内;
其中,所述第一组内引线部分至少和所述芯片的第一侧边相交,且其端部延伸到靠近所述芯片的第三侧边排列的压焊块附近;
所述第二组内引线部分至少和所述芯片的第一侧边相交,且其端部延伸到靠近所述芯片的第四侧边排列的压焊块附近,
所述第三组内引线部分至少和所述芯片的第二侧边相交,且其端部延伸到靠近所述芯片的第三侧边排列的压焊块附近。
所述第四组内引线部分至少和所述芯片的第二侧边相交,且其端部延伸到靠近所述芯片的第四侧边排列的压焊块附近。
4、如权利要求3所述的制造半导体器件的工艺过程,其中,所述绝缘片至少是由硅橡胶、聚酰亚胺薄膜或有机材料中的一种制成的。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5840785A JPH06105721B2 (ja) | 1985-03-25 | 1985-03-25 | 半導体装置 |
JP58407/85 | 1985-03-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1043828A true CN1043828A (zh) | 1990-07-11 |
Family
ID=13083507
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN90100191A Pending CN1043828A (zh) | 1985-03-25 | 1986-03-19 | 半导体器件的制造方法 |
CN198686101795A Pending CN86101795A (zh) | 1985-03-25 | 1986-03-19 | 半导体器件及其生产方法,以及上述工艺所用的引线框架 |
CN96106214A Pending CN1147151A (zh) | 1985-03-25 | 1996-05-08 | 半导体器件及其制造方法,以及上述工艺所用的引线框架 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN198686101795A Pending CN86101795A (zh) | 1985-03-25 | 1986-03-19 | 半导体器件及其生产方法,以及上述工艺所用的引线框架 |
CN96106214A Pending CN1147151A (zh) | 1985-03-25 | 1996-05-08 | 半导体器件及其制造方法,以及上述工艺所用的引线框架 |
Country Status (4)
Country | Link |
---|---|
US (2) | US4943843A (zh) |
JP (1) | JPH06105721B2 (zh) |
KR (1) | KR940010546B1 (zh) |
CN (3) | CN1043828A (zh) |
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-
1986
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- 1986-03-19 CN CN90100191A patent/CN1043828A/zh active Pending
- 1986-03-19 CN CN198686101795A patent/CN86101795A/zh active Pending
-
1989
- 1989-12-08 US US07/445,942 patent/US4943843A/en not_active Expired - Lifetime
-
1990
- 1990-05-29 US US07/529,448 patent/US5126821A/en not_active Expired - Lifetime
-
1996
- 1996-05-08 CN CN96106214A patent/CN1147151A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
KR940010546B1 (ko) | 1994-10-24 |
CN1147151A (zh) | 1997-04-09 |
CN86101795A (zh) | 1986-09-24 |
KR860007735A (ko) | 1986-10-17 |
US4943843A (en) | 1990-07-24 |
JPH06105721B2 (ja) | 1994-12-21 |
US5126821A (en) | 1992-06-30 |
JPS61218139A (ja) | 1986-09-27 |
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