JP2007129182A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2007129182A JP2007129182A JP2006115959A JP2006115959A JP2007129182A JP 2007129182 A JP2007129182 A JP 2007129182A JP 2006115959 A JP2006115959 A JP 2006115959A JP 2006115959 A JP2006115959 A JP 2006115959A JP 2007129182 A JP2007129182 A JP 2007129182A
- Authority
- JP
- Japan
- Prior art keywords
- group
- chip
- lead
- resin
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01002—Helium [He]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01037—Rubidium [Rb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
【解決手段】たとえば、ボンディングパッド群が一辺に設けられたチップ10をリードフレーム11上に搭載し、樹脂15で封止した半導体パッケージ装置において、リードフレーム11は一対の内部リード群11a,11bを有し、チップ10は裏面の有機系絶縁膜12を介して、長い方の内部リード11b群および吊りピン部11f上に搭載されている。吊りピン部11fは、長い方の内部リード11bの、最も外側の内部リードに接続されるとともに、チップ10の裏面に固着されて、チップ10を安定にホールドする構成となっている。
【選択図】 図3
Description
図1乃至図3は、本発明の第1の実施形態にしたがったTSOP構造の半導体装置(半導体パッケージ装置)の基本構成を示すものである。なお、図1は半導体パッケージ装置の断面図であり、図2は半導体パッケージ装置の内部を該装置の裏面側より透過して示す平面(下面)図であり、図3は半導体パッケージ装置の内部を該装置の表面側より透過して示す平面(上面)図である。
図6は、本発明の第1の実施形態にしたがった半導体パッケージ装置に適用される、リードフレームの一例を具体的に示すものである。ここでは、半導体パッケージ装置を、メモリ集積回路装置、たとえばNAND型フラッシュメモリとした場合について説明する。なお、図6には、第1の実施形態で示したリードフレーム11の内部リード11a,11b群の左右の位置関係を反転させたリードフレーム11Aを例に示している。また、図中に示すVCC,VSS,I/O−0〜I/O−7,RB,RE,CE,CLE,ALE,WE,WPは、対応する外部端子の一例である。ちなみに、図中にN.Cで示す内部リードは未使用(非接触)となっている。
図7は、本発明の第1の実施形態にしたがった半導体パッケージ装置に適用される、リードフレームの他の一例を具体的に示すものである。ここでは、半導体パッケージ装置を、メモリ集積回路装置、たとえばNAND型フラッシュメモリとした場合について説明する。なお、図7には、第1の実施形態で示したリードフレーム11の内部リード11a,11b群の左右の位置関係を反転させたリードフレーム11Bを例に示している。また、図中に示すVCC,VSS,I/O−0〜I/O−7,RB,RE,CE,CLE,ALE,WE,WPは、対応する外部端子の一例である。ちなみに、図中にN.Cで示す内部リードは未使用(非接触)となっている。
図9は、本発明の第2の実施形態にしたがったTSOP構造の半導体装置(半導体パッケージ装置)の構成を示すものである。図9は、半導体パッケージ装置の内部を表面側より透過して示す平面(上面)図であり、第1の実施形態に示した半導体パッケージ装置と同一部分には同一符号を付し、詳しい説明は割愛する。
図10は、本発明の第3の実施形態にしたがったTSOP構造の半導体装置(半導体パッケージ装置)の構成を示すものである。
図11および図12(a),(b)は、本発明の第4の実施形態にしたがったTSOP構造の半導体装置(半導体パッケージ装置)の構成を示すものである。ここでは、半導体パッケージ装置を、メモリ集積回路装置、たとえばNAND型フラッシュメモリとした場合について説明する。なお、図11は半導体パッケージ装置の内部を透過して示す平面(上面)図であり、図12(a)は半導体パッケージ装置の外部リードの突出方向に沿う、内部リードの先端部付近の断面図であり、図12(b)は半導体パッケージ装置の外部リードの突出方向と直交する方向に沿う、吊りピン部付近の断面図である。
図14は、本発明の第5の実施形態にしたがったTSOP構造の半導体装置(半導体パッケージ装置)の構成を示すものである。図14は、半導体パッケージ装置の内部を表面側より透過して示す平面(上面)図であり、第4の実施形態に示した半導体パッケージ装置と同一部分には同一符号を付し、詳しい説明は割愛する。
図15(a),(b)は、本発明の第6の実施形態にしたがったTSOP構造の半導体装置(半導体パッケージ装置)の構成を示すものである。図15(a)は半導体パッケージ装置の外部リードの突出方向に沿う、内部リードの先端部付近の断面図であり、図15(b)は半導体パッケージ装置の外部リードの突出方向と直交する方向に沿う、吊りピン部付近の断面図である。
図16および図17は、本発明の第7の実施形態にしたがったTSOP構造の半導体装置(半導体パッケージ装置)の構成を示すものである。ここでは、半導体パッケージ装置を、メモリ集積回路装置、たとえばNAND型フラッシュメモリとした場合について説明する。なお、図16は半導体パッケージ装置の内部を透過して示す平面(下面)図であり、図17は半導体パッケージ装置の外部リードの突出方向に沿う、内部リードの先端部付近の断面図である。
図19は、本発明の第8の実施形態にしたがったTSOP構造の半導体装置(半導体パッケージ装置)の構成を示すものである。図19は半導体パッケージ装置の外部リードの突出方向に沿う、内部リードの先端部付近の断面図である。なお、この半導体パッケージ装置は、その上面から透過した図が、図16の下面図とほぼ等価なものとなっている。
Claims (5)
- 素子形成面側のチップ一辺に沿って配置されたボンディングパッド群を有する半導体チップと、
各先端部が前記半導体チップの前記ボンディングパッド群の一部と対向するように配置された第1の内部リード群、および、前記半導体チップの非素子形成面側が固着されるチップ搭載部を有し、各先端部が前記第1の内部リード群の各先端部と前記半導体チップとの間に位置するように配置された第2の内部リード群を含むリードフレームと、
前記第1の内部リード群と前記ボンディングパッド群の一部のボンディングパッドとを接続する第1のボンディングワイヤ群と、
前記第2の内部リード群の先端部と前記ボンディングパッド群の一部のボンディングパッドとを接続する第2のボンディングワイヤ群と、
前記半導体チップの非素子形成面に固着された吊りピン部と、
前記吊りピン部、および、前記第1,第2の内部リード群と前記第1,第2のボンディングワイヤ群との接続部を含んで、前記半導体チップの周囲を封止する樹脂パッケージと
を具備したことを特徴とする半導体装置。 - 前記吊りピン部は、さらに、前記リードフレームの一部に接続されていることを特徴とする請求項1に記載の半導体装置。
- 前記吊りピン部は、前記リードフレームをフレーム本体に支持するための支持部材であることを特徴とする請求項1または2に記載の半導体装置。
- 前記リードフレームは、前記第1,第2の内部リード群にそれぞれ連なる第1,第2の外部リード群を有し、
前記第1,第2の外部リード群は、それぞれ、前記樹脂パッケージの少なくとも対向する一対の辺から外部へ突出し、かつ、前記チップ搭載部の方向へ折り曲げられていることを特徴とする請求項1に記載の半導体装置。 - 前記半導体チップは、その素子形成面側が下向きとなるフェイスダウンの状態で、前記樹脂パッケージにて形成されていることを特徴とする請求項1に記載の半導体装置。
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006115959A JP2007129182A (ja) | 2005-05-11 | 2006-04-19 | 半導体装置 |
KR1020060041841A KR100810324B1 (ko) | 2005-05-11 | 2006-05-10 | 반도체 칩의 주위를 밀봉하여 이루어지는 반도체 장치 |
US11/430,965 US7919837B2 (en) | 2005-05-11 | 2006-05-10 | Semiconductor device with sealed semiconductor chip |
CNB2006100817751A CN100440498C (zh) | 2005-05-11 | 2006-05-11 | 密封了半导体芯片周围而形成的半导体器件 |
US13/029,466 US8970019B2 (en) | 2005-05-11 | 2011-02-17 | Semiconductor device with sealed semiconductor chip |
US14/617,637 US10366942B2 (en) | 2005-05-11 | 2015-02-09 | Semiconductor device with sealed semiconductor chip |
US16/438,826 US10872844B2 (en) | 2005-05-11 | 2019-06-12 | Semiconductor device with sealed semiconductor chip |
US16/952,968 US11424176B2 (en) | 2005-05-11 | 2020-11-19 | Semiconductor device with sealed semiconductor chip |
US17/864,064 US11854946B2 (en) | 2005-05-11 | 2022-07-13 | Semiconductor device with sealed semiconductor chip |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005138718 | 2005-05-11 | ||
JP2005291391 | 2005-10-04 | ||
JP2006115959A JP2007129182A (ja) | 2005-05-11 | 2006-04-19 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012285961A Division JP5619128B2 (ja) | 2005-05-11 | 2012-12-27 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007129182A true JP2007129182A (ja) | 2007-05-24 |
Family
ID=37418342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006115959A Pending JP2007129182A (ja) | 2005-05-11 | 2006-04-19 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (6) | US7919837B2 (ja) |
JP (1) | JP2007129182A (ja) |
KR (1) | KR100810324B1 (ja) |
CN (1) | CN100440498C (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100920052B1 (ko) | 2008-01-02 | 2009-10-07 | 주식회사 하이닉스반도체 | 반도체 패키지용 리드 프레임 |
JP2010182873A (ja) * | 2009-02-05 | 2010-08-19 | Toshiba Corp | 半導体デバイス |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7368320B2 (en) * | 2003-08-29 | 2008-05-06 | Micron Technology, Inc. | Method of fabricating a two die semiconductor assembly |
JP2007129182A (ja) * | 2005-05-11 | 2007-05-24 | Toshiba Corp | 半導体装置 |
US20080054496A1 (en) * | 2006-08-30 | 2008-03-06 | Neill Thornton | High temperature operating package and circuit design |
JP2008294384A (ja) * | 2007-04-27 | 2008-12-04 | Renesas Technology Corp | 半導体装置 |
US7863102B2 (en) * | 2008-02-22 | 2011-01-04 | Stats Chippac Ltd. | Integrated circuit package system with external interconnects within a die platform |
JP5536388B2 (ja) * | 2009-08-06 | 2014-07-02 | 株式会社テラプローブ | 半導体装置およびその製造方法 |
US9679831B2 (en) | 2015-08-13 | 2017-06-13 | Cypress Semiconductor Corporation | Tape chip on lead using paste die attach material |
JP2018110169A (ja) * | 2016-12-28 | 2018-07-12 | 富士電機株式会社 | 半導体装置および半導体装置製造方法 |
CN108878405A (zh) * | 2018-07-02 | 2018-11-23 | 深圳市槟城电子有限公司 | 一种防护器件及其制作方法、电子设备 |
US11502045B2 (en) * | 2019-01-23 | 2022-11-15 | Texas Instruments Incorporated | Electronic device with step cut lead |
CN113851447B (zh) * | 2021-09-23 | 2022-06-07 | 先之科半导体科技(东莞)有限公司 | 一种免金线的肖特基二极管及其制作方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06151685A (ja) * | 1992-11-04 | 1994-05-31 | Mitsubishi Electric Corp | Mcp半導体装置 |
JPH06204390A (ja) * | 1993-01-07 | 1994-07-22 | Fujitsu Ltd | 半導体装置 |
JPH06224362A (ja) * | 1992-10-28 | 1994-08-12 | Internatl Business Mach Corp <Ibm> | 電子素子用リードフレーム・パッケージ |
JPH08195463A (ja) * | 1995-01-17 | 1996-07-30 | Hitachi Ltd | 樹脂封止型半導体装置及びその製造に使用されるリードフレーム |
JPH08227903A (ja) * | 1995-12-28 | 1996-09-03 | Hitachi Vlsi Eng Corp | 半導体装置 |
JPH11121677A (ja) * | 1998-08-12 | 1999-04-30 | Miyazaki Oki Electric Co Ltd | 樹脂封止型半導体装置 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06105721B2 (ja) * | 1985-03-25 | 1994-12-21 | 日立超エル・エス・アイエンジニアリング株式会社 | 半導体装置 |
JPH0846131A (ja) * | 1994-08-02 | 1996-02-16 | Sony Corp | リードフレーム及びワイヤボンディング装置 |
US5615475A (en) * | 1995-01-30 | 1997-04-01 | Staktek Corporation | Method of manufacturing an integrated package having a pair of die on a common lead frame |
JP3209696B2 (ja) * | 1996-03-07 | 2001-09-17 | 松下電器産業株式会社 | 電子部品の製造方法 |
US5907769A (en) * | 1996-12-30 | 1999-05-25 | Micron Technology, Inc. | Leads under chip in conventional IC package |
US6054754A (en) | 1997-06-06 | 2000-04-25 | Micron Technology, Inc. | Multi-capacitance lead frame decoupling device |
JP3688440B2 (ja) | 1997-07-29 | 2005-08-31 | 株式会社ルネサステクノロジ | 半導体装置 |
JP3415509B2 (ja) | 1999-09-28 | 2003-06-09 | エヌイーシーマイクロシステム株式会社 | 半導体装置 |
KR100494228B1 (ko) | 1999-12-15 | 2005-06-13 | 도모에고교 가부시키가이샤 | 원심선별장치 |
JP3768761B2 (ja) | 2000-01-31 | 2006-04-19 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
JP3813788B2 (ja) * | 2000-04-14 | 2006-08-23 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US6541849B1 (en) * | 2000-08-25 | 2003-04-01 | Micron Technology, Inc. | Memory device power distribution |
JP2002231882A (ja) | 2001-02-06 | 2002-08-16 | Mitsubishi Electric Corp | 半導体装置 |
JP4372022B2 (ja) | 2004-04-27 | 2009-11-25 | 株式会社東芝 | 半導体装置 |
WO2006028421A1 (en) * | 2004-09-09 | 2006-03-16 | United Test And Assembly Center Limited | Multi-die ic package and manufacturing method |
JP2007129182A (ja) * | 2005-05-11 | 2007-05-24 | Toshiba Corp | 半導体装置 |
US7375415B2 (en) * | 2005-06-30 | 2008-05-20 | Sandisk Corporation | Die package with asymmetric leadframe connection |
-
2006
- 2006-04-19 JP JP2006115959A patent/JP2007129182A/ja active Pending
- 2006-05-10 US US11/430,965 patent/US7919837B2/en active Active
- 2006-05-10 KR KR1020060041841A patent/KR100810324B1/ko active IP Right Grant
- 2006-05-11 CN CNB2006100817751A patent/CN100440498C/zh not_active Expired - Fee Related
-
2011
- 2011-02-17 US US13/029,466 patent/US8970019B2/en active Active
-
2015
- 2015-02-09 US US14/617,637 patent/US10366942B2/en active Active
-
2019
- 2019-06-12 US US16/438,826 patent/US10872844B2/en active Active
-
2020
- 2020-11-19 US US16/952,968 patent/US11424176B2/en active Active
-
2022
- 2022-07-13 US US17/864,064 patent/US11854946B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06224362A (ja) * | 1992-10-28 | 1994-08-12 | Internatl Business Mach Corp <Ibm> | 電子素子用リードフレーム・パッケージ |
JPH06151685A (ja) * | 1992-11-04 | 1994-05-31 | Mitsubishi Electric Corp | Mcp半導体装置 |
JPH06204390A (ja) * | 1993-01-07 | 1994-07-22 | Fujitsu Ltd | 半導体装置 |
JPH08195463A (ja) * | 1995-01-17 | 1996-07-30 | Hitachi Ltd | 樹脂封止型半導体装置及びその製造に使用されるリードフレーム |
JPH08227903A (ja) * | 1995-12-28 | 1996-09-03 | Hitachi Vlsi Eng Corp | 半導体装置 |
JPH11121677A (ja) * | 1998-08-12 | 1999-04-30 | Miyazaki Oki Electric Co Ltd | 樹脂封止型半導体装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100920052B1 (ko) | 2008-01-02 | 2009-10-07 | 주식회사 하이닉스반도체 | 반도체 패키지용 리드 프레임 |
JP2010182873A (ja) * | 2009-02-05 | 2010-08-19 | Toshiba Corp | 半導体デバイス |
US8912636B2 (en) | 2009-02-05 | 2014-12-16 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US10872844B2 (en) | 2020-12-22 |
KR20060116728A (ko) | 2006-11-15 |
US7919837B2 (en) | 2011-04-05 |
US11854946B2 (en) | 2023-12-26 |
US20150155225A1 (en) | 2015-06-04 |
US8970019B2 (en) | 2015-03-03 |
KR100810324B1 (ko) | 2008-03-04 |
US11424176B2 (en) | 2022-08-23 |
US20060255436A1 (en) | 2006-11-16 |
CN100440498C (zh) | 2008-12-03 |
US10366942B2 (en) | 2019-07-30 |
US20210074609A1 (en) | 2021-03-11 |
US20220044987A9 (en) | 2022-02-10 |
US20220352053A1 (en) | 2022-11-03 |
CN1862798A (zh) | 2006-11-15 |
US20190295928A1 (en) | 2019-09-26 |
US20110133323A1 (en) | 2011-06-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4372022B2 (ja) | 半導体装置 | |
JP2007129182A (ja) | 半導体装置 | |
US7755175B2 (en) | Multi-stack chip package with wired bonded chips | |
JP5207868B2 (ja) | 半導体装置 | |
JP2567961B2 (ja) | 半導体装置及びリ−ドフレ−ム | |
US20040145042A1 (en) | Semiconductor device | |
JP4643341B2 (ja) | 半導体装置 | |
JP5619128B2 (ja) | 半導体装置 | |
JP6023866B2 (ja) | 半導体装置 | |
JP2007250935A (ja) | 半導体装置と半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090209 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090422 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110830 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111031 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120110 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120307 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20120529 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20121002 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121227 |