JP2010182873A - 半導体デバイス - Google Patents
半導体デバイス Download PDFInfo
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- JP2010182873A JP2010182873A JP2009024988A JP2009024988A JP2010182873A JP 2010182873 A JP2010182873 A JP 2010182873A JP 2009024988 A JP2009024988 A JP 2009024988A JP 2009024988 A JP2009024988 A JP 2009024988A JP 2010182873 A JP2010182873 A JP 2010182873A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】リードフレーム1は、インナーリード領域Yと重なるチップ搭載領域Xと、インナーリード領域Yの外側に配置されたアウターリード部3、4と、インナーリード領域内に配置されたインナーリード部2とを備える。リードフレーム1には半導体チップ5が搭載される。半導体チップ5の電極パッド6はインナーリード2A、2Bと金属ワイヤ8を介して接続される。インナーリード2Bはインナーリード領域Y内のチップ搭載領域Xを除く領域に位置する部分をデプレス加工した加工部12を有する。
【選択図】図4
Description
Claims (5)
- インナーリード領域と、少なくとも一部が前記インナーリード領域と重なるように設けられたチップ搭載領域と、前記インナーリード領域の外側に配置された複数のアウターリードを有するアウターリード部と、前記インナーリード領域内に配置された複数のインナーリードを有するインナーリード部とを備える回路基材と;
前記回路基材の前記チップ搭載領域に搭載され、1つの外形辺に沿って配列された電極パッドを有する半導体チップと;
前記半導体チップの前記電極パッドと前記回路基材の前記インナーリードとを電気的に接続する金属ワイヤと;
前記半導体チップを前記金属ワイヤと共に封止する樹脂封止部とを具備し、
前記インナーリードは前記インナーリード領域内の前記チップ搭載領域を除く領域に位置する部分をデプレス加工した加工部を有することを特徴とする半導体デバイス。 - 請求項1記載の半導体デバイスにおいて、
前記インナーリードの加工部は前記半導体チップの搭載面側が凸状となるようにデプレス加工されていることを特徴とする半導体デバイス。 - 請求項1または請求項2記載の半導体デバイスにおいて、
前記アウターリード部は、第1のアウターリードを有する第1のアウターリード部と、前記第1のアウターリードと前記インナーリード領域を介して対向配置された第2のアウターリードを有する第2のアウターリード部とを備え、かつ前記インナーリード部は前記第1のアウターリードに接続された第1のインナーリードと、前記第2のアウターリードに接続された第2のインナーリードとを有し、前記第1および第2のインナーリードの少なくとも一方が前記チップ搭載領域内を引き回されていると共に、前記チップ搭載領域内を引き回されている前記インナーリードの前記チップ搭載領域外に位置する部分に前記加工部が設けられていることを特徴とする半導体デバイス。 - 請求項3記載の半導体デバイスにおいて、
前記第1のインナーリードは前記第1のアウターリード部側に配置され、前記第2のインナーリードは前記第2のアウターリード部から前記チップ搭載領域を介して前記第1のアウターリード部に向けて引き回されていると共に、前記第2のアウターリード部との接続部分と前記チップ搭載領域との間の部分に設けられた前記加工部を有することを特徴とする半導体デバイス。 - 請求項4記載の半導体デバイスにおいて、
前記半導体チップは前記電極パッドが配列された前記外形辺が前記第1のインナーリードの先端部および前記第2のインナーリードの先端部が配置された接続領域の近傍に位置するように配置されていることを特徴とする半導体デバイス。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009024988A JP5361426B2 (ja) | 2009-02-05 | 2009-02-05 | 半導体デバイス |
US12/699,446 US8912636B2 (en) | 2009-02-05 | 2010-02-03 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2009024988A JP5361426B2 (ja) | 2009-02-05 | 2009-02-05 | 半導体デバイス |
Publications (2)
Publication Number | Publication Date |
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JP2010182873A true JP2010182873A (ja) | 2010-08-19 |
JP5361426B2 JP5361426B2 (ja) | 2013-12-04 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009024988A Active JP5361426B2 (ja) | 2009-02-05 | 2009-02-05 | 半導体デバイス |
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US (1) | US8912636B2 (ja) |
JP (1) | JP5361426B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4489100B2 (ja) | 2007-06-18 | 2010-06-23 | 株式会社東芝 | 半導体パッケージ |
JP5618873B2 (ja) * | 2011-03-15 | 2014-11-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
DE102015101674B4 (de) | 2015-02-05 | 2021-04-29 | Infineon Technologies Austria Ag | Halbleiterchipgehäuse mit Kontaktstiften an kurzen Seitenrändern |
US10749177B2 (en) * | 2018-07-17 | 2020-08-18 | Guangxi Nowphene Energy Storage Technologies Co., Ltd | Method of synthesizing phosphate salt of high purity for preparation of electrode material |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000196002A (ja) * | 1998-10-21 | 2000-07-14 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2000513505A (ja) * | 1996-06-28 | 2000-10-10 | シーメンス アクチエンゲゼルシヤフト | 集積半導体回路 |
JP2002100719A (ja) * | 2000-09-25 | 2002-04-05 | Toshiba Corp | 樹脂封止型半導体装置 |
JP2005340766A (ja) * | 2004-04-27 | 2005-12-08 | Toshiba Corp | 半導体装置 |
JP2007129182A (ja) * | 2005-05-11 | 2007-05-24 | Toshiba Corp | 半導体装置 |
JP2008085032A (ja) * | 2006-09-27 | 2008-04-10 | Toshiba Corp | 半導体装置 |
Family Cites Families (13)
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US5484959A (en) * | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
US5523617A (en) * | 1994-12-27 | 1996-06-04 | National Semiconductor Corporation | Fuse frames, programmable fuse frames, and methods for programming by fusing |
TW468258B (en) | 1998-10-21 | 2001-12-11 | Hitachi Ltd | Semiconductor device and method of manufacturing the same |
WO2000033379A1 (en) * | 1998-12-02 | 2000-06-08 | Hitachi, Ltd. | Semiconductor device, method of manufacture thereof, and electronic device |
US20040053447A1 (en) * | 2001-06-29 | 2004-03-18 | Foster Donald Craig | Leadframe having fine pitch bond fingers formed using laser cutting method |
US6798046B1 (en) * | 2002-01-22 | 2004-09-28 | Amkor Technology, Inc. | Semiconductor package including ring structure connected to leads with vertically downset inner ends |
US7375415B2 (en) * | 2005-06-30 | 2008-05-20 | Sandisk Corporation | Die package with asymmetric leadframe connection |
US7728411B2 (en) * | 2006-02-15 | 2010-06-01 | Sandisk Corporation | COL-TSOP with nonconductive material for reducing package capacitance |
TWI378539B (en) * | 2006-10-26 | 2012-12-01 | Chipmos Technologies Inc | Stacked chip package structure with lead-frame having inner leads with transfer pad |
JP4745205B2 (ja) * | 2006-11-30 | 2011-08-10 | 株式会社東芝 | 半導体装置 |
JP4489100B2 (ja) * | 2007-06-18 | 2010-06-23 | 株式会社東芝 | 半導体パッケージ |
JP4970401B2 (ja) | 2007-10-16 | 2012-07-04 | 株式会社東芝 | 半導体装置 |
US7612436B1 (en) * | 2008-07-31 | 2009-11-03 | Micron Technology, Inc. | Packaged microelectronic devices with a lead frame |
-
2009
- 2009-02-05 JP JP2009024988A patent/JP5361426B2/ja active Active
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2010
- 2010-02-03 US US12/699,446 patent/US8912636B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000513505A (ja) * | 1996-06-28 | 2000-10-10 | シーメンス アクチエンゲゼルシヤフト | 集積半導体回路 |
JP2000196002A (ja) * | 1998-10-21 | 2000-07-14 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002100719A (ja) * | 2000-09-25 | 2002-04-05 | Toshiba Corp | 樹脂封止型半導体装置 |
JP2005340766A (ja) * | 2004-04-27 | 2005-12-08 | Toshiba Corp | 半導体装置 |
JP2007129182A (ja) * | 2005-05-11 | 2007-05-24 | Toshiba Corp | 半導体装置 |
JP2008085032A (ja) * | 2006-09-27 | 2008-04-10 | Toshiba Corp | 半導体装置 |
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Publication number | Publication date |
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JP5361426B2 (ja) | 2013-12-04 |
US8912636B2 (en) | 2014-12-16 |
US20100193924A1 (en) | 2010-08-05 |
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