JP2000513505A - 集積半導体回路 - Google Patents
集積半導体回路Info
- Publication number
- JP2000513505A JP2000513505A JP10503727A JP50372798A JP2000513505A JP 2000513505 A JP2000513505 A JP 2000513505A JP 10503727 A JP10503727 A JP 10503727A JP 50372798 A JP50372798 A JP 50372798A JP 2000513505 A JP2000513505 A JP 2000513505A
- Authority
- JP
- Japan
- Prior art keywords
- housing
- semiconductor
- lead frame
- integrated semiconductor
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 集積半導体回路、例えば半導体メモリであって、 半導体チップ(1)を有し、該半導体チップ(1)を収容するハウジング(5 )を有し、さらに前記半導体チップ(1)の接点面(2)と集積半導体回路の外 部端子(7)との間を接続するための個々のリード(3)から成るリードフレー ム(4)を有し、前記接点面(2)に接続される前記リードフレーム(4)の第 1の領域と前記外部端子(7)に接続される前記リードフレーム(4)の第2の 領域とが実質的に同一平面に存在する、集積半導体回路、例えば半導体メモリに おいて、 前記リードフレーム(4)の前記リード(3)は第3の領域(6)において前 記第1及び第2の領域のレベルから前記接点面(2)に対向配置された前記半導 体チップ(1)の上側表面へと低下されており、 前記第3の領域(6)は前記第1の領域と第2の領域との間に存在し、前記半 導体チップ(1)の周囲の外側に設けられていることを特徴とする、集積半導体 回路、例えば半導体メモリ。 2. 第3の領域(6)の低下はほぼハウジング(5)の中心面にまで達するこ とを特徴とする請求項1記載の集積半導体回路。 3. リードフレームはニッケル/鉄及び銅合金から成り、ハウジングはエポキ シベースの可塑材料から成ることを特徴とする請求項1又は2記載の集積半導体 回路。 4. 第3の領域(6)は、半導体チップ(1)とハウジング(5)の周縁との 間の間隔が最大であるような集積半導体回路のゾーンに設けられてることを特徴 とする請求項1〜3までのうちの1項記載の集積半導体回路。 5. 第3の領域(6)における低下はリードフレーム(4)の製造の際に下方 にエンボシングすることによって形成され、 半導体チップ(1)は前記リードフレーム(4)に接続され、さらにハウジン グ(5)にモールドされることを特徴とする請求項1〜4までのうちの1項記載 の集積半導体回路の製造の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19626087A DE19626087C2 (de) | 1996-06-28 | 1996-06-28 | Integrierte Halbleiterschaltung mit Leiterrahmen und Gehäuse |
DE19626087.6 | 1996-06-28 | ||
PCT/DE1997/001273 WO1998000867A1 (de) | 1996-06-28 | 1997-06-19 | Integrierte halbleiterschaltung |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000513505A true JP2000513505A (ja) | 2000-10-10 |
JP3634381B2 JP3634381B2 (ja) | 2005-03-30 |
Family
ID=7798367
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50372798A Expired - Fee Related JP3634381B2 (ja) | 1996-06-28 | 1997-06-19 | 集積半導体回路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6057595A (ja) |
EP (1) | EP0907966B1 (ja) |
JP (1) | JP3634381B2 (ja) |
KR (1) | KR100381934B1 (ja) |
DE (2) | DE19626087C2 (ja) |
WO (1) | WO1998000867A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010182873A (ja) * | 2009-02-05 | 2010-08-19 | Toshiba Corp | 半導体デバイス |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6278175B1 (en) * | 2000-01-21 | 2001-08-21 | Micron Technology, Inc. | Leadframe alteration to direct compound flow into package |
JP2001230360A (ja) * | 2000-02-18 | 2001-08-24 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6459148B1 (en) * | 2000-11-13 | 2002-10-01 | Walsin Advanced Electronics Ltd | QFN semiconductor package |
US6512286B1 (en) * | 2001-10-09 | 2003-01-28 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with no void in encapsulant and method for fabricating the same |
US20040108580A1 (en) * | 2002-12-09 | 2004-06-10 | Advanpack Solutions Pte. Ltd. | Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture |
JP2006066008A (ja) * | 2004-08-30 | 2006-03-09 | Hitachi Global Storage Technologies Netherlands Bv | 磁気ディスクおよび磁気ディスクの製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6015786A (ja) * | 1983-07-06 | 1985-01-26 | Dainippon Printing Co Ltd | Icカ−ドおよびその製造法 |
JPS6474748A (en) * | 1987-09-16 | 1989-03-20 | Nec Corp | Lead frame |
JPH07121633B2 (ja) * | 1988-04-28 | 1995-12-25 | 松下電器産業株式会社 | Icカード用モジュールとそれを用いたicカード |
JPH03235360A (ja) * | 1990-02-09 | 1991-10-21 | Nec Corp | 樹脂封止型半導体装置 |
JPH04162640A (ja) * | 1990-10-25 | 1992-06-08 | Hitachi Ltd | 半導体装置 |
JPH06252333A (ja) * | 1993-02-22 | 1994-09-09 | Hitachi Constr Mach Co Ltd | 半導体装置及びその製造方法 |
US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
US5760471A (en) * | 1994-04-20 | 1998-06-02 | Fujitsu Limited | Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package |
KR0184076B1 (ko) * | 1995-11-28 | 1999-03-20 | 김광호 | 상하 접속 수단이 패키지 내부에 형성되어 있는 3차원 적층형 패키지 |
US5866939A (en) * | 1996-01-21 | 1999-02-02 | Anam Semiconductor Inc. | Lead end grid array semiconductor package |
-
1996
- 1996-06-28 DE DE19626087A patent/DE19626087C2/de not_active Expired - Fee Related
-
1997
- 1997-06-19 JP JP50372798A patent/JP3634381B2/ja not_active Expired - Fee Related
- 1997-06-19 KR KR10-1998-0710751A patent/KR100381934B1/ko not_active IP Right Cessation
- 1997-06-19 EP EP97929127A patent/EP0907966B1/de not_active Expired - Lifetime
- 1997-06-19 DE DE59706321T patent/DE59706321D1/de not_active Expired - Lifetime
- 1997-06-19 WO PCT/DE1997/001273 patent/WO1998000867A1/de active IP Right Grant
-
1998
- 1998-12-28 US US09/221,774 patent/US6057595A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010182873A (ja) * | 2009-02-05 | 2010-08-19 | Toshiba Corp | 半導体デバイス |
Also Published As
Publication number | Publication date |
---|---|
DE19626087C2 (de) | 1998-06-10 |
JP3634381B2 (ja) | 2005-03-30 |
EP0907966B1 (de) | 2002-02-06 |
US6057595A (en) | 2000-05-02 |
DE19626087A1 (de) | 1998-01-02 |
DE59706321D1 (de) | 2002-03-21 |
KR100381934B1 (ko) | 2003-07-16 |
WO1998000867A1 (de) | 1998-01-08 |
EP0907966A1 (de) | 1999-04-14 |
KR20000022328A (ko) | 2000-04-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR960004562B1 (ko) | 반도체 장치 패키지 | |
EP1470587A1 (en) | A lead frame | |
JPH1168006A (ja) | リードフレーム及びこれを用いた半導体装置及びこれらの製造方法 | |
JPH04324662A (ja) | 半導体パッケージ | |
GB2451077A (en) | Semiconductor chip package | |
US20050051877A1 (en) | Semiconductor package having high quantity of I/O connections and method for fabricating the same | |
KR20020066483A (ko) | 반도체 패키지와 그 반도체 패키지의 기판 실장 구조 및적층 구조 | |
GB2317989A (en) | Lead frames for semiconductor packages | |
JP2000513505A (ja) | 集積半導体回路 | |
KR100390466B1 (ko) | 멀티칩 모듈 반도체패키지 | |
KR0148078B1 (ko) | 연장된 리드를 갖는 리드 온 칩용 리드프레임 | |
JP3234614B2 (ja) | 半導体装置及びその製造方法 | |
JP2001177007A (ja) | 半導体装置及びその製造方法 | |
JP3179414B2 (ja) | 半導体装置及びその製造方法 | |
JP3495566B2 (ja) | 半導体装置 | |
JP2001267484A (ja) | 半導体装置およびその製造方法 | |
KR19990086280A (ko) | 반도체 패키지 | |
KR0119759Y1 (ko) | 버텀 리드형 반도체 패키지 | |
JP2912813B2 (ja) | 電子部品 | |
KR20020031881A (ko) | 반도체 패키지 및 그 제조방법 | |
JPH0521649A (ja) | 半導体装置 | |
KR100252862B1 (ko) | 반도체 패키지 및 그의 제조방법 | |
JP2000236033A (ja) | 半導体装置並びにその製造方法 | |
KR950010866B1 (ko) | 표면 실장형(surface mounting type) 반도체 패키지(package) | |
KR100525091B1 (ko) | 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040330 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040628 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20041207 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20041224 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080107 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090107 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100107 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110107 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110107 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120107 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130107 Year of fee payment: 8 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |