JP4489100B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP4489100B2 JP4489100B2 JP2007159942A JP2007159942A JP4489100B2 JP 4489100 B2 JP4489100 B2 JP 4489100B2 JP 2007159942 A JP2007159942 A JP 2007159942A JP 2007159942 A JP2007159942 A JP 2007159942A JP 4489100 B2 JP4489100 B2 JP 4489100B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 220
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229920005989 resin Polymers 0.000 claims description 35
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- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/495—Lead-frames or other flat leads
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Description
Claims (4)
- 複数のアウターリードを有するアウターリード部と、前記アウターリードに接続されたインナーリードと前記アウターリードに接続されていない中継用インナーリードとを有するインナーリード部とを備えるリードフレームと、
前記リードフレームの下面側に積層され、それぞれ片側の長辺に沿って配列された電極パッドを有する複数の半導体素子を備える半導体素子群と、
前記インナーリード部と前記複数の半導体素子の前記電極パッドとを電気的に接続する接続用金属ワイヤと、
前記半導体素子群を前記接続用金属ワイヤと共に封止する樹脂封止部とを具備し、
前記中継用インナーリードの一端は前記接続用金属ワイヤを介して前記半導体素子の前記電極パッドと電気的に接続されており、他端は前記インナーリードを跨ぐように配置された中継用金属ワイヤを介して前記アウターリードと電気的に接続されており、
前記アウターリード部は前記半導体素子の対向する短辺からそれぞれ突出するように配置されていると共に、前記インナーリード部は前記アウターリード部から前記電極パッドが配列された前記半導体素子の長辺に向けて引き回されていることを特徴とする半導体パッケージ。 - 請求項1記載の半導体パッケージにおいて、
前記複数の半導体素子は接着層を介して積層されており、前記リードフレームへの積層順に対して下層側の前記半導体素子に接続された前記接続用金属ワイヤの素子側端部は、前記積層順に対して上層側の前記半導体素子を接着する前記接着層内に埋め込まれていることを特徴とする半導体パッケージ。 - 請求項1または請求項2記載の半導体パッケージにおいて、
前記リードフレームは素子支持部を有し、前記素子支持部から前記インナーリード部までが平坦化されていることを特徴とする半導体パッケージ。 - 請求項1ないし請求項3のいずれか1項記載の半導体パッケージにおいて、
前記アウターリード部の配列方向の両端に位置する前記アウターリードは、それぞれダムバーカット部の下方に設けられ、前記配列方向の外側に向けて突出された位置決め用突起を有することを特徴とする半導体パッケージ。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007159942A JP4489100B2 (ja) | 2007-06-18 | 2007-06-18 | 半導体パッケージ |
US12/140,658 US7989932B2 (en) | 2007-06-18 | 2008-06-17 | Semiconductor device |
US13/167,296 US8193621B2 (en) | 2007-06-18 | 2011-06-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007159942A JP4489100B2 (ja) | 2007-06-18 | 2007-06-18 | 半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008311559A JP2008311559A (ja) | 2008-12-25 |
JP4489100B2 true JP4489100B2 (ja) | 2010-06-23 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007159942A Expired - Fee Related JP4489100B2 (ja) | 2007-06-18 | 2007-06-18 | 半導体パッケージ |
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US (2) | US7989932B2 (ja) |
JP (1) | JP4489100B2 (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5275019B2 (ja) * | 2008-12-26 | 2013-08-28 | 株式会社東芝 | 半導体装置 |
JP5361426B2 (ja) * | 2009-02-05 | 2013-12-04 | 株式会社東芝 | 半導体デバイス |
JP2011181697A (ja) * | 2010-03-01 | 2011-09-15 | Toshiba Corp | 半導体パッケージおよびその製造方法 |
US8836137B2 (en) | 2012-04-19 | 2014-09-16 | Macronix International Co., Ltd. | Method for creating a 3D stacked multichip module |
US8987914B2 (en) | 2013-02-07 | 2015-03-24 | Macronix International Co., Ltd. | Conductor structure and method |
US8993429B2 (en) | 2013-03-12 | 2015-03-31 | Macronix International Co., Ltd. | Interlayer conductor structure and method |
JP5814965B2 (ja) * | 2013-03-15 | 2015-11-17 | 株式会社東芝 | 半導体装置 |
US9117526B2 (en) | 2013-07-08 | 2015-08-25 | Macronix International Co., Ltd. | Substrate connection of three dimensional NAND for improving erase performance |
US9070447B2 (en) | 2013-09-26 | 2015-06-30 | Macronix International Co., Ltd. | Contact structure and forming method |
US8970040B1 (en) | 2013-09-26 | 2015-03-03 | Macronix International Co., Ltd. | Contact structure and forming method |
US9343322B2 (en) | 2014-01-17 | 2016-05-17 | Macronix International Co., Ltd. | Three dimensional stacking memory film structure |
US9196628B1 (en) | 2014-05-08 | 2015-11-24 | Macronix International Co., Ltd. | 3D stacked IC device with stepped substack interlayer connectors |
US9721964B2 (en) | 2014-06-05 | 2017-08-01 | Macronix International Co., Ltd. | Low dielectric constant insulating material in 3D memory |
DE102015101674B4 (de) | 2015-02-05 | 2021-04-29 | Infineon Technologies Austria Ag | Halbleiterchipgehäuse mit Kontaktstiften an kurzen Seitenrändern |
US9379129B1 (en) | 2015-04-13 | 2016-06-28 | Macronix International Co., Ltd. | Assist gate structures for three-dimensional (3D) vertical gate array memory structure |
JP6352876B2 (ja) * | 2015-09-15 | 2018-07-04 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
CN109065520A (zh) * | 2018-06-26 | 2018-12-21 | 深圳信炜生物识别科技有限公司 | 一种芯片封装结构、芯片功能模组及电子设备 |
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JPH07101726B2 (ja) | 1985-08-13 | 1995-11-01 | 松下電子工業株式会社 | リ−ドフレ−ム |
JPS63107159A (ja) | 1986-10-24 | 1988-05-12 | Toshiba Corp | 半導体装置 |
KR970011649B1 (ko) * | 1988-03-10 | 1997-07-12 | 가부시끼가이샤 히다찌세이사꾸쇼 | 반도체 장치의 제조방법 |
US5162894A (en) * | 1988-05-24 | 1992-11-10 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit having a dummy lead and shaped inner leads |
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US20090001530A1 (en) | 2009-01-01 |
US20110248395A1 (en) | 2011-10-13 |
JP2008311559A (ja) | 2008-12-25 |
US7989932B2 (en) | 2011-08-02 |
US8193621B2 (en) | 2012-06-05 |
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