KR20090012378A - 반도체 패키지 - Google Patents
반도체 패키지 Download PDFInfo
- Publication number
- KR20090012378A KR20090012378A KR1020070076127A KR20070076127A KR20090012378A KR 20090012378 A KR20090012378 A KR 20090012378A KR 1020070076127 A KR1020070076127 A KR 1020070076127A KR 20070076127 A KR20070076127 A KR 20070076127A KR 20090012378 A KR20090012378 A KR 20090012378A
- Authority
- KR
- South Korea
- Prior art keywords
- mounting plate
- chip mounting
- chip
- lead
- semiconductor package
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (4)
- 칩탑재판, 파워바 및 다수의 리드들이 다운셋없이 하나의 평면을 이루는 구조의 리드프레임과;상기 칩탑재판에 부착된 반도체 칩과;상기 반도체 칩과 리드간, 상기 반도체 칩과 파워바간을 연결하는 와이어와;상기 반도체 칩, 칩탑재판의 상면, 파워바의 상면, 리드의 상면을 감싸면서 몰딩하는 상부 몰딩수지와;상기 칩탑재판의 저면을 제외하고, 파워바의 저면과 리드의 저면을 감싸면서 몰딩하는 하부 몰딩수지와;상기 상부 및 하부 몰딩수지의 측부로 통해 외부로 노출 연장되어, 단자로서 포밍된 외부리드;로 구성된 것을 특징으로 하는 반도체 패키지.
- 청구항 1에 있어서, 외부로 노출된 상기 칩탑재판의 저면에는 히트싱크가 부착된 것을 특징으로 하는 반도체 패키지.
- 청구항 1에 있어서, 상기 칩탑재판의 저면 테두리 부분은 하부 몰딩수지로 감싸여지는 것을 특징으로 하는 반도체 패키지.
- 청구항 1 내지 청구항 3중 어느 하나의 항에 있어서,상기 외부리드가 하부 몰딩수지쪽으로 절곡되며 포밍되는 경우에 상기 칩탑재판의 저면은 아래쪽을 향하게 되고, 상기 외부리드가 상부 몰딩수지쪽으로 절곡되며 포밍되는 경우에는 상기 칩탑재판의 저면은 위쪽을 향하게 되는 것을 특징으로 하는 반도체 패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070076127A KR100940760B1 (ko) | 2007-07-30 | 2007-07-30 | 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070076127A KR100940760B1 (ko) | 2007-07-30 | 2007-07-30 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20090012378A true KR20090012378A (ko) | 2009-02-04 |
KR100940760B1 KR100940760B1 (ko) | 2010-02-11 |
Family
ID=40683148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070076127A KR100940760B1 (ko) | 2007-07-30 | 2007-07-30 | 반도체 패키지 |
Country Status (1)
Country | Link |
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KR (1) | KR100940760B1 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102231769B1 (ko) * | 2019-08-20 | 2021-04-01 | 제엠제코(주) | 고열전도를 위한 히트싱크 노출형 반도체 패키지 및 그 제조방법 |
KR102172689B1 (ko) * | 2020-02-07 | 2020-11-02 | 제엠제코(주) | 반도체 패키지 및 그 제조방법 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990033767A (ko) * | 1997-10-27 | 1999-05-15 | 윤종용 | 반도체 패키지 및 그 제조방법 |
JP2004140275A (ja) * | 2002-10-21 | 2004-05-13 | Renesas Technology Corp | 半導体装置及びその製造方法 |
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2007
- 2007-07-30 KR KR1020070076127A patent/KR100940760B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR100940760B1 (ko) | 2010-02-11 |
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