KR20030079170A - 리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법 - Google Patents
리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법 Download PDFInfo
- Publication number
- KR20030079170A KR20030079170A KR1020020018015A KR20020018015A KR20030079170A KR 20030079170 A KR20030079170 A KR 20030079170A KR 1020020018015 A KR1020020018015 A KR 1020020018015A KR 20020018015 A KR20020018015 A KR 20020018015A KR 20030079170 A KR20030079170 A KR 20030079170A
- Authority
- KR
- South Korea
- Prior art keywords
- die pad
- lead frame
- lead
- semiconductor package
- semiconductor chip
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (2)
- 다이패드 및, 상기 다이패드와 분리된 것으로 중심부에 소재가 제거되어 빈 공간부가 형성되고 이로부터 방사상으로 배열되는 복수 개의 리드를 구비하는 리드프레임을 준비하는 단계;상기 다이패드가 상기 리드프레임의 중심부에 위치되도록 상기 다이패드와 리드프레임을 접착테이프 위에 부착하는 단계;상기 다이패드 위에 반도체 칩을 부착하는 단계;상기 반도체 칩의 전극과 상기 리드, 및 상기 반도체 칩의 전극과 상기 다이패드를 와이어 본딩하여 연결하는 단계;상기 반도체 칩, 다이패드, 및 리드를 수지로 몰딩하여 엔캡슐레이션을 형성하는 단계; 및상기 다이패드 및 리드의 아래에 부착된 접착테이프를 제거하는 단계;를 구비하여 된 것을 특징으로 하는 반도체 패키지 제조 방법.
- 제 1 항에 있어서,상기 다이패드 및 리드프레임 준비 단계에서는 다이패드의 테두리부 및 리드의 말단부를 하프 에칭하는 것을 특징으로 하는 반도체 패키지 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020018015A KR100819794B1 (ko) | 2002-04-02 | 2002-04-02 | 리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020018015A KR100819794B1 (ko) | 2002-04-02 | 2002-04-02 | 리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030079170A true KR20030079170A (ko) | 2003-10-10 |
KR100819794B1 KR100819794B1 (ko) | 2008-04-07 |
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Family Applications (1)
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KR1020020018015A KR100819794B1 (ko) | 2002-04-02 | 2002-04-02 | 리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법 |
Country Status (1)
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100633898B1 (ko) * | 2004-01-26 | 2006-10-13 | 앰코 테크놀로지 코리아 주식회사 | 반도체 장치의 몰드 클리닝용 회로기판의 재사용 방법 및이를 위한 테이핑 장치 |
KR100819799B1 (ko) * | 2005-02-22 | 2008-04-07 | 삼성테크윈 주식회사 | 다열리드형 반도체 패키지 제조 방법 |
Family Cites Families (12)
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JPS6290953A (ja) * | 1985-10-01 | 1987-04-25 | Fujitsu Ltd | 樹脂封止型半導体装置 |
CN87107692A (zh) * | 1986-11-13 | 1988-05-25 | Mt化学公司 | 半导体器件的制造方法 |
KR0149798B1 (ko) * | 1994-04-15 | 1998-10-01 | 모리시다 요이치 | 반도체 장치 및 그 제조방법과 리드프레임 |
KR970008530A (ko) * | 1995-07-07 | 1997-02-24 | 김광호 | 표면 실장용 리드프레임 및 그를 이용한 반도체 패키지와 그 제조방법 |
KR970018281A (ko) * | 1995-09-14 | 1997-04-30 | 김광호 | 반도체 패키지의 몰드수지와 리드프레임의 결착구조 |
KR970077547A (ko) * | 1996-05-31 | 1997-12-12 | 김광호 | 분리된 다이패드 및 그를 이용한 반도체 칩 패키지 및 제조 방법 |
JP2811170B2 (ja) * | 1996-06-28 | 1998-10-15 | 株式会社後藤製作所 | 樹脂封止型半導体装置及びその製造方法 |
US5798570A (en) * | 1996-06-28 | 1998-08-25 | Kabushiki Kaisha Gotoh Seisakusho | Plastic molded semiconductor package with thermal dissipation means |
JP3012816B2 (ja) * | 1996-10-22 | 2000-02-28 | 松下電子工業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP3034814B2 (ja) * | 1997-02-27 | 2000-04-17 | 沖電気工業株式会社 | リードフレーム構造及び半導体装置の製造方法 |
JP3420057B2 (ja) * | 1998-04-28 | 2003-06-23 | 株式会社東芝 | 樹脂封止型半導体装置 |
US6504238B2 (en) * | 2000-01-31 | 2003-01-07 | Texas Instruments Incorporated | Leadframe with elevated small mount pads |
-
2002
- 2002-04-02 KR KR1020020018015A patent/KR100819794B1/ko active IP Right Grant
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100633898B1 (ko) * | 2004-01-26 | 2006-10-13 | 앰코 테크놀로지 코리아 주식회사 | 반도체 장치의 몰드 클리닝용 회로기판의 재사용 방법 및이를 위한 테이핑 장치 |
KR100819799B1 (ko) * | 2005-02-22 | 2008-04-07 | 삼성테크윈 주식회사 | 다열리드형 반도체 패키지 제조 방법 |
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Publication number | Publication date |
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KR100819794B1 (ko) | 2008-04-07 |
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