JPS6290953A - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPS6290953A
JPS6290953A JP60219624A JP21962485A JPS6290953A JP S6290953 A JPS6290953 A JP S6290953A JP 60219624 A JP60219624 A JP 60219624A JP 21962485 A JP21962485 A JP 21962485A JP S6290953 A JPS6290953 A JP S6290953A
Authority
JP
Japan
Prior art keywords
chips
lead frame
printed board
resin
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60219624A
Other languages
English (en)
Inventor
Tsuyoshi Aoki
強 青木
Michio Ono
小野　道夫
Kazuhiro Maeda
前田　和浩
Hiroyuki Kitasako
北迫　弘幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60219624A priority Critical patent/JPS6290953A/ja
Priority to KR1019860008118A priority patent/KR900002908B1/ko
Publication of JPS6290953A publication Critical patent/JPS6290953A/ja
Priority to US07/207,929 priority patent/US4903114A/en
Pending legal-status Critical Current

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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概要〕 集積回路は樹脂あるいはセラミック等の外囲器にＩＣチ
ップが通常１個封入され、使用に当たりユーザ側で必要
なるＩｃを複数個プリント板に搭載して目的の回路を構
成する。本発明では樹脂封止型ＩＣでパッケージ内に複
数個のＩＣチップを搭載して、装置の小型化及びコスト
の削減を図った半導体装置を述べる。
〔産業上の利用分野〕
本発明は、樹脂封止型ＩＣパッケージにおいて複数個の
ＩＣチップを搭載した半導体装置に関する。
現在、大量に生産されている低価格ＩＣバッヶ−ジ構造
としては樹脂封止型ＩＣが広く用いられている。ユーザ
としては装置製作に必要とする回路をこれらのＩＣパッ
ケージを必要数プリント板上に搭載して構成しているが
、使用ＩＣの数に比例した実装コストが掛かる。
１個のＩＣチップはパッケージの寸法に比して著しく小
さいので、１つのＩＣパッケージ内に更に大きな回路構
成のＩＣチップを挿入した合理的なＩＣの出現が要望さ
れている。
〔従来の技術〕
上記に述べたごとく、１つのＩＣパッケージに従来の複
数個分のＩＣチップに相当する回路を１個のチップに集
約して収納することは可能である。
然し、このようなチップを新たに製作するにはウェハー
・プロセスで使用する多くの種類のマスクを準備するこ
とが必要であり需要数が少ない場合は合理的でない。
また、同一のウェハーあるいはチップ上に形成すること
が技術的に不可能の場合も起こり得る。
１つのチップ上に大規模な回路を収容する方法では、開
発に必要なるマスク等の費用を負担するだけの需要数量
を必要とする。
この条件に合致しない場合は、セラミック等の基板上に
複数のＩＣチップ及びその他のチップ部品等を搭載して
封入するハイブリッド集積回路を形成する方法が用いら
れる。
然し、このハイブリッド集積回路もカスタム製品的なる
要素が大で、低コスト化に対しては必ずしも満足すべき
状態ではない。
〔発明が解決しようとする問題点〕
樹脂封止型ＩＣパッケージで用いられているリードフレ
ーム上にＩＣチップを搭載し、トランスファ・モールド
装置を用いて樹脂封止する技術は、量産化、低価格には
最適である。
然し、この技術をそのまま適用して、複数のＩＣチップ
を１つのパッケージ内に収容するためには次のの問題点
の解決を必要とする。
即ち、ＩＣチップをリードフレームに搭載する方法、チ
ップ相互間、あるいはリードフレーム端子との配線の方
法、信頼性確保のためのパッケージ構造等について細か
い配慮が必要である。
〔問題点を解決するための手段〕
上記問題点は、リードフレームのダイステージ上に複数
の半導体チップを搭載せるプリント板を載置する構造と
、該リードフレームの内部リードの端子と、該半導体チ
ップのパッドと、該プリント板に設けられたパッドとを
相互に配線する構造を有してなる本発明の樹脂封止型半
導体装置によって解決される。
本発明において、プリント板としては多層プリント板を
用いること、あるいはプリント板の裏面に絶縁層を設け
ることにより本発明の価値を高めることが出来る。
また、リードフレームのダイステージをデプレッション
構造とすること、またその材料として銅合金を使用する
ことにより信頼性の向上をはかることも出来る。
〔作用〕
プリント板を介在させてＩＣチップを複数個搭載するこ
とにより、ＩＣチップのパッド部とプリント板のパッド
間の相互配線は別工程で、先に準備しておくことが可能
で、ダイステージに搭載後の内部リードの端子との配線
は自動機をそのまま使用して実施することが出来る。
多層プリント板を使用することによりクロス配線を生ず
る場合も何等支障はなく配線可能で、スルーホールでの
短絡の問題は、プリント板の裏面に絶縁層を設けること
により避けること出来る。
また、プリント板の挿入により配線用のパッドとリード
フレームとの端子部との段差は、リードフレームにデプ
レッション構造を設けることにより同一平面内での配線
で行える。
樹脂封入パッケージ内に従来よりも多くのＩＣチップ、
あるいはプリント板等が挿入されているので、封入樹脂
とのマツチングが低下して信頼性を落とすのを避けるた
めリードフレームの材質を銅合金とする方法を用いる。
〔実施例〕
本発明の一実施例を図面により詳細説明する。
第１図は本発明の樹脂封止型半導体装置において、完成
品樹脂封止部８を部分的に除去して内部を露出せしめた
上面図を示す。また、第２図はＸ−Ｘでの断面図を示す
。
本実施例では、２個のＩＣチップ２を用い、これらはプ
リント板１に搭載され、更にリードフレーム３のダイス
テージ４に！３！置して固定されている。
プリント板１は集積度の低いＩＣチップを用いるときは
単層で配線中継用のバッド５のみを設けて使用すること
も可能であるが、搭載チップ数が増加し、またチップの
集積度の高い場合は多層プリント板を使用することが望
ましい。
これはチップ相互間の配線にクロス配線を必要とするこ
とが屡発生するので、この場合、クロス配線をプリント
板の眉間配線層で容易に実施することが可能である。
多層プリント板を使用する場合はプリント板の底面には
絶縁層が設けられていることが望ましい・これは多層プ
リント板のとき、そのスルーポールとダイステージを通
して短絡を防止するためである。
ダイステージ４は、リードフレーム３の内部リード６よ
り一段と低い段差のあるデプレッション構造となってい
る。この理由はプリント板を搭載せる際、プリント板の
バッド５と内部リード６との高さを出来るだけ平面化し
てボンディングを容易とするためである。
ＩＣチップをプリント板に搭載して、ＩＣチップのバッ
ド７とプリント板のバッド５との配線は別の工程で行っ
ておけば、プリント板１をダイステージ４に搭載して、
内部リード部６とプリント板との配線はすべて従来の装
置を用いて従来と同様の方法により実施することが可能
である。
配線の終わったアセンブリーは、従来のトランスファ・
モールド装置を用いて、同様に樹脂封止をすることが出
来る。
〔発明の効果〕
以上に説明せるごとく、本発明の樹脂封止型半導体装置
の構造を適用することにより、複数個のＩＣチップを１
個のパッケージに収容せる集積回路を、従来の装置をそ
のまま使用して極めて低コストで提供することが出来る
。
【図面の簡単な説明】
第１図は本発明にかかわる樹脂封止型半導体装置の上面
図、 第２図は本発明にかかわる樹脂封止型半導体装置の断面
図を示す。 図面において、 １はプリント板、 ２はＩＣチップ、 ３はリードフレーム、 ４はダイステージ、 ５はプリント板のバッド、 ６は内部リード、 ７はＩＣチップのバッド、 ８は樹脂封止部、 をそれぞれ示す。

Claims (5)

    【特許請求の範囲】
  1. （１）リードフレーム（３）のダイステージ（４）上に
    、複数の半導体チップ（２）を搭載せるプリント板（１
    ）を載置する構造と、 該リードフレームの内部リード（６）と、該半導体チッ
    プのパッド（７）と、該プリント板に設けられたパッド
    （５）とを相互に配線する構造を有してなることを特徴
    とする樹脂封止型半導体装置。
  2. （２）前記、プリント板（１）として多層プリント板を
    用いることを特徴とする特許請求範囲第（１）項記載の
    樹脂封止型半導体装置。
  3. （３）前記、プリント板（１）としてその裏面に絶縁層
    を有することを特徴とする特許請求範囲第（１）項記載
    の樹脂封止型半導体装置。
  4. （４）前記、リードフレームのダイステージ（４）をデ
    プレッション構造とせることを特徴とする特許請求範囲
    第（１）項記載の樹脂封止型半導体装置。
  5. （５）前記、リードフレーム（３）の材料として銅合金
    を使用することを特徴とする特許請求範囲第（１）項記
    載の樹脂封止型半導体装置。
JP60219624A 1985-10-01 1985-10-01 樹脂封止型半導体装置 Pending JPS6290953A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP60219624A JPS6290953A (ja) 1985-10-01 1985-10-01 樹脂封止型半導体装置
KR1019860008118A KR900002908B1 (ko) 1985-10-01 1986-09-27 수지 봉지형 반도체 장치
US07/207,929 US4903114A (en) 1985-10-01 1988-06-15 Resin-molded semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60219624A JPS6290953A (ja) 1985-10-01 1985-10-01 樹脂封止型半導体装置

Publications (1)

Publication Number Publication Date
JPS6290953A true JPS6290953A (ja) 1987-04-25

Family

ID=16738444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60219624A Pending JPS6290953A (ja) 1985-10-01 1985-10-01 樹脂封止型半導体装置

Country Status (3)

Country Link
US (1) US4903114A (ja)
JP (1) JPS6290953A (ja)
KR (1) KR900002908B1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100420880B1 (ko) * 1999-06-02 2004-03-02 세이코 엡슨 가부시키가이샤 멀티칩의 실장 구조, 전기 광학 장치 및 전자 기기

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2734463B2 (ja) * 1989-04-27 1998-03-30 株式会社日立製作所 半導体装置
US5231304A (en) * 1989-07-27 1993-07-27 Grumman Aerospace Corporation Framed chip hybrid stacked layer assembly
US5196992A (en) * 1989-08-25 1993-03-23 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device in which a very small semiconductor chip is sealed in package with resin
JP2848682B2 (ja) * 1990-06-01 1999-01-20 株式会社東芝 高速動作用半導体装置及びこの半導体装置に用いるフィルムキャリア
US5086335A (en) * 1990-07-31 1992-02-04 Hewlett-Packard Company Tape automated bonding system which facilitate repair
JPH04280664A (ja) * 1990-10-18 1992-10-06 Texas Instr Inc <Ti> 半導体装置用リードフレーム
JPH04352436A (ja) * 1991-05-30 1992-12-07 Fujitsu Ltd 半導体装置
US5138430A (en) * 1991-06-06 1992-08-11 International Business Machines Corporation High performance versatile thermally enhanced IC chip mounting
GB2257827B (en) * 1991-07-17 1995-05-03 Lsi Logic Europ Support for semiconductor bond wires
JPH0536756A (ja) * 1991-07-30 1993-02-12 Mitsubishi Electric Corp 半導体装置用テープキヤリア及びその製造方法
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
JPH06151685A (ja) * 1992-11-04 1994-05-31 Mitsubishi Electric Corp Ｍｃｐ半導体装置
JP2809945B2 (ja) * 1992-11-05 1998-10-15 株式会社東芝 半導体装置
WO1994025979A1 (en) * 1993-04-30 1994-11-10 Lsi Logic Corporation Integrated circuit with lead frame package having internal power and ground busses
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
US5455387A (en) * 1994-07-18 1995-10-03 Olin Corporation Semiconductor package with chip redistribution interposer
US5818102A (en) * 1995-12-29 1998-10-06 Lsi Logic Corporation System having integrated circuit package with lead frame having internal power and ground busses
US6064116A (en) 1997-06-06 2000-05-16 Micron Technology, Inc. Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications
JP3315644B2 (ja) * 1998-05-14 2002-08-19 富士通株式会社 弾性表面波素子
JP3631120B2 (ja) * 2000-09-28 2005-03-23 沖電気工業株式会社 半導体装置
US7199477B1 (en) * 2000-09-29 2007-04-03 Altera Corporation Multi-tiered lead package for an integrated circuit
JP2003188262A (ja) * 2001-12-14 2003-07-04 Mitsubishi Electric Corp 半導体素子
US6908843B2 (en) * 2001-12-28 2005-06-21 Texas Instruments Incorporated Method and system of wire bonding using interposer pads
KR100819794B1 (ko) * 2002-04-02 2008-04-07 삼성테크윈 주식회사 리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법
DE102004004422A1 (de) * 2004-01-29 2005-08-18 Conti Temic Microelectronic Gmbh Elektronisches Gerät sowie Verfahren zum Bonden eines elektronischen Gerätes
CN102487025B (zh) * 2010-12-08 2016-07-06 飞思卡尔半导体公司 用于长结合导线的支撑体
US20120286409A1 (en) * 2011-05-10 2012-11-15 Jitesh Shah Utilizing a jumper chip in packages with long bonding wires
US8994157B1 (en) * 2011-05-27 2015-03-31 Scientific Components Corporation Circuit system in a package
US8951847B2 (en) 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4208698A (en) * 1977-10-26 1980-06-17 Ilc Data Device Corporation Novel hybrid packaging scheme for high density component circuits
JPS58210650A (ja) * 1982-06-01 1983-12-07 Fujitsu Ltd 半導体装置
JPS58220434A (ja) * 1982-06-16 1983-12-22 Matsushita Electric Ind Co Ltd 半導体装置
JPS60250A (ja) * 1983-06-15 1985-01-05 Matsushita Electric Ind Co Ltd ヒ−トポンプ給湯機
JPH0751295B2 (ja) * 1992-07-15 1995-06-05 株式会社新潟鉄工所 回転テーブルの支持装置
JPH1195A (ja) * 1997-06-11 1999-01-06 Yotsugi Kk 蔓性植物の巻上がり防止装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100420880B1 (ko) * 1999-06-02 2004-03-02 세이코 엡슨 가부시키가이샤 멀티칩의 실장 구조, 전기 광학 장치 및 전자 기기
US6775149B1 (en) 1999-06-02 2004-08-10 Seiko Epson Corporation Multichip mounted structure, electro-optical apparatus, and electronic apparatus

Also Published As

Publication number Publication date
KR900002908B1 (ko) 1990-05-03
US4903114A (en) 1990-02-20
KR870004507A (ko) 1987-05-11

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