KR100819799B1 - 다열리드형 반도체 패키지 제조 방법 - Google Patents
다열리드형 반도체 패키지 제조 방법 Download PDFInfo
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- KR100819799B1 KR100819799B1 KR1020050014494A KR20050014494A KR100819799B1 KR 100819799 B1 KR100819799 B1 KR 100819799B1 KR 1020050014494 A KR1020050014494 A KR 1020050014494A KR 20050014494 A KR20050014494 A KR 20050014494A KR 100819799 B1 KR100819799 B1 KR 100819799B1
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- lead frame
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- raw material
- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Abstract
Description
Claims (6)
- 반도체 칩과, 각각 별도로 상기 반도체 칩 및 외부기판과 전기적으로 연결된 적어도 2열 이상의 리드를 가진 리드 프레임을 구비한 다열리드형 반도체 패키지를 제조하는 방법으로서,반도체 패키지용 리드 프레임 원자재를 공급하는 단계;상기 리드 프레임 원자재의 상면 및 하면에 감광제를 형성하는 단계;상기 리드 프레임 원자재의 상면 중 적어도 일부를 노광, 현상 및 에칭하여, 리드 프레임의 형상 가공 및 상기 리드 프레임의 인접 열 사이 제거를 동시에 행하는 단계;상기 리드 프레임에 상기 반도체 다이를 장착 및 결합하는 단계; 및상기 리드 프레임 및 반도체 다이를 몰딩하는 단계를 포함하는 것을 특징으로 하는 다열리드형 반도체 패키지의 제조방법.
- 제 1 항에 있어서,상기 감광제는 DFR(Dry Film photo-Resist) 또는 카세인(casein)인 것을 특징으로 하는 다열리드형 반도체 패키지의 제조방법.
- 제 1 항에 있어서,상기 몰딩 단계 이후에는 상기 리드 프레임의 하면에 형성된 감광제를 박리하는 단계를 거치는 것을 특징으로 하는 다열리드형 반도체 패키지의 제조방법.
- 제 1 항에 있어서,상기 리드 프레임 원자재의 상면에 형성된 감광제는, 상기 리드 프레임 원자재의 하면에 형성된 감광제보다 빨리 현상되는 것을 특징으로 하는 다열리드형 반도체 패키지의 제조방법.
- 제 4 항에 있어서,상기 리드 프레임 원자재의 하면에 형성된 감광제의 두께는, 상기 리드 프레임 원자재의 상면에 형성된 감광제보다 두꺼운 것을 특징으로 하는 다열리드형 반도체 패키지의 제조방법.
- 제 4 항에 있어서,상기 리드 프레임 원자재 상면 및 하면에 형성된 감광제는, 서로 다른 용재에 의하여 박리되는 것을 특징으로 하는 다열리드형 반도체 패키지의 제조방법.
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KR1020050014494A KR100819799B1 (ko) | 2005-02-22 | 2005-02-22 | 다열리드형 반도체 패키지 제조 방법 |
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KR1020050014494A KR100819799B1 (ko) | 2005-02-22 | 2005-02-22 | 다열리드형 반도체 패키지 제조 방법 |
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KR100819799B1 true KR100819799B1 (ko) | 2008-04-07 |
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KR101006907B1 (ko) * | 2008-02-20 | 2011-01-13 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 |
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KR950007068A (ko) * | 1993-08-27 | 1995-03-21 | 김광호 | 적층형 반도체 장치의 제조방법 및 그에 따른 반도체 패키지 |
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2005
- 2005-02-22 KR KR1020050014494A patent/KR100819799B1/ko active IP Right Grant
Patent Citations (10)
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KR950007068A (ko) * | 1993-08-27 | 1995-03-21 | 김광호 | 적층형 반도체 장치의 제조방법 및 그에 따른 반도체 패키지 |
KR970008508A (ko) * | 1995-07-28 | 1997-02-24 | 문정환 | 반도체 패키지 및 그 제조방법 |
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KR20000012443A (ko) * | 1999-12-04 | 2000-03-06 | 김무 | 반도체 패키지용 리드프레임 자재의 세정 방법 |
KR20000012442A (ko) * | 1999-12-04 | 2000-03-06 | 김무 | 반도체 패키지용 리드프레임 자재의 세정 방법 |
KR20020086219A (ko) * | 2001-05-11 | 2002-11-18 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치의 제조 방법 |
JP2003158142A (ja) * | 2001-11-21 | 2003-05-30 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JP2003197845A (ja) * | 2001-12-27 | 2003-07-11 | Mitsui High Tec Inc | リードフレーム及びこれを用いた半導体装置並びにその製造方法 |
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KR20040036292A (ko) * | 2002-10-24 | 2004-04-30 | 페어차일드코리아반도체 주식회사 | 탭 본딩을 위한 반도체 패키지 |
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