KR950007068A - 적층형 반도체 장치의 제조방법 및 그에 따른 반도체 패키지 - Google Patents

적층형 반도체 장치의 제조방법 및 그에 따른 반도체 패키지 Download PDF

Info

Publication number
KR950007068A
KR950007068A KR1019930016780A KR930016780A KR950007068A KR 950007068 A KR950007068 A KR 950007068A KR 1019930016780 A KR1019930016780 A KR 1019930016780A KR 930016780 A KR930016780 A KR 930016780A KR 950007068 A KR950007068 A KR 950007068A
Authority
KR
South Korea
Prior art keywords
leads
semiconductor
semiconductor chip
package
semiconductor device
Prior art date
Application number
KR1019930016780A
Other languages
English (en)
Other versions
KR100292036B1 (ko
Inventor
이충우
송영재
서동수
박정일
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930016780A priority Critical patent/KR100292036B1/ko
Priority to JP6196451A priority patent/JP2800967B2/ja
Priority to US08/296,596 priority patent/US5559305A/en
Publication of KR950007068A publication Critical patent/KR950007068A/ko
Application granted granted Critical
Publication of KR100292036B1 publication Critical patent/KR100292036B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

적층형 반도체 패키지에 있어서, 반도체 칩상에 리드들이 접착되는 리드-온-칩(Lead On Chip) 방법으로 리드 프레임의 리드들을 반도체 칩의 상부 또는 하부로 서로 교차되도록 횡단시켜서 적어도 두개 이상의 반도체칩을 실장하거나 절연 테이프상에 형성되어 있는 금속박막리드들을 사용하는 탭(Tape Automated Bondig)방법으로 적어도 두개 이상의 반도체 칩을 각각 고밀도로 실장하여, 상기 리드들의 하부에 접착제가 도포되어 적어도 두개 이상의 반도체 칩이 실장되고, 상기 리드들과 반도체 칩의 본딩패드가 경사지게 와이어 본딩된 후 상기 와이어 본딩부와 반도체 칩이 보호되도록 몰딩되어 반도체 장치용 패키지가 제조된다. 따라서 적층형 반도체 장치의 제조방법 및 그에 따른 반도체 패키지는 대규모 집적회로 실장용 패키지에 적합한 이점이 있다.

Description

적층형 반도체 장치의 제조방법 및 그에 따른 반도체 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도 (가) 및 (나)는 이 발명에 따른 적층형 반도체 장치의 제조공정도.
제4도는 이 발명에 따른 적층형 반도체 패키지의 단면도.
제5도는 반도체 패키지가 프린트 회로 보드에 실장된 도면으로서, (가)는 종래의 반도체 패키지 실장도, (나)는 이 발명에 따른 반도체 패키지의 실장도이다.

Claims (4)

  1. 리드 온 칩방법에 의해 적어도 하나 이상의 반도체 칩들을 실장하고 있는 적층형 반도체 장치의 제조방법에 있어서; 상기 리드들을 가로방향으로 서로 횡단되도록 배열형성하는 단계와; 상기 단계후 인너리드 상부에 절연접착 부재를 매개하여 적어도 두개 이상의 반도체 칩을 실장하여 어태치하는 단계와; 상기 단계후 반도체 칩의 본딩패드와 인너 리드를 소정 각도롤 경사지게 금선이나 은선으로 와이어 본딩하는 단계와; 상기 단계후 반도체 칩의 본딩패드와 인너 리드를 소정 각도를 경사지게 금선이나 은선으로 와이어 본딩하는 단계와; 상기 단계후 에폭시몰드 컴파운드로 몰딩하여 패키지의 몸체를 형성하는 단계로 이루어진 적층형 반도체 장치의 제조방법.
  2. 탭 방법에 의해 적어도 하나 이상의 반도체 칩들이 실장되는 적층형 반도체 장치의 제조방법에 있어서; 절연 테이프상에 인너리드들과 아웃리드들을 포함하도록 금속배선 패턴을 형성하는 단계와; 상기 단계후 인너리드들 상부에 금속 범프를 형성하는 단계와; 상기 단계후 금속 범프상에 다수개의 반도체 칩을 실장하고, 상기 리드들 상부에 형성된 금속 범프와 반도체 칩의 본딩패드를 열압착 방법에 의해 어태치 하는 단계와; 상기 단계후 반도체 칩을 보호하기 위하여 수지로 봉지하는 단계로 이루어진 적층형 반도체 장치의 제조방법.
  3. 리드 프레임의 리드를 상부 또는 하부에 접착제를 매개하여 다수개의 반도체 칩이 실장되고, 반도체 칩의 본딩패드들과 리드페레임의 인너 리드들이 와이어 본딩된 후 에폭시 몰들 컴파운드로 몰딩되어 형성된 반도체 장치용 패키지에 있어서; 상기 리드들이 가로방향으로 서로 횡단되도록 배열 형성되어, 상기 리드들의 하부에 접착제가 도포되어 적어도 2개의 이상의 반도체 칩이 실장되고, 상기 리드들과 반도체 칩의 본딩패드가 경사지게 와이어 본딩된 후 상기 와이어 본딩부와 반도체 칩이 보호되도록 몰딩되어 형성된 반도체 장치용 패키지.
  4. 제3항에 있어서, 상기 접착제는 리드를 상부에 적어도 2개 이상 도포되어 반도체 칩을 접착시키는 반도체 장치용 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930016780A 1993-08-27 1993-08-27 반도체패키지의제조방법및그에 따른반도체패키지 KR100292036B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019930016780A KR100292036B1 (ko) 1993-08-27 1993-08-27 반도체패키지의제조방법및그에 따른반도체패키지
JP6196451A JP2800967B2 (ja) 1993-08-27 1994-08-22 積層形半導体装置の製造方法及びそれによる半導体パッケージ
US08/296,596 US5559305A (en) 1993-08-27 1994-08-29 Semiconductor package having adjacently arranged semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930016780A KR100292036B1 (ko) 1993-08-27 1993-08-27 반도체패키지의제조방법및그에 따른반도체패키지

Publications (2)

Publication Number Publication Date
KR950007068A true KR950007068A (ko) 1995-03-21
KR100292036B1 KR100292036B1 (ko) 2001-09-17

Family

ID=19362091

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930016780A KR100292036B1 (ko) 1993-08-27 1993-08-27 반도체패키지의제조방법및그에 따른반도체패키지

Country Status (3)

Country Link
US (1) US5559305A (ko)
JP (1) JP2800967B2 (ko)
KR (1) KR100292036B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100819799B1 (ko) * 2005-02-22 2008-04-07 삼성테크윈 주식회사 다열리드형 반도체 패키지 제조 방법

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6384333B1 (en) * 1996-05-21 2002-05-07 Micron Technology, Inc. Underfill coating for LOC package
JPH1070230A (ja) * 1996-08-27 1998-03-10 Hitachi Cable Ltd Ｌｏｃ用リードフレーム
JP2954110B2 (ja) * 1997-09-26 1999-09-27 九州日本電気株式会社 Ｃｓｐ型半導体装置及びその製造方法
US5869895A (en) 1997-12-15 1999-02-09 Micron Technology, Inc. Embedded memory assembly
DE19927747C1 (de) * 1999-06-17 2000-07-06 Siemens Ag Multichipmodul aus einem zusammenhängenden Waferscheibenteil für die LOC-Montage sowie Verfahren zu dessen Herstellung
US20040108580A1 (en) * 2002-12-09 2004-06-10 Advanpack Solutions Pte. Ltd. Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture
TWI237889B (en) * 2004-01-16 2005-08-11 Optimum Care Int Tech Inc Chip leadframe module
JP4770514B2 (ja) * 2006-02-27 2011-09-14 株式会社デンソー 電子装置
US20080157307A1 (en) * 2006-12-28 2008-07-03 Semiconductor Manufacturing International (Shanghai) Corporation Lead frame
US8174099B2 (en) * 2008-08-13 2012-05-08 Atmel Corporation Leadless package with internally extended package leads

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582013B2 (ja) * 1991-02-08 1997-02-19 株式会社東芝 樹脂封止型半導体装置及びその製造方法
US5138438A (en) * 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
US4937656A (en) * 1988-04-22 1990-06-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
US5296737A (en) * 1990-09-06 1994-03-22 Hitachi, Ltd. Semiconductor device with a plurality of face to face chips
US5206536A (en) * 1991-01-23 1993-04-27 Texas Instruments, Incorporated Comb insert for semiconductor packaged devices
JPH04340267A (ja) * 1991-05-16 1992-11-26 Sony Corp 半導体装置
JPH04348057A (ja) * 1991-05-25 1992-12-03 Sony Corp 樹脂封止型半導体装置
JP2634516B2 (ja) * 1991-10-15 1997-07-30 三菱電機株式会社 反転型ｉｃの製造方法、反転型ｉｃ、ｉｃモジュール
JP2509422B2 (ja) * 1991-10-30 1996-06-19 三菱電機株式会社 半導体装置及びその製造方法
JPH05299456A (ja) * 1992-04-20 1993-11-12 Toshiba Corp 樹脂封止型半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100819799B1 (ko) * 2005-02-22 2008-04-07 삼성테크윈 주식회사 다열리드형 반도체 패키지 제조 방법

Also Published As

Publication number Publication date
KR100292036B1 (ko) 2001-09-17
US5559305A (en) 1996-09-24
JPH07153904A (ja) 1995-06-16
JP2800967B2 (ja) 1998-09-21

Similar Documents

Publication Publication Date Title
US6720666B2 (en) BOC BGA package for die with I-shaped bond pad layout
US6692987B2 (en) BOC BGA package for die with I-shaped bond pad layout
US6277673B1 (en) Leads under chip in conventional IC package
US6355502B1 (en) Semiconductor package and method for making the same
US6855575B2 (en) Semiconductor chip package having a semiconductor chip with center and edge bonding pads and manufacturing method thereof
US20030006055A1 (en) Semiconductor package for fixed surface mounting
KR950007068A (ko) 적층형 반도체 장치의 제조방법 및 그에 따른 반도체 패키지
US20130200507A1 (en) Two-sided die in a four-sided leadframe based package
KR20010022174A (ko) 반도체 장치 및 그 제조방법
US8349655B2 (en) Method of fabricating a two-sided die in a four-sided leadframe based package
US20030038358A1 (en) Semiconductor package without outer leads
KR100220244B1 (ko) 솔더 범프를 이용한 스택 패키지
KR100218335B1 (ko) 칩 사이즈 패키지
KR960005965A (ko) 반도체 장치
KR200154510Y1 (ko) 리드 온 칩 패키지
KR100462373B1 (ko) 칩스케일 패키지 및 그 제조방법
KR940010298A (ko) 반도체 패키지 및 그의 제조방법
KR100567045B1 (ko) 반도체 패키지
JPH06163801A (ja) 樹脂封止型半導体装置
KR20010111602A (ko) 반도체칩과 섭스트레이트 사이의 와이어 본딩 구조 및이를 이용한 반도체패키지, 그리고 그 반도체패키지의제조 방법
KR970053649A (ko) 와이어리스 반도체 패키지
KR940008056A (ko) 반도체 장치 및 그 제조방법
KR19990081577A (ko) 멀티 칩 패키지
KR19980030915A (ko) 칩 스케일 패키지
KR950030209A (ko) 버퍼칩을 이용한 반도체 장치 및 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080303

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee