US20080224283A1 - Leadframe-based semiconductor package and fabrication method thereof - Google Patents
Leadframe-based semiconductor package and fabrication method thereof Download PDFInfo
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- US20080224283A1 US20080224283A1 US11/523,719 US52371906A US2008224283A1 US 20080224283 A1 US20080224283 A1 US 20080224283A1 US 52371906 A US52371906 A US 52371906A US 2008224283 A1 US2008224283 A1 US 2008224283A1
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Abstract
Description
- The present invention relates to semiconductor packages and fabrication methods hereof, and more particularly, to a leadframe-based flip-chip type semiconductor package and a method of fabricating the semiconductor package.
- Conventionally, a semiconductor package using a leadframe as a chip carrier, which is referred to as a leadframe-based semiconductor package, is formed by attaching a non-active surface of a semiconductor chip to a die pad of the leadframe, electrically connecting the semiconductor chip to a plurality of leads of the leadframe via a plurality of bonding wires, and forming an encapsulant to encapsulate the semiconductor chip, the bonding wires and a part of the leadframe. However, this type of semiconductor package usually encounters problems that, for example, electronic signals become weakened due to the length of the bonding wires, and during a molding process of forming the encapsulant, wire loops of the bonding wires tend to be swept or sagged due to impact of mold flow of an encapsulating resin, thereby leading to undesirable contact and short circuit between adjacent bonding wires. Moreover, the leadframe-based semiconductor package cannot be further reduced in thickness as the height of the wire loops of the bonding wires must be considered.
- Accordingly, there has been proposed another leadframe-based semiconductor package using a flip-chip technology. In this semiconductor package, a semiconductor chip is mounted on a leadframe in an upside-down manner that a plurality of conductive bumps implanted to an active surface of the semiconductor chip are bonded and electrically connected to corresponding leads of the leadframe. Consequently, without the use of bonding wires, a path for transmitting electronic signals in the semiconductor package is shortened through the conductive bumps and the quality of electronic signals during transmission is not adversely affected, and further, the semiconductor package can be effectively reduced in height as not having to consider the loop height of the bonding wires.
- However, in the above leadframe-based flip-chip type semiconductor package, the leads of the leadframe are disposed at a peripheral portion of the leadframe, and there is no electrical connection provided at a central portion of the leadframe, such that an issue of not having a sufficient number of electrical connections may arise.
- In order to solve the aforementioned problem, U.S. Pat. No. 6,815,833 proposes a semiconductor package 1 having electrical connections formed at a central portion of a leadframe. As shown in
FIGS. 1A and 1B , the semiconductor package 1 comprises: aleadframe 17 having a plurality ofleads 14 and adie pad 15; asemiconductor chip 11 having anactive surface 112, thesemiconductor chip 11 being mounted and electrically connected to thedie pad 15 and theleads 14 of theleadframe 17 by a plurality ofconductive bumps 12 formed on theactive surface 112 of thesemiconductor chip 11; and anencapsulant 16 for encapsulating a part of theleadframe 17, theconductive bumps 12 and thesemiconductor chip 11, wherein bottom surfaces of theleads 14 and thedie pad 15 are exposed from theencapsulant 16. By this arrangement, theleads 14 of theleadframe 17 serve as input/output (I/O) connections, and thedie pad 15 of theleadframe 17 serves as, for example, an additional power or grounding connection. - U.S. Pat. No. 6,597,059 also proposes a semiconductor package 2 with an increased number of electrical connections. As shown in
FIGS. 2A and 2B , the semiconductor package 2 comprises: aleadframe 27 having a plurality ofleads 24 and twodie pads 25; asemiconductor chip 21 having anactive surface 212, thesemiconductor chip 21 being electrically connected to thecorresponding leads 24 and the twodie pads 25 by a plurality ofconductive bumps 22 formed on theactive surface 212 of thesemiconductor chip 21; and an encapsulant 26 for encapsulating a part of theleadframe 27, theconductive bumps 22 and thesemiconductor chip 21, wherein bottom surfaces of theleads 24 and thedie pads 25 are exposed from the encapsulant 26. By such arrangement, theleads 24 of theleadframe 27 serve as I/O connections, and the twodie pads 25 of theleadframe 27 serve as, for example, two additional power and/or grounding connections. - Although in the above-mentioned packages, it seems beneficial of having the die pad(s) provide one or two additional electrical connections besides the leads of the lead frame, the die pad(s) may only serve as power or grounding connection(s) but not I/O connection(s) because a plurality of conductive bumps are electrically connected thereto, such that this arrangement still does not fulfill the need of sufficient I/O connections for a highly integrated semiconductor chip with high electrical performance and multi-functionality. Therefore, the problem to be solved here is to provide a semiconductor package with an increased number of I/O connections so as to enhance the electrical performance of the semiconductor package.
- In view of the foregoing drawbacks of the prior art, a primary objective of the present invention is to provide a leadframe-based semiconductor package and a fabrication method thereof, which can increase the number of I/O connections of the semiconductor package.
- Another objective of the present invention is to provide a leadframe-based semiconductor package and a fabrication method thereof, which can enhance the heat dissipating efficiency, improve the electrical performance and increase the number of I/O connections of the semiconductor package.
- In order to achieve the foregoing and other objectives, the present invention proposes a leadframe-based semiconductor package, comprising: a leadframe having a plurality of leads; a chip mounted on the leadframe, wherein the chip has an active surface defined with a first region and a second region surrounded by the first region; a plurality of first conductive bumps implanted to the first region of the active surface of the chip, for electrically connecting the chip to the leads of the leadframe; a plurality of second conductive bumps implanted to the second region of the active surface of the chip, for electrically connecting the chip directly to an external device; and an encapsulant for encapsulating the chip, the first conductive bumps, the second conductive bumps and the leadframe, wherein a bottom surface of each of the leads and a bottom end of each of the second conductive bumps are exposed from the encapsulant.
- The bottom ends of the second conductive bumps may be exposed by performing a grinding process on the encapsulant and the bottom surfaces of the leads, such that the second conductive bumps act as additional electrical connections for the semiconductor package.
- As such, the chip can be electrically connected to the external device via the first conductive bumps and the leads of the leadframe, and may further be electrically connected directly to the external device by the second conductive bumps, such that the number of electrical connections for the semiconductor package is increased by means of the second conductive bumps. The additional electrical connections provided by the second conductive bumps implanted to the second region of the active surface of the chip not only may serve as grounding or power connections but also may function as signal I/O connections for the chip, thereby desirably increasing the number of I/O connections for the semiconductor package. This solves the problem of not able to increase the number of I/O connections as in the prior art.
- Further, the chip in the semiconductor package may have a redistribution layer for redistributing bond pads of the chip to the first and second regions of the active surface of the chip, such that the first conductive bumps can be implanted to the first region of the active surface of the chip and the second conductive bumps can be implanted to the second region of the active surface of the chip, so as to desirably increase the overall number of I/O connections for the semiconductor package.
- Moreover, besides the plurality of leads, the leadframe of the semiconductor package can also comprise a conductive pad (die pad), such that a portion of the second conductive bumps implanted to the second region of the chip can be attached to and electrically connected to the conductive pad to serve as grounding or power connections. The rest of the second conductive bumps, which are not attached to the conductive pad, are exposed from the encapsulant and serve as I/O connections.
- The present invention also proposes a fabrication method of the foregoing leadframe-based semiconductor package, comprising the steps of: preparing a leadframe and a chip, the leadframe having a plurality of leads and the chip having an active surface defined with a first region and a second region surrounded by the first region, wherein a plurality of first conductive bumps are implanted on the first region of the active surface of chip and a plurality of second conductive bumps are implanted on the second region of the active surface of the chip; attaching and electrically connecting the first conductive bumps on the chip to the corresponding leads of the leadframe; forming an encapsulant to encapsulate the chip, the first and second conductive bumps and the leadframe; and performing a grinding process on the encapsulant and bottom surfaces of the leads so as to expose the second conductive bumps from the encapsulant.
- The above fabrication method of the semiconductor package further comprises: forming a redistribution layer on the active surface of the chip, for redistributing bond pads of the chip to the first region and the second region of the chip. This allows the bond pads, if not disposed at proper positions on the chip originally, to be redistributed to the proper positions where the first conductive bumps can be implanted to the first region of the chip and correspond in position to the leads and the second conductive bumps can be implanted to the second region of the chip and subsequently exposed from the encapsulant to serve as additional I/O connections for the semiconductor package.
- The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
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FIG. 1A (PRIOR ART) is a plane view of a leadframe-based semiconductor package disclosed by U.S. Pat. No. 6,815,833; -
FIG. 1B (PRIOR ART) is a cross-sectional view of the leadframe-based semiconductor package disclosed by U.S. Pat. No. 6,815,833; -
FIG. 2A (PRIOR ART) is a plane view of a leadframe-based semiconductor package disclosed by U.S. Pat. No. 6,597,059; -
FIG. 2B (PRIOR ART) is a cross-sectional view of the leadframe-based semiconductor package disclosed by U.S. Pat. No. 6,597,059; -
FIG. 3A is a plane view of a semiconductor package according to a first preferred embodiment of the present invention; -
FIG. 3B is a cross-sectional view of the semiconductor package ofFIG. 3A taken alongline 3B-3B; -
FIGS. 4A to 4F are schematic diagrams showing the steps of a fabrication method of the semiconductor package according to the first preferred embodiment of the present invention; -
FIG. 5A is a plane view of a semiconductor package according to a second preferred embodiment of the present invention; and -
FIG. 5B is a cross-sectional view of the semiconductor package ofFIG. 5A taken alongline 5B-5B. - Preferred embodiments of a semiconductor package and a fabrication method thereof as proposed in the present invention are described as follows with reference to
FIGS. 3A to 3B , 4A to 4F and 5A to 5B. - The following embodiments are exemplified by a Flip-Chip Quad Flat Non-Leads (FC-QFN) semiconductor package and a fabrication method thereof. It should be understood that the drawings are simplified schematic diagrams only showing the elements relevant to the present invention, and the layout of elements could be more complicated in practical implementation.
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FIGS. 3A and 3B are respectively a plan view and a cross-sectional view of a semiconductor package 3 according to a first preferred embodiment of the present invention. As shown inFIGS. 3A and 3B , the semiconductor package 3 comprises: aleadframe 30, achip 31 mounted on theleadframe 30, and anencapsulant 32 for encapsulating theleadframe 30 and thechip 31. Theleadframe 30 comprises a plurality ofleads 300, wherein aninner end 300 a of each of theleads 300 is directed toward a center of theleadframe 30, and the inner ends 300 a of theleads 300 define and surround aspacing 300 b. Each of theleads 300 further has atop surface 300 c and an oppositebottom surface 300 d. Theleadframe 30 may be made of a metallic material, such as copper or an alloy thereof. Theleadframe 30 can be formed by any suitable conventional method such as punching, etching, or the like. - The
chip 31 has anactive surface 310 on which a redistribution layer (RDL, not shown) is formed. The redistribution layer is used to redistribute a plurality of electrical connections such asbond pads 311 on thechip 31 to desirable positions on theactive surface 310. As the formation of the redistribution layer is conventional and well known to persons skilled in the art, detailed description thereto and physical indication thereof in the drawings are herein omitted. Theactive surface 310 of thechip 31 is further defined with afirst region 310 a (e.g. a peripheral region as shown) and asecond region 310 b (e.g. a central region as shown) surrounded by thefirst region 310 a, such that a portion of thebond pads 311 are positioned within thefirst region 310 a and the rest of thebond pads 311 are positioned within thesecond region 310 b. - A plurality of first
conductive bumps 33, for serving as I/O connections for thechip 31, are implanted to thecorresponding bond pads 311 located within thefirst region 310 a of theactive surface 310 of thechip 31, such that when thechip 31 is mounted on theleadframe 30, each of the firstconductive bumps 33 is bonded to thetop surface 300 c of a corresponding one of theleads 300. Accordingly, thechip 31 is electrically connected to theleads 300 of theleadframe 30 by the firstconductive bumps 33. - In addition to the first
conductive bumps 33, a plurality of secondconductive bumps 34 are implanted to thecorresponding bond pads 311 located within thesecond region 310 b and are received in thespacing 300 b of theleadframe 30. The secondconductive bumps 34 are used for serving as power connections, grounding connections, heat-dissipating connections, and/or I/O connections for thechip 31, such that thechip 31 can be directly electrically connected to an external device, such as a printed circuit board (not shown), by the second conductive bumps 34. In order to establish the direct connection relationship with the external device, the secondconductive bumps 34 are required to be exposed from theencapsulant 32. Accordingly, an exposed portion (e.g. a bottom end) of each of the secondconductive bumps 34 is made to be flush with the bottom surfaces 300 d of theleads 300 and alower surface 320 of theencapsulant 32. This thus allows the exposed portions of the secondconductive bumps 34 and the bottom surfaces 300 d of theleads 300 to be electrically connected to the external device in a coplanar manner. - Further, the height of each of the second
conductive bumps 34 has to be greater than that of each of the firstconductive bumps 33, so as for the secondconductive bumps 34 to be exposed from theencapsulant 32. That is, the height of each of the secondconductive bumps 34 has to be equal to the sum of the height of each of the firstconductive bumps 33 and the thickness of each of theleads 300. - Also, for the sake of further enhancing the bonding strength between the
leadframe 30 and theencapsulant 32, theinner end 300 a of each of theleads 300 may additionally be etched or punched from thebottom surface 300 d to form arecess 300 e. Thus, theleads 300 can be anchored into theencapsulant 32 by allowing theencapsulant 32 to fill therecesses 300 e of theleads 300. - It is thus clear that the semiconductor package 3 of the present invention, with provision of the second
conductive bumps 34 bonded to thechip 31, has an increased number of I/O connections than that of the prior art, such that the electrical performance of the semiconductor package 3 is enhanced. - The semiconductor package 3 of the present invention can be fabricated by a method shown in
FIGS. 4A to 4F . - As shown in
FIGS. 4A and 4B , asemiconductor chip 31 having anactive surface 310 is prepared. A plurality ofbond pads 311, such as I/O connections, power connections, grounding connections and so on, are formed on theactive surface 310 of thechip 31. Theactive surface 310 is defined with afirst region 310 a and asecond region 310 b surrounded by thefirst region 310 a, wherein a portion of thebond pads 311 are disposed within thefirst region 310 a and the rest of thebond pads 311 are disposed within thesecond region 310 b by means of a redistribution technology. As shown inFIG. 4C , a plurality of firstconductive bumps 33 are implanted on thebond pads 311 formed in thefirst region 310 a of theactive surface 310 of thechip 31 to serve as I/O connections for thechip 31, and a plurality of secondconductive bumps 34 are implanted on thebond pads 311 formed in thesecond region 310 b of theactive surface 310 of thechip 31 to serve as electrical connections such as power connections, grounding connections and/or I/O connections. The height of each of the secondconductive bumps 34 is greater than that of each of the firstconductive bumps 33. - As shown in
FIG. 4D , aleadframe 30, which can be made of copper or an alloy thereof, is provided. Theleadframe 30 comprises a plurality ofleads 300, wherein each of theleads 300 has aninner end 300 a directed toward a center of theleadframe 30, with aspacing 300 b being defined and surrounded by the inner ends 300 a of theleads 300. Further, each of theleads 300 has atop surface 300 c and an oppositebottom surface 300 d. Thechip 31 is mounted to theleadframe 30 by having each of the firstconductive bumps 33 bonded to thetop surface 300 c of a corresponding one of theleads 300. As shown inFIG. 4E , anencapsulant 32 is formed for encapsulating thechip 31, the firstconductive bumps 33, the secondconductive bumps 34 and theleadframe 30, with the bottom surfaces 300 d of theleads 300 being exposed from theencapsulant 32. - As shown in
FIG. 4F , a grinding process is carried out to grind the bottom surfaces 300 d of theleads 300 and alower surface 320 of theencapsulant 32 until a desired portion (e.g. a bottom end 340) of each of the secondconductive bumps 34 is exposed from theencapsulant 32. By such processing, the bottom ends 340 of the secondconductive bumps 34 are flush with the bottom surfaces 300 d of theleads 300 and thelower surface 320 of theencapsulant 32. This thus completes the fabrication of the semiconductor package 3 shown inFIGS. 3A and 3B . Since the grinding process is performed, the final thickness of the fabricated semiconductor package 3 can be reduced to a desired extent. - The foregoing fabrication method of the semiconductor package of the present invention may optionally comprise a step of plating the bottom surfaces 300 d of the
leads 300 with a solder layer (not shown) following the completion of the grinding process, such that the semiconductor package 3 can be electrically connected to an external device such as a printed circuit board via the solder layer and the secondconductive bumps 34 exposed from theencapsulant 32. -
FIGS. 5A and 5B are respectively a plane view and a cross-sectional view of a semiconductor package according to a second preferred embodiment of the present invention. The semiconductor package of the second embodiment is similar to that of the first embodiment, with a primary difference in that the leadframe further comprises at least one conductive pad (die pad) formed in a central portion of the leadframe and spaced apart from a plurality of leads formed in a peripheral portion of the leadframe. - Particularly, as shown in
FIGS. 5A and 5B , the semiconductor package 5 of the second embodiment comprises: aleadframe 50, achip 51 attached to theleadframe 50, and anencapsulant 52 for encapsulating theleadframe 50 and thechip 51. Theleadframe 50 includes a plurality ofleads 500, and adie pad 501 spaced apart from and surrounded by the plurality of leads 500. Each of theleads 500 has atop surface 500 a and an oppositebottom surface 500 b, and thedie pad 501 has atop surface 501 a and an oppositebottom surface 501 b. And between theleads 500 and thedie pad 501 there is formed aspacing 502 with a predetermined width. - The
chip 51 has anactive surface 510, wherein theactive surface 510 is defined with afirst region 510 a, asecond region 510 b within thefirst region 510 a, and athird region 510 c within thesecond region 510 b. A plurality ofbond pads 511 are formed on theactive surface 510 and disposed within thefirst region 510 a, thesecond region 510 b, and thethird region 510 c. By such arrangement, a plurality of firstconductive bumps 53 can be implanted on thebond pads 511 located within thefirst region 510 a, a plurality of secondconductive bumps 54 can be implanted on thebond pads 511 located within thesecond region 510 b, and a plurality of thirdconductive bumps 55 can be implanted on thebond pads 511 located within thethird region 510 c. Thechip 51 is attached to theleadframe 50 via theactive surface 510 in a manner that the firstconductive bumps 53 are bonded to thetop surfaces 500 a of theleads 500, the secondconductive bumps 54 are received in thespacing 502, and the thirdconductive bumps 55 are bonded to thetop surface 501 a of thedie pad 501. Thus, thechip 51 is electrically connected to theleadframe 50 by the firstconductive bumps 53 and the thirdconductive bumps 55. - The second
conductive bumps 54 are greater in height than the first and thirdconductive bumps encapsulant 52, bottom ends 540 of the secondconductive bumps 54 are exposed from theencapsulant 52 and are used to electrically connect thechip 51 to an external device such as a printed circuit board. Likewise, the bottom surfaces 500 b of theleads 500 and thebottom surface 501 b of thedie pad 501 are also exposed from theencapsulant 52 and are coplanar with the bottom ends 540 of the second conductive bumps 54. Thus, thedie pad 501 may act as a power connection, a grounding connection and/or a heat-dissipating connection for thechip 51, and the secondconductive bumps 54 may act as I/O connections for thechip 51. As such, desired multi-functionality, electrical performance and heat dissipating efficiency for the semiconductor package 5 can be achieved. - The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. For example, a non-active surface of the chip opposing to the active surface thereof may be exposed from an upper surface of the encapsulant opposing to the lower surface thereof, allowing the exposed non-active surface of the chip to be optionally adhered to a heat spreader in order to enhance the heat dissipating performance of the semiconductor package. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (20)
Priority Applications (1)
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US13/214,076 US8420452B2 (en) | 2005-09-20 | 2011-08-19 | Fabrication method of leadframe-based semiconductor package |
Applications Claiming Priority (2)
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TW094132399A TWI263351B (en) | 2005-09-20 | 2005-09-20 | Semiconductor package and fabrication method thereof |
TW094132399 | 2005-09-20 |
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US13/214,076 Division US8420452B2 (en) | 2005-09-20 | 2011-08-19 | Fabrication method of leadframe-based semiconductor package |
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US20080224283A1 true US20080224283A1 (en) | 2008-09-18 |
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US11/523,719 Abandoned US20080224283A1 (en) | 2005-09-20 | 2006-09-20 | Leadframe-based semiconductor package and fabrication method thereof |
US13/214,076 Active US8420452B2 (en) | 2005-09-20 | 2011-08-19 | Fabrication method of leadframe-based semiconductor package |
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US13/214,076 Active US8420452B2 (en) | 2005-09-20 | 2011-08-19 | Fabrication method of leadframe-based semiconductor package |
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Cited By (10)
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US20080283984A1 (en) * | 2007-05-14 | 2008-11-20 | Advanced Semiconductor Engineering, Inc. | Package structure and manufacturing method thereof |
US20130049182A1 (en) * | 2011-08-31 | 2013-02-28 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
US20130049217A1 (en) * | 2011-08-31 | 2013-02-28 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
CN103107152A (en) * | 2011-11-11 | 2013-05-15 | 台湾积体电路制造股份有限公司 | Bumps for chip scale packaging |
US8597983B2 (en) | 2011-11-18 | 2013-12-03 | Freescale Semiconductor, Inc. | Semiconductor device packaging having substrate with pre-encapsulation through via formation |
US20200075523A1 (en) * | 2018-08-29 | 2020-03-05 | Texas Instruments Incorporated | Integrated circuits with conductive bumps having a profile with a wave pattern |
CN112204732A (en) * | 2018-05-31 | 2021-01-08 | 华为技术有限公司 | Circuit board and mobile terminal |
US11355470B2 (en) * | 2020-02-27 | 2022-06-07 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and methods of manufacturing semiconductor devices |
US11444048B2 (en) * | 2017-10-05 | 2022-09-13 | Texas Instruments Incorporated | Shaped interconnect bumps in semiconductor devices |
US20230068329A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
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US11291146B2 (en) | 2014-03-07 | 2022-03-29 | Bridge Semiconductor Corp. | Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same |
KR101892876B1 (en) * | 2017-12-01 | 2018-08-28 | 삼성전기주식회사 | Fan-out semiconductor package |
TWI749465B (en) * | 2020-02-14 | 2021-12-11 | 聚積科技股份有限公司 | Transfer packaging method of integrated circuit |
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US7816773B2 (en) * | 2007-05-14 | 2010-10-19 | Advanced Semiconductor Engineering, Inc. | Package structure and manufacturing method thereof |
US20080283984A1 (en) * | 2007-05-14 | 2008-11-20 | Advanced Semiconductor Engineering, Inc. | Package structure and manufacturing method thereof |
US8916421B2 (en) * | 2011-08-31 | 2014-12-23 | Freescale Semiconductor, Inc. | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
US20130049182A1 (en) * | 2011-08-31 | 2013-02-28 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
US20130049217A1 (en) * | 2011-08-31 | 2013-02-28 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
US9142502B2 (en) * | 2011-08-31 | 2015-09-22 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
US9553065B2 (en) | 2011-11-11 | 2017-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bumps for chip scale packaging including under bump metal structures with different diameters |
CN103107152A (en) * | 2011-11-11 | 2013-05-15 | 台湾积体电路制造股份有限公司 | Bumps for chip scale packaging |
US8597983B2 (en) | 2011-11-18 | 2013-12-03 | Freescale Semiconductor, Inc. | Semiconductor device packaging having substrate with pre-encapsulation through via formation |
US11444048B2 (en) * | 2017-10-05 | 2022-09-13 | Texas Instruments Incorporated | Shaped interconnect bumps in semiconductor devices |
CN112204732A (en) * | 2018-05-31 | 2021-01-08 | 华为技术有限公司 | Circuit board and mobile terminal |
US20200075523A1 (en) * | 2018-08-29 | 2020-03-05 | Texas Instruments Incorporated | Integrated circuits with conductive bumps having a profile with a wave pattern |
US10847483B2 (en) * | 2018-08-29 | 2020-11-24 | Texas Instruments Incorporated | Integrated circuits with conductive bumps having a profile with a wave pattern |
US11855027B2 (en) | 2018-08-29 | 2023-12-26 | Texas Instruments Incorporated | Integrated circuits with conductive bumps having a profile with a wave pattern |
US11355470B2 (en) * | 2020-02-27 | 2022-06-07 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and methods of manufacturing semiconductor devices |
US20230068329A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
TWI263351B (en) | 2006-10-01 |
US20110300671A1 (en) | 2011-12-08 |
TW200713613A (en) | 2007-04-01 |
US8420452B2 (en) | 2013-04-16 |
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