TWI447873B - 封裝件結構、封裝基板結構及其製法 - Google Patents

封裝件結構、封裝基板結構及其製法 Download PDF

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Publication number
TWI447873B
TWI447873B TW100147660A TW100147660A TWI447873B TW I447873 B TWI447873 B TW I447873B TW 100147660 A TW100147660 A TW 100147660A TW 100147660 A TW100147660 A TW 100147660A TW I447873 B TWI447873 B TW I447873B
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layer
region
wire
conductive
crystallizing
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TW100147660A
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TW201327743A (zh
Inventor
陳嘉音
劉玉菁
張月瓊
王愉博
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矽品精密工業股份有限公司
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Priority to TW100147660A priority Critical patent/TWI447873B/zh
Priority to CN201210034131.2A priority patent/CN103178034B/zh
Priority to US13/490,810 priority patent/US8901729B2/en
Publication of TW201327743A publication Critical patent/TW201327743A/zh
Application granted granted Critical
Publication of TWI447873B publication Critical patent/TWI447873B/zh
Priority to US14/531,226 priority patent/US9269677B2/en

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Description

封裝件結構、封裝基板結構及其製法
本發明係關於封裝件結構、封裝基板結構及其製法，特別是關於一種以打線方式電性連接晶片之封裝件結構、封裝基板結構及其製法。
在現行以銲線電性連接半導體晶片並承載該半導體晶片之封裝基板或導線架之結構中，該半導體晶片的表面上係形成有電極墊(electronic pad)，該封裝基板亦具有相對應的打線墊，而導線架係具有相對應的導腳；將該晶片接置於該封裝基板之置晶區上或導線架之置晶座上後，乃以銲線(金線)電性連接晶片之電極墊與封裝基板之打線墊或導線架之導腳，以電性連接晶片與封裝基板或導線架。
有關以封裝基板作載件之封裝製程中，一般於打線製程之前，會先於該封裝基板之打線墊上電鍍如鎳/金材之表面處理層，以提昇該金線與該打線墊之間的電性耦合結合力，且可防止該打線墊氧化。而目前電鍍表面處理層之製程種類繁多，大致可分為有電鍍線與無電鍍線。
如第1A及1A’圖所示，係為習知有電鍍線之電鍍製程，係於一具有置晶區A與線路層11之基板本體10上先形成一絕緣保護層12，且該絕緣保護層12形成有複數開孔120，以令各該打線墊110外露於各該開孔120。其中，該線路層11具有複數導電跡線11a與複數導電盲孔11b，各該導電跡線11a具有鄰近該置晶區A之打線墊110與遠離該置晶區A之一端以連接導電盲孔11b，連接該導電盲孔11b之一端並具有延伸至基板本體10邊緣之電鍍線111，再將該基板本體10每一側之複數電鍍線111連接至一電鍍匯流排(或稱共用電鍍導線，圖未示)。
接著，將具有呈矩陣式排列之複數基板本體10構成之版面置入電鍍槽(圖未示)中，進行電鍍製程，使電流通過各該電鍍匯流排，以經由各該電鍍線111分別輸送電流，而於各該打線墊110上以形成表面處理層14，再移除各該電鍍匯流排。
然而，習知電鍍製程中，需於各該導電跡線11a上設計一電鍍線111，而於電鍍製程完成後，各該電鍍線111仍保留於該基板本體10邊緣上，故當封裝基板結構1應用於高頻且電性效能較大的產品時，各該導電跡線11a之訊號傳遞容易受到該些電鍍線111之相互干擾而造成串音(cross-talk)現象，致使產品發生訊號傳輸失真或不佳之問題。
因此，業界遂提出一種無電鍍線(no plating line,NPL)之電鍍方法，可參閱本國專利第I223426號或如第1B圖所示，係先在一基板本體10’上覆蓋一導電膜13，再於該導電膜13上形成第一阻層12a，以電鍍形成線路層11’；然後再形成第二阻層12b；接著，藉由導電膜13進行電鍍製程，以於該打線墊110’上電鍍形成表面處理層14’；之後移除該第一與第二阻層12a,12b及其所覆蓋之導電膜13。藉由導電膜13取代複數電鍍線，以避免發生串音現象。
惟，習知無電鍍線之電鍍方法中，需進行兩次阻層之圖案化製程，因阻層及光罩之材料費與曝光、顯影製程所用之設備費均非常昂貴，導致NPL製程之製作成本過高，且製程冗長，故不符合經濟效益。
之後進行接置晶片16製程於封裝基板上時，會先於該置晶區A之絕緣保護層12上形成膠層15以結合該晶片16。然而，以第1A’圖為例，當晶片16壓合該膠層15時，該膠層15會受到該晶片16擠壓而向外溢出，因而污染位於該置晶區A周圍之打線墊110，導致封裝基板結構1之電性連接不良。
又，若增加該打線墊110與該置晶區A之間的距離D，雖可避免該打線墊110受到膠材之污染，但需增加該基板本體10之面積而使封裝基板結構1無法滿足微小化之需求，且因須佈設電鍍線111而縮小該線路層11之佈線空間而限制佈線之彈性化。
另外，增加該打線墊110與該置晶區A之間的距離D，勢必增加打線製程之金線(圖未示)長度，因而提高材料成本，而使產品製造成本增加。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明之其中一目的係提供一種封裝件結構、封裝基板結構及其製法，以避免串音現象發生。
本發明之另一目的係提供一種封裝件結構、封裝基板結構及其製法，以降低成本、滿足微小化之需求與提升佈線之彈性化。
本發明所述之封裝件結構，係包括：基板本體，係具有置晶區；線路層，係設於該基板本體上，且具有複數導電跡線，各該導電跡線具有鄰近該置晶區之第一端與遠離該置晶區之第二端，該第一端係具有打線墊，且對應該置晶區至少一側邊之導電跡線之第二端連結有電鍍線，又該置晶區側邊的電鍍線之數量與同一置晶區側邊的打線墊之數量不相等；表面處理層，係形成於該打線墊上；以及晶片，係藉由膠層結合於該置晶區上，並以複數銲線電性連接各該打線墊與該晶片。
本發明所述之封裝基板結構，係包括：基板本體，係具有置晶區；線路層，係設於該基板本體上，且具有複數導電跡線，各該導電跡線具有鄰近該置晶區之第一端與遠離該置晶區之第二端，該第一端係具有打線墊，且對應該置晶區至少一側邊之導電跡線之第二端連結有電鍍線，又該置晶區側邊的電鍍線之數量與同一置晶區側邊的打線墊之數量不相等；以及表面處理層，係形成於該打線墊上。
本發明所述之封裝基板結構之製法，係包括：提供一基板本體，該基板本體上具有置晶區與位於該置晶區周圍之線路層，該線路層具有複數導電跡線，各該導電跡線具有相對之第一端與第二端，各該導電跡線之第一端係具有打線墊，且對應該置晶區至少一側邊之導電跡線之第二端連結有電鍍線，又該置晶區側邊的電鍍線之數量與同一置晶區側邊的打線墊之數量不相等；形成導電層於該置晶區邊緣，且該導電層位於該置晶區與該線路層之間，並令該導電層電性連接各該導電跡線；藉該導電層與該電鍍線，於各該打線墊上電鍍形成表面處理層；以及移除該導電層。
前述之製法中，各該導電跡線之第一端係鄰近該置晶區，且該第二端係遠離該置晶區
前述之製法中，該導電層之移除係可以雷射、化學液或刮刀移除方式為之。
前述之製法中，該些打線墊可連結有延伸線以連接該導電層。
前述之封裝基板結構及其製法，復可形成膠層於該置晶區上，以供晶片藉該膠層黏置於該置晶區上，且該晶片藉由複數銲線電性連接該打線墊。
前述之封裝件結構、封裝基板結構及其製法中，該置晶區側邊的電鍍線之數量可少於同一置晶區側邊的打線墊之數量，例如：該置晶區側邊之打線墊中僅有一者對應之第二端連結有電鍍線。
前述之封裝件結構、封裝基板結構及其製法，復可於移除該導電層時，一併形成對應該導電層位置之凹槽，使該凹槽位於該置晶區與該線路層之間，且該打線墊連結有延伸線以連通該凹槽。
前述之封裝件結構、封裝基板結構及其製法，復可形成接地部於該基板本體上。
另外，前述之封裝件結構、封裝基板結構及其製法，於形成該導電層之後，且於電鍍形成該表面處理層之前，復可包括形成絕緣保護層於該基板本體與該線路層上，且該絕緣保護層形成有複數開孔，以令各該打線墊外露於各該開孔。
由上可知，本發明封裝件結構、封裝基板結構及其製法，係藉由在置晶區周圍形成有電鍍用與防溢膠用之凹槽，使該凹槽中之導電層可連通所有之導電跡線，故只需於其中一導電跡線上設計電鍍線，即可於各該打線墊上電鍍形成表面處理層，因而於該基板本體上僅殘留有一電鍍線，使各該導電跡線之訊號傳遞不會受到相鄰之電鍍線之干擾，而可避免發生串音現象，以克服產品訊號傳輸失真或不佳之問題。
再者，當晶片壓合該膠層時，該膠層會受晶片擠壓，此時，受擠壓而溢出之膠材則會流入該凹槽中，因而可避免膠材污染打線墊而影響打線接合及電性之可靠度問題。
又，因凹槽之設計，而無需增加該打線墊與該置晶區之間的距離，故不需增加該基板本體之面積而使封裝基板結構可滿足微小化之需求，且因僅須佈設少許電鍍線而可保持該線路層之佈線空間而可提升佈線之彈性化。另外，亦無須增加打線製程之金線長度，因而可降低材料成本，使製造成本降低。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“上側”、“二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2E圖，係為本發明之封裝基板結構之製法之剖面示意圖。
如第2A及2A’圖所示，一基板本體20上具有一置晶區A、位於該置晶區A周圍之線路層21、及位於該置晶區A與該線路層21之間的導電層23。
再者，該線路層21具有複數導電跡線21a與複數導電盲孔21b，各該導電跡線21a具有鄰近該置晶區A之第一端210a與遠離該置晶區A之第二端210b，各該第一端210a係具有打線墊210，且該些打線墊210連結有延伸線212，各該第二端210b係連接該導電盲孔21b，並於對應該置晶區A各側之導電跡線21a中，僅於其中一側(如第2A’圖所示之上側)之其中一導電跡線21a之第二端210b具有電鍍線211，而於其他導電跡線21a之第二端210b上未形成有電鍍線。
又，該電鍍線211之數量係位於該置晶區A之四側共一條，如第2A’圖所示。惟佈設該電鍍線211之數量係不限定此種類型，可依後續電鍍製程需要佈設所需數量之電鍍導線。
另外，該導電層23連接各該導電跡線21a之延伸線212，以令所有之導電跡線21a連接至同一導電層23。該導電層23係作為後述電鍍金屬材料所需之電流傳導路徑，且該導電層23可為電鍍銅、金屬、合金或沉積數層金屬層、或導電高分子材料。該導電層23可為一環形(如第2A’圖所示)或複數對應置晶區A各邊之長條狀(圖未示)，並無特別限制，只需將複數條之導電跡線連接至單一導電層即可，例如：置晶區之其中一側的複數導電跡線連接至單一導電層。前述導電層23最佳為以電鍍製程形成導電跡線時，同時電鍍形成導電層23，以省去另外以其他製程或材質形成導電層23之時間與成本。
於其他實施例中，該導電跡線21a之打線墊210亦可直接連接該導電層23，而不需藉由延伸線212。
如第2B及2B’圖所示，於該基板本體20與該線路層21上形成一絕緣保護層22，且該絕緣保護層22形成有複數開孔220，以令各該打線墊210與該導電層23外露於各該開孔220。而前述之絕緣保護層22亦可形成開孔220僅顯露打線墊210，而無須顯露導電層23，其可依佈設需求做不同設計。
如第2C圖所示，將該基板本體20之電鍍線211連接至一電鍍匯流排(或稱共用電鍍導線，圖未示)。再將具有呈矩陣式排列之複數基板本體20構成之版面置入電鍍槽(圖未示)中，進行電鍍製程，使電流通過各該電鍍匯流排，以經由該電鍍線211輸送電流至導電層23，而於各該打線墊210上電鍍形成表面處理層24。接著，移除該電鍍匯流排。
於本實施例中，形成該表面處理層24之材質係為鎳/金(Ni/Au)、化鎳鈀浸金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、及直接浸金(Direct Immersion Gold,DIG)之其中一者。
再者，將該導電層23設計為一環形，只須進行一次電鍍製程，可節省製程步驟與時間；若將該導電層23設計為複數長條狀，因置晶區A各邊分別進行電鍍，故有利於檢測與修補電鍍品質，以提升產品可靠度。
如第2D圖所示，移除該導電層23。於本實施例中，係以雷射燒灼之方式移除該導電層23，而於其他實施例中，亦可用化學液或刮刀移除該導電層23。
再者，於移除該導電層23時，可依需求同時形成對應該導電層23位置之凹槽200。
本發明之製法藉由在該置晶區A與該線路層21之間形成導電層23，使該導電層23連通該線路層21所有之導電跡線21a，故只需於該置晶區A之其中一側之其中一導電跡線21a上設計電鍍線211，即可於各該打線墊210上電鍍形成該表面處理層24。因此，相較於習知技術，本發明封裝基板結構2不需每一導電跡線21a上均設計相對應之電鍍線，故當應用於高頻且電性效能較大的產品時，各側邊之各該導電跡線21a之訊號傳遞不會受到單一電鍍線211之干擾，而可避免發生串音現象，以克服產品訊號傳輸失真或不佳之問題。
再者，本發明之製法無需進行如NPL製程中之阻層圖案化步驟，故可省去阻層及光罩材料費與曝光、顯影製程所用之設備費，因而可大幅降低製作成本，且縮短製程時程，以符合經濟效益。
如第2E圖所示，形成膠層25於該置晶區A上，以接置一晶片26，俾供複數如金線之銲線27電性連接各該打線墊210與該晶片之電極墊260。於本實施例中，該膠層25係銀膠。
若有形成凹槽200，當該晶片26設於該膠層25上時，該膠層25之膠材會受該晶片26擠壓而向外溢出，此時，該溢出之膠材會流入該凹槽200中，而不會流至該打線墊210上，故可克服習知技術中因膠材外溢而污染打線墊的問題。
因此，本發明之製法藉由於移除該導電層23時一併形成該凹槽200，因而無須增加該打線墊210與該置晶區A之間的距離，故不僅因無需增加該基板本體20之面積而使封裝基板結構2可滿足微小化之需求，且因保留該線路層21之佈線空間而可提升佈線之彈性化。
再者，亦無需增加打線製程之銲線27長度，而可降低材料成本，使製造成本降低。
於另一實施例中，如第3及3’圖所示，於移除該導電層23時，可依需求形成二圍繞該置晶區A之環形凹槽300a,300b，且內圈之凹槽300a用以供膠層25之膠材流入，而外圈之凹槽300b可供膠層25之膠材流入以作進一步的防護。
再者，於移除該導電層23時，亦可保留部分導電層23材質，以形成一環狀之接地部31。於本實施例中，該接地部31位於該線路層21(打線墊210)與該置晶區A之間，如：位於該兩環形凹槽300a,300b之間。又，該接地部31之形狀並不限於環狀，且其形成位置亦無特別限制。
另外，該電鍍線311之數量亦可於該置晶區A之一側均一條(共四條)，如第3’圖所示，。
本發明復提供一種封裝基板結構2，係包括：基板本體20、設於該基板本體20上之線路層21、以及形成於該線路層21上之表面處理層24。
所述之基板本體20係具有置晶區A。可依需求於該置晶區A與該線路層21之間設計凹槽200。
所述之線路層21係具有複數導電跡線21a，各該導電跡線21a具有鄰近該置晶區A(或凹槽200)之第一端210a與遠離該置晶區A(或凹槽200)之第二端210b，該第一端210a係具有打線墊210，且該打線墊210具有延伸線212以連通該凹槽200，且對應該置晶區A各側邊之導電跡線21a中僅有一者之第二端210b連結有電鍍線211,311，可共為1至4條。
所述之表面處理層24係形成於該打線墊210上。
所述之封裝基板結構2復包括形成於該置晶區A上之膠層25，以接置晶片26，令該晶片26以銲線27電性連接該打線墊210，以形成一封裝件結構。
於另一實施例中，所述之封裝基板結構3復包括設於該基板本體20上之接地部31，且該接地部31並未連接該線路層21。
綜上所述，本發明之封裝件結構、封裝基板結構及其製法，藉由該導電層連通所有之導電跡線，故只需於少部分之導電跡線上設計電鍍線，即可進行電鍍製程。因此，該封裝基板結構上因僅具有少數電鍍線，而有效避免音串干擾之問題。
再者，因無需進行如NPL製程中之多次阻層圖案化步驟，故可大幅降低製作成本。
又，該凹槽可防止膠材流至打線墊上，故可克服習知技術中因膠材所造成之種種問題，以滿足微小化之需求及使製造成本降低。
此外，僅須佈設少數電鍍線，故可提升導電跡線之佈線彈性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,3．．．封裝基板結構
10,10’,20．．．基板本體
11,11’,21．．．線路層
11a,21a．．．導電跡線
11b,21b．．．導電盲孔
110,110’,210．．．打線墊
111,211,311．．．電鍍線
12,22．．．絕緣保護層
120,220．．．開孔
12a．．．第一阻層
12b．．．第二阻層
13．．．導電膜
14,14’,24．．．表面處理層
15,25．．．膠層
16,26．．．晶片
200,300a,300b．．．凹槽
210a．．．第一端
210b．．．第二端
212．．．延伸線
23．．．導電層
260．．．電極墊
27．．．銲線
31．．．接地部
A．．．置晶區
D．．．距離
第1A圖係為習知封裝基板之上視示意圖；
第1A’圖為習知封裝基板與晶片之剖面示意圖；
第1B圖係為另一習知封裝基板之製法之剖面示意圖；
第2A至2D圖係為本發明之封裝基板結構之製法之剖面示意圖；其中，如第2A’及2B’圖係分別為第2A及2B圖之省略銲線之上視示意圖；
第2E圖係為本發明之封裝件結構之剖面示意圖；其中，第2E’圖係為第2E圖之省略銲線之上視示意圖；以及
第3圖係為本發明之封裝基板結構之另一實施例之剖面示意圖；其中，第3’圖係為第3圖之上視圖。
20．．．基板本體
200．．．凹槽
21．．．線路層
21a．．．導電跡線
21b．．．導電盲孔
210．．．打線墊
211．．．電鍍線
212．．．延伸線
22．．．絕緣保護層
220．．．開孔
24．．．表面處理層
26．．．晶片
A．．．置晶區

Claims (17)

  1. 一種封裝基板結構，係包括：基板本體，係具有置晶區與凹槽；線路層，係設於該基板本體上，且具有複數導電跡線，各該導電跡線具有鄰近該置晶區之第一端與遠離該置晶區之第二端，該第一端係具有打線墊，且對應該置晶區至少一側邊之導電跡線之第二端連結有電鍍線，又該置晶區側邊的電鍍線之數量與同一置晶區側邊的打線墊之數量不相等，其中，該凹槽係位於該置晶區與該線路層之間，該打線墊連結有延伸線以連通該凹槽；以及表面處理層，係形成於該打線墊上。
  2. 一種封裝件結構，係包括：基板本體，係具有置晶區與凹槽；線路層，係設於該基板本體上，且具有複數導電跡線，各該導電跡線具有鄰近該置晶區之第一端與遠離該置晶區之第二端，該第一端係具有打線墊，且對應該置晶區至少一側邊之導電跡線之第二端連結有電鍍線，又該置晶區側邊的電鍍線之數量與同一置晶區側邊的打線墊之數量不相等，其中，該凹槽係位於該置晶區與該線路層之間，該打線墊連結有延伸線以連通該凹槽；表面處理層，係形成於該打線墊上；以及晶片，係藉由膠層結合於該置晶區上，並以複數 銲線電性連接各該打線墊與該晶片。
  3. 如申請專利範圍第1或2項所述之結構，其中，該置晶區側邊的電鍍線之數量少於同一置晶區側邊的打線墊之數量。
  4. 如申請專利範圍第3項所述之結構，其中，該置晶區側邊之打線墊中僅有一者對應之第二端連結有該電鍍線。
  5. 如申請專利範圍第1或2項所述之結構，復包括形成於該基板本體上之接地部。
  6. 如申請專利範圍第1或2項所述之結構，復包括形成於該基板本體與該線路層上之絕緣保護層，係形成有複數開孔，以令各該打線墊外露於各該開孔。
  7. 如申請專利範圍第1項所述之封裝基板結構，復包括形成於該置晶區上用以接置晶片之膠層。
  8. 一種封裝基板結構之製法，係包括：提供一基板本體，該基板本體上具有置晶區與位於該置晶區周圍之線路層，該線路層具有複數導電跡線，各該導電跡線具有相對之第一端與第二端，各該導電跡線之第一端係具有打線墊，且對應該置晶區至少一側邊之導電跡線之第二端連結有電鍍線，又該置晶區側邊的電鍍線之數量與同一置晶區側邊的打線墊之數量不相等；形成導電層於該置晶區邊緣，且該導電層位於該置晶區與該線路層之間，並令該導電層電性連接各該 導電跡線；藉該導電層與該電鍍線，於各該打線墊上電鍍形成表面處理層；以及移除該導電層。
  9. 如申請專利範圍第8項所述之封裝基板結構之製法，其中，各該導電跡線之第一端係鄰近該置晶區，且該第二端係遠離該置晶區。
  10. 如申請專利範圍第8項所述之封裝基板結構之製法，其中，該些打線墊連結有延伸線以連接該導電層。
  11. 如申請專利範圍第8項所述之封裝基板結構之製法，其中，該導電層之移除係以雷射、化學液或刮刀移除方式為之。
  12. 如申請專利範圍第8項所述之封裝基板結構之製法，復包括形成膠層於該置晶區上，以供晶片藉該膠層黏置於該置晶區上，且該晶片藉由複數銲線電性連接該打線墊。
  13. 如申請專利範圍第8項所述之封裝基板結構之製法，復包括形成接地部於該基板本體上。
  14. 如申請專利範圍第8項所述之封裝基板結構之製法，復包括於移除該導電層時，一併形成對應該導電層位置之凹槽。
  15. 如申請專利範圍第8項所述之封裝基板結構之製法，其中，該置晶區側邊的電鍍線之數量少於同一置晶區側邊的打線墊之數量。
  16. 如申請專利範圍第15項所述之封裝基板結構之製法，其中，該置晶區側邊之打線墊中僅有一者對應之第二端連結有該電鍍線。
  17. 如申請專利範圍第8項所述之封裝基板結構之製法，於形成該導電層之後，且於電鍍形成該表面處理層之前，復包括形成絕緣保護層於該基板本體與該線路層上，且該絕緣保護層形成有複數開孔，以令各該打線墊外露於各該開孔。
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