CN1705099A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1705099A
CN1705099A CNA2005100743166A CN200510074316A CN1705099A CN 1705099 A CN1705099 A CN 1705099A CN A2005100743166 A CNA2005100743166 A CN A2005100743166A CN 200510074316 A CN200510074316 A CN 200510074316A CN 1705099 A CN1705099 A CN 1705099A
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semiconductor chip
power line
circuit part
opening
conductor layer
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CN100392843C (zh
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细山田澄和
十和人
久保田义浩
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Socionext Inc
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Fujitsu Ltd
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Abstract

一种半导体器件，包括一半导体芯片，其中在该半导体芯片中心处设置的电路部分与电源线和电源电极连接，以从外部电源向该电路部分供电。衬底被设置为用于在其上承载该半导体芯片，并且被设置为使得在围绕该半导体芯片的区域中设置的第一端子电连接至电源电极。在电路部分中心处的电源线上形成第一开口。在电路部分外围部分的电源线上形成第二开口。导体层电连接至设置于该衬底上围绕半导体芯片区域中的第二端子，并且被设置为使得该第一开口中的电源线与该第二开口中的电源线连接在一起。

Description

半导体器件
相关申请的交叉参考
本申请基于并要求在2004年6月2日提交的日本专利申请号2004-164857的优先权，在此通过参考并入其全部内容。
技术领域
本发明大体上涉及一种半导体器件，更特别地，涉及一种具有电源布线以经由半导体芯片的电源线向半导体芯片的电路部分供应电力的的半导体器件。
背景技术
通常，在使用引线(wire)接合法来安装半导体芯片的半导体器件中，在衬底上承载的半导体芯片外围部分处的电极与在衬底上的接合导线(lead)通过引线等电连接在一起。
在工作时，从半导体芯片外围部分的电极、经由电源线向半导体芯片中心处的电路部分供应电源电流。
图1示出常规半导体器件10的组成。半导体芯片1比如LSI被承载在插入件(interposer)上，该插入件用作由图1中的虚线所示的衬底。半导体芯片1包括形成电路部分的核心部分5，位于核心部分5外围部分处的多个电极焊盘2，以及电源线4。
通过半导体芯片1的电路部分和电源线4，连接多个电极焊盘2中为电源设置的电极焊盘2。通过半导体芯片1的电路部分和电源线4，连接多个电极焊盘2中为接地设置的电极焊盘2。
来自电源(图中未示)的电源电流在工作时经由电源线4从半导体芯片1的外围被供应至半导体芯片1中心处的核心部分5的电路。
在半导体器件1的衬底上，在围绕半导体芯片1的区域中，设置多条接合导线7。在多条接合导线7中用于电源的接合导线7被连接至电源(未示出)，并且在多条接合导线7中用于接地的接合导线7被接地。在衬底上设置的所有接合导线7都通过引线8与半导体芯片1外围的电极焊盘2电接合。
作为公知的关于半导体器件电源布线的方法，日本公开专利申请号03-008360公开了在具有多个布线层的半导体器件中设置的电源布线。该半导体器件具有这样的布线结构，其中多个半导体芯片和电源布线经由通孔连接。
而且，日本公开专利申请号64-089447公开了具有多层互连结构的半导体集成电路器件。为了避免受到集成电路外部的电场和磁场的影响，半导体电路器件被构造为具有这样的布线结构，其中在多个导体层中至少有一个导体层被连接至电源或接地以便整体覆盖衬底上元件(晶体管)的外围。
在图1的常规半导体器件10中，电源电流在工作时经由电源线4被供应至半导体芯片1的核心部分5。然而，会存在这样的趋势，即在核心部分5中心处的供应电压会变得低于核心部分5外围部分处的供应电压。
特别地，在高速工作时，电源电流通过无源元件部分比如电阻器和电感被消耗，并且在核心部分5中心处的供应电压将会低于在核心部分5外围部分处的供应电压。将会出现由于供应电压下降而导致半导体芯片1的电路部分不能执行预定操作的问题。因此，在常规半导体器件10的情况下，供应电压下降成为半导体芯片1操作故障的原因。
发明内容
本发明的一目的是提供一种能消除上述问题的改进的半导体器件。
本发明的另一目的是提供一种简单和低成本的半导体器件，其中电源线的结构被改进并且可以有效稳定半导体芯片的操作。
为了实现上述目的，本发明提供一种半导体器件，其中在半导体芯片的电路部分中心处的电源线上和在半导体芯片的电路部分外围部分处的电源线上分别形成开口。并且电路部分中心的开口上的电源线和电路部分外围部分的开口上的电源线通过由银膏等形成的导体层而被相互连接。能够在工作期间使得电路部分中心处提供的电源电流增大。因此，本发明能够防止在电路部分中心处的供应电压在工作期间下降，并且能够有效稳定半导体芯片的工作。
附图说明
当接合附图阅读下述具体描述时，本发明的其他目的、特征和优点将变得显而易见。
图1是示出常规半导体器件组成的图；
图2A是用于说明在本发明优选实施例中的半导体芯片的电路部分的电源线上形成的导体层的图；
图2B是用于说明在本发明优选实施例中的半导体芯片的电路部分的电源线上形成的导体层的图；
图3是示出在图2B的半导体芯片中电源线与导体层之间连接的横截面视图；
图4是示出在本发明一个实施例中的半导体器件组成的图；
图5是示出在本发明另一实施例中的半导体器件组成的图；
图6是示出在图5的半导体器件中衬底、半导体芯片与导体层之间连接的横截面视图；
图7是示出本发明另一实施例中的半导体器件组成的图；
图8是示出在图7的半导体器件中TAB带、半导体芯片与导体层之间连接的横截面视图；
图9是示出图2B的半导体芯片的横截面结构的横截面视图；以及
图10是示出在图4的半导体器件中布线板、半导体芯片与导体层之间连接的侧视图。
具体实施方式
现在参照附图给出本发明优选实施例的描述。
图4示出本发明优选实施例中的半导体器件的组成。图10示出在图4的半导体器件中布线板、半导体芯片与导体层之间的连接。
图4的半导体器件20包括在布线板21上承载的半导体芯片11，比如LSI。布线板21例如被用作插入件。半导体芯片11包含在中心处形成的电路部分(核心部分)，在电路部分的外围部分处设置的多个电极焊盘12，以及电源线14。
如图10所示，半导体芯片11经由压模(die)材料21a安装于布线板21上，其中其电路部分形成在向上放置的前表面上和在向下放置的后表面上。在多个电极焊盘12中为电源设置的电极焊盘12与半导体芯片11的电路部分和电源线14连接。
在多个电极焊盘12中为接地设置的电极焊盘12与半导体芯片11的电路部分和电源线14连接。来自电源(未示出)的电源电流在工作时从半导体芯片11的外围部分经由电源线14被供应至半导体芯片中心处的电路部分。
在半导体器件20的布线板21上，在围绕半导体芯片11的区域中设置多条接合导线17。在多条接合导线17中，用于电源的接合导线17与电源(未示出)连接，并且在多条接合导线17中用于接地的接合导线17被接地。
在半导体芯片11外围的每个电极焊盘12通过引线18分别电连接至多条导线17的其中之一。
为了解决在上述常规半导体器件工作时，在半导体芯片的电路部分中心处提供的供应电压下降的问题，图4的半导体器件20如下述构造。在半导体芯片11的电路部分的中心和外围部分处，在每条电源线14上分别形成开口13。在这些开口13上形成导体层16以覆盖半导体芯片11的电路部分的整个表面，并且在电路部分中心的开口13上的电源线14和在电路部分外围部分的开口13上的电源线14通过导体层16相互连接。
该导体层16能够通过向半导体芯片11涂覆导电材料比如银膏来形成。在半导体器件20的布线板21上的多条接合导线17中用于导体层的接合导线17通过引线18电连接至导体层16。这些用于导体层的接合导线17(在图4的实例中，有8条)包括连接到电源(未示出)的接合导线，和连接到地极的接合导线。
因此，在工作时，来自电源(未示出)的电源电流经由用于导体层的接合导线17和引线18被直接供应至导体层16。通过在本发明的半导体器件中形成该导体层16，能够增加在工作时供应至半导体芯片11中心处的电路部分的电源电流量。
因此，在工作时，能够防止半导体芯片11的电路部分中心处的供应电压的下降，并且有效稳定半导体芯片11的工作。
图2A和图2B是用于说明图4的半导体芯片11的电路部分的电源线14上形成的导体层16的图。
在形成导体层16之前，在半导体芯片11的电源线14上形成多个开口13，如图2A所示。对于半导体芯片11的电路部分外围部分附近的电源线14上的位置、和易于出现电压下降的半导体芯片11的电路部分中心附近的电源线14上的位置，均等分布形成多个开口13的位置。
在多个开口13的每一个中，开口都是这样形成的：使得其它布线层、绝缘层等不闭合半导体芯片11的电源线14的一部分。在半导体芯片11的制造过程中可附加地形成这些开口13。可选地，可在半导体芯片11的制造之后形成这些开口13。
如图2B所示，在形成多个开口13之后，在其上形成导体层16。通过涂覆或印刷导电物质比如银膏，形成导体层16以覆盖半导体芯片11上的所有多个开口13，并且导体层16和电源线14在每个开口13处连接在一起。
图9示出图2B的半导体芯片11的横截面结构。
如图9所示，半导体芯片11包括：衬底19比如硅，在衬底19上形成的布线层15，在布线层15上形成的导体层16，以及电极焊盘12。布线层15包括绝缘层15a，电源线14和其它布线层。
通过去除布线层15的绝缘层15a来形成开口13，从而露出电源线14。通过涂覆或印刷银膏等形成导体层16，从而通过导体层16覆盖半导体芯片11上的所有开口13。
在该实施例中，使用的银膏的银(Ag)含量为60％或以上，银膏被加热和硬化，并且硬化材料的银含量为99％或以上。理所当然地，可使用除了银(Ag)之外的金属比如金(Au)或铜(Cu)及其他导电物质来作为用于形成导体层16的材料。
图3示出在图2B的半导体芯片11的开口13中，电源线14与导体层16之间的连接。
利用铝(Al)或铜(Cu)形成图2B的半导体芯片11的布线，并且电源线14的布线宽度相对较小(约10微米)。为此，在涂覆银膏之前，进行非电解电镀，从而在开口13位置处的电源线14上形成镍(Ni)和金(Au)的镀层，以避免在硬化银膏时热应力引起布线的断开。
如图3所示，在位于半导体芯片11的电路部分中的开口13中，在电源线14上形成镍镀层17a和Au镀层17b，并且进一步通过涂覆和硬化银膏在镀层17a和17b上形成导体层16，从而导体层16几乎覆盖半导体芯片11的电路部分(含有其中心和外围部分)的整个表面。
在具有上述结构的半导体器件20中，位于半导体芯片的电路部分中心处的开口13和位于半导体芯片11的电路部分外围部分处的开口13通过导体层16相互连接，并且导体层16在每个这些开口13处与电源线14电连接。
如上所述，在图4的半导体器件20中，通过在半导体芯片11的电路部分中形成开口13和导体层16，能够在工作时增加供应至半导体芯片11中心处的电路部分的电源电流。因此，能够防止在工作时半导体芯片11的电路部分中心处的供应电压的下降，并且能够有效稳定半导体芯片11的工作。
此外，通过利用公知的布线方法，能够在半导体芯片11上容易地形成该实施例中的开口13和导体层16，并且本发明能够提供简单和低成本的半导体器件。
接下来，将参照图5和图6说明本发明另一实施例中的半导体器件。
关于安装IC或LSI芯片的芯片安装技术，公知的有引线接合法、倒装接合法、TAB(卷带式自动接合)法等。并且依据所涉及的器件或产品领域，正适当采用这些方法。
图4的上述半导体器件20是本发明的一个实施例，其中通过使用引线接合法来进行半导体芯片的安装。
与此相对照，图5和图6所示的半导体器件30是本发明的一个实施例，其中通过使用倒装接合法来进行半导体芯片的安装。
图5示出在该实施例中的半导体芯片11a的电路形成表面(后表面)的组成。图6示出该实施例的半导体器件30中衬底22、半导体芯片11a与导体层16之间的连接。
该实施例的半导体器件30包括在衬底22上承载的半导体芯片11a比如LSI。与图2B中的设置有多个电极焊盘12的半导体芯片11不同，在该实施例中的半导体芯片11a的外围部分处设置多个突起12a，取代多个电极焊盘12，如图5所示。
如图5所示，半导体芯片11a包括：在中心处形成的电路部分(核心部分)，设置在电路部分的外围部分的多个突起12a，电源线14，多个开口13，以及导体层16。在多个突起12a中为电源设置的突起12a与半导体芯片11a的电路部分和电源线14连接。在多个突起12a中为接地设置的突起12a与半导体芯片11a的电路部分和电源线14连接。
来自电源(未示出)的电源电流在工作时从半导体芯片11a的外围部分经由电源线14被供应至半导体芯片11a中心处的电路部分。
在位于半导体芯片11a的电路部分中心处的电源线14上和位于半导体芯片11a的电路部分外围部分处的电源线14上，分别形成开口13。在这些开口13上形成导体层16以覆盖半导体芯片11a的电路部分的整个表面，并且在电路部分中心的开口13上的电源线14和在电路部分外围部分的开口13上的电源线14通过导体层16相互连接。
与上述参照图2B所述的形成方法类似，可通过向半导体芯片11a涂覆并硬化导电材料比如银膏，来形成导体层16。在下述中，将省略重复的说明。
如图6所示，在半导体器件30的衬底22上，在面向半导体芯片11a的电路部分的区域中设置端子24，并且在衬底22上在面向半导体芯片11a的多个突起12a的区域中设置多个端子23。
在多个端子23中，用于电源的端子23与电源(未示出)连接，并且在多个端子23中用于接地的端子23被接地。
在图6的半导体器件30中，在半导体芯片11a外围的多个突起12a的每一个分别电连接至位于衬底22上的多个端子23其中之一。在半导体芯片11a的中心处的导体层16也电连接至位于衬底22上的端子24。
与前面图4的实施例类似，在该实施例的半导体器件30中，通过在半导体芯片11a的电路部分中形成开口13和导体层16，能够增大在工作时供应至半导体芯片11a中心处的电路部分的电源电流。因此，能够防止在工作时在半导体芯片11a的电路部分中心处的供应电压下降，并且能够有效稳定半导体芯片11a的工作。
由于通过利用公知的布线方法，能够在半导体芯片11a上容易地形成该实施例中的开口13和导体层16，则本发明能够提供简单和低成本的半导体器件。
接下来，将参照图7和图8说明本发明另一实施例中的半导体器件。
如上所述，图4的半导体器件20是本发明的一个实施例，其中通过使用引线接合法来进行半导体芯片的安装。与此相对照，图7和图8所示的半导体器件40是本发明的一个实施例，其中通过使用TAB法来进行半导体芯片的安装。
图7示出在该实施例的半导体芯片11b的电路形成表面(前表面)和TAB带28的组成。图8示出该实施例的半导体器件40中TAB带28、半导体芯片11b与导体层16之间的连接。
该实施例的半导体器件40包括在TAB带28上承载的半导体芯片11b。与图2B中的实例不同，在如图7所示的半导体芯片11b的外围部分处设置多个突起12b，取代多个电极焊盘12。
如图7所示，半导体芯片11b包括：在中心处形成的电路部分(核心部分)，设置在电路部分的外围部分的多个突起12b，电源线14，多个开口13，以及导体层16。
在多个突起12b中为电源设置的突起12b与半导体芯片11b的电路部分和电源线14连接。在多个突起12b中为接地设置的突起12b与半导体芯片11b的电路部分和电源线14连接。
来自电源(未示出)的电源电流在工作时从半导体芯片11b的外围部分经由电源线14被供应至中心电路部分。
在位于半导体芯片11b的电路部分中心处的电源线14上和位于半导体芯片11b的电路部分外围部分处的电源线上，分别形成开口13。在这些开口13上形成导体层16以覆盖半导体芯片11b的电路部分的整个表面，并且在电路部分中心的开口13上的电源线14和在电路部分外围部分的开口13上的电源线14通过导体层16相互连接。
与上述参照图2所述的形成方法类似，可通过向半导体芯片11b涂覆并硬化导电材料比如银膏，来形成导体层16。在下述中，将省略重复的说明。
在TAB带28中，分别在面向半导体芯片11b的多个突起12b的位置处设置多条导线27。在多条导线27中用于电源的导线27与电源(未示出)连接，并且在多条导线27中用于接地的导线27被接地。而且，设置成X状形式的用于电源的一对导线29设置于在面向半导体芯片11b的电路部分的位置处的TAB带28的开口中。
如图8所示，在该实施例的半导体器件40中，在半导体芯片11b外围的多个突起12b的每一个分别电连接至位于TAB带28上的多条导线27其中之一。并且，在半导体芯片11b中心处的导体层16也电连接至在TAB带28上形成的用于电源的导线29。
与前面的图4的实施例类似，在该实施例的半导体器件40中，通过在半导体芯片11b的电路部分中形成开口13和导体层16，能够增大在工作时供应至半导体芯片11b的电路部分中心处的电源电流。因此，能够防止在工作期间在半导体芯片11b的电路部分中心处的供应电压的下降，并且能够有效稳定半导体芯片11b的工作。由于通过利用公知的布线方法，也能够在半导体芯片11b上容易地形成该实施例中的开口13和导体层16，则本发明能够提供简单和低成本的半导体器件。
本发明不限于上述的实施例，并且在不脱离本发明范围的条件下可进行各种变化和改型。

Claims (9)

1.一种半导体器件，包括：
半导体芯片，其中在该半导体芯片中心处设置的电路部分与电源线和电源电极连接，以从外部电源向该电路部分供电；
衬底，设置为用于在其上承载该半导体芯片，并且设置为使得在围绕该半导体芯片的区域中设置的第一端子电连接至所述电源电极；
第一开口，形成在该电路部分中心处的电源线上；
第二开口，形成在该电路部分外围部分处的电源线上；以及
导体层，电连接至在该衬底上围绕该半导体芯片的区域中设置的第二端子，并且设置为使得该第一开口中的电源线与该第二开口中的电源线通过该导体层相互连接。
2.如权利要求1所述的半导体器件，其中该导体层使用银、金和铜中的任意导电物质来形成。
3.如权利要求1所述的半导体器件，其中该第一开口中的电源线和该第二开口中的电源线经由金属镀层与该导体层连接。
4.一种半导体器件，包括：
半导体芯片，其中在该半导体芯片中心处设置的电路部分与电源线和电源突起连接，以从外部电源向该电路部分供电；
衬底，设置为用于在其上承载该半导体芯片，并且设置为使得在面向该半导体芯片上的电源突起的区域中设置的第一端子电连接至所述电源突起；
第一开口，形成在该电路部分中心处的电源线上；
第二开口，形成在该电路部分外围部分处的电源线上；以及
导体层，电连接至在该衬底上面向该电路部分的区域中设置的第二端子，并且设置为使得该第一开口中的电源线与该第二开口中的电源线通过该导体层相互连接。
5.如权利要求4所述的半导体器件，其中该导体层使用银、金和铜中的任意导电物质来形成。
6.如权利要求4所述的半导体器件，其中该第一开口中的电源线和该第二开口中的电源线经由金属镀层与该导体层连接。
7.一种半导体器件，包括：
半导体芯片，其中在该半导体芯片的中心处设置的电路部分与电源突起和电源线连接，以从外部电源向该电路部分供电；
TAB带，设置为用于在其上承载该半导体芯片，并且设置为使得在围绕该半导体芯片的区域中设置的第一导线电连接至所述电源突起；
第一开口，形成在该电路部分中心处的电源线上；
第二开口，形成在该电路部分外围部分处的电源线上；以及
导体层，电连接至在该TAB带上面向该半导体芯片的区域中设置的第二导线，并且设置为使得该第一开口中的电源线与该第二开口中的电源线通过该导体层相互连接。
8.如权利要求7所述的半导体器件，其中该导体层使用银、金和铜中的任意导电物质来形成。
9.如权利要求7所述的半导体器件，其中该第一开口中的电源线和该第二开口中的电源线经由金属镀层与该导体层连接。
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US20050280034A1 (en) 2005-12-22
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