CN101064294A - 电路装置及电路装置的制造方法 - Google Patents

电路装置及电路装置的制造方法 Download PDF

Info

Publication number
CN101064294A
CN101064294A CNA2007101018784A CN200710101878A CN101064294A CN 101064294 A CN101064294 A CN 101064294A CN A2007101018784 A CNA2007101018784 A CN A2007101018784A CN 200710101878 A CN200710101878 A CN 200710101878A CN 101064294 A CN101064294 A CN 101064294A
Authority
CN
China
Prior art keywords
wiring layer
circuit arrangement
layer
resin layer
gold plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007101018784A
Other languages
English (en)
Other versions
CN101064294B (zh
Inventor
村井诚
小原泰浩
臼井良辅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN101064294A publication Critical patent/CN101064294A/zh
Application granted granted Critical
Publication of CN101064294B publication Critical patent/CN101064294B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01083—Bismuth [Bi]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01088—Radium [Ra]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals

Abstract

一种电路装置和其制造方法，抑制焊垫电极部的密封树脂层的剥离，提高电路装置的可靠性。该电路装置具有配线层(3)、含金镀层(4)、绝缘树脂层(5)、电路元件(6)、导电部件(7)、及密封树脂层(8)。配线层(3)在含有铜的配线层(3)的焊垫电极部分，在其表面形成含金镀层(4)。将该部分之外的表面进行粗面加工。绝缘树脂层(5)被形成为覆盖配线层(3)并且焊垫电极形成区域具有开口部(5a)。电路元件(6)安装于规定区域的绝缘树脂层(5)上。密封树脂层(8)形成于绝缘树脂层(5)上，在整个面上形成覆盖电路元件(6)及焊垫电极的开口部(5a)。在此，密封树脂层(8)被设置为在焊垫电极部分与含金镀层(4)及配线层(3)相接。

Description

电路装置及电路装置的制造方法
技术领域
本发明涉及电路装置，尤其是涉及具有焊垫电极的电路装置。
背景技术
随着手机、PDA、DVC、DSC这种便携电子设备的高性能化加速，为了使这样的产品被市场接受，而必须使其小型、轻量化，为实现该小型、轻量化，而要求高集成的系统LSI。另一方面，对于这些电子设备，要求使用更容易且便利，对于设备中使用的LSI要求高功能化、高性能化。因此，随着LSI芯片的高集成化，其I/O数增大，另一方面还强烈要求封装本身小型化，为了同时满足这些条件，而强烈要求适用于半导体部件的高密度衬底安装的半导体封装的开发。对应这样的要求，开发各种被称为CSP(Chip SizePackage)的封装技术。
作为这样的封装之一例。已知有BGA(Ball Grid Array)。在BGA中，在封装用衬底上安装半导体芯片，在将其树脂模制后，在相反侧的面上区块状形成焊料球作为外部端子。
图18是专利文献1中记载的BAG型半导体装置的概略剖面图。该半导体装置(电路装置)中，在电路衬底110的一个面上搭载半导体元件(电路元件)106，在另一个面上结合焊料球112作为外部连接端子。在电路衬底110的一个面上设有与半导体元件106电连接的配线图形103(焊垫电极部103a)，在电路衬底110的另一面上设有结合外部连接端子的焊盘部103b。配线图形103和焊盘部103b的电连接经由设于贯通绝缘衬底101的贯通孔111内壁面的导体部进行。阻焊剂105保护电路衬底110的表面。电路衬底110的另一面在搭载了半导体元件106之后，由密封树脂层108密封。
图19是将图18所示的半导体装置的焊垫电极部(图18中X所示的剖面部分)放大后的剖面图。与半导体元件106引线连接的焊垫电极部103a构成为含有铜的配线部和覆盖其表面的含金镀层104。阻焊剂105覆盖焊垫电极部103a上的铜配线部，进而覆盖含金镀层104的局部。阻焊剂105的开口部在进行了半导体元件106的搭载及引线连接等之后，由密封树脂层108与半导体元件106一起密封。
专利文献1：(日本)特开2005-197648号公报
如上述文献所记载，在由密封树脂层108密封半导体元件106时，焊垫电极部103a中的密封树脂层108的密接性(有无剥离)是重要的。当该部分的密接性产生不良时，半导体装置(电路装置)的可靠性会因受到热应力或水分的影响而显著降低。
发明内容
本发明是鉴于上述情况而构成的，其目的在于，抑制焊垫电极部中的密封树脂层的剥离，提高电路装置的可靠性。
为实现上述目的，本发明一方面提供一种电路装置，其特征在于，具有：含有铜的配线层和具有在提供其表面进行电连接的部分的局部形成的含金镀层的电极层、和覆盖所述电极整个面的密封树脂层，密封树脂层被设置为与含金镀层及配线层相接。在此，电极是指，例如设于封装衬底或模制衬底等电路衬底上的焊垫电极、或设于以LSI芯片为代表的电路元件上的封装电极。通过该电极，将电路衬底和以LSI芯片为代表的电路元件引线连接，或将电路衬底和外部的电路装置引线连接。
根据该方面，由于电极中的密封树脂层不仅与含金镀层相接，而且也与密接性比含金镀层高的配线层相接，因此，与如现有技术那样的只与含金镀层相接的情况相比，电极中的密封树脂层的密接强度提高。其结果是不会受到热应力或水分的影响，从而电路装置的可靠性提高。
在上述结构中，还具有将电路元件和形成焊垫电极的含金镀层的部分电连接的导电部件，导电部件优选经由含金镀层与配线层电连接。该情况下，由于在焊垫电极表面设有含金镀层，故可抑制采用含有铜的配线层时产生的焊垫电极表面的恶化。因此，可提高焊垫电极中密封树脂层的密接强度，同时可进一步抑制电路装置中的电路元件和配线层的连接不良。其结果可进一步提高电路装置的可靠性。
另外，本发明的另一方面提供一种电路装置，其特征在于，具有：衬底；形成于衬底上的含有铜的配线层；形成于衬底及配线层上，在电极形成区域具有开口部的绝缘树脂层；在提供设于开口部内的配线层的表面进行电连接的部分形成的含金镀层；设于衬底上的电路元件；经由含金镀层将电路元件和配线层电连接的导电部件；形成于绝缘树脂层上，将电路元件及电极形成区域密封的密封树脂层，密封树脂层被设置为与含金镀层及配线层相接。
根据该方面，由于密封电极的形成区域的树脂层不仅与含金镀层相接，而且也与密接性比含金镀层高的配线层相接，因此，与如现有技术那样的只与含金镀层相接的情况相比，密封电极的形成区域的密封树脂层的密接性提高。其结果是不会受到热应力及水分的影响，从而电路装置的可靠性提高。
在上述结构中，电路元件也可以是半导体元件。半导体元件是指IC、LSI等。该情况下，也可以使用导电部件将半导体元件引线连接。另外，还可以使用导电部件将半导体元件倒装片连接。再有，电路元件也可以是无源元件。无源元件是指例如电阻、电容器等。
在上述结构中，与密封树脂层相接的配线层的表面优选实施粗面加工。由此，可进一步提高配线层和密封树脂层的界面的密接性，且可有效地抑制电极的密封树脂层的剥离。
在上述结构中，密封树脂层与配线层相接的区域也可以设于与含金镀层相接的区域周围。该情况下，由于含金镀层周围被实施了粗面加工的配线层包围，故可更有效地抑制密封树脂层从焊垫电极的剥离。
本发明的再一方面是提供电路装置的制造方法。该电路装置的制造方法的特征在于，具有：在衬底的主面上形成配线层的工序；在配线衬底在整个主面上形成导电层的工序；在配线衬底的整个主面上形成在电极形成区域具有大于电极的开口的第一绝缘层的工序；将在开口露出的导电层除去，使配线层露出的工序；将导电层作为镀敷用配线使用，在露出的配线层上形成含金镀层的工序；除去第一绝缘层及导电层的工序；在配线衬底的整个主面上形成具有使含金镀层和其附近的配线层露出的开口的第二绝缘层的工序；将电路元件与含金镀层电连接的工序。
根据该方面，由于将形成于配线层上的导电层作为总线使用，且在形成含金镀层之后将导电层除去，因此避免了镀敷用总线成为噪声源。
另外，由于在形成含金镀层之后将镀敷用导电层除去，故配线等的布线不易受到制约，因此，可实现电路装置的高密度化。
在上述方面的电路装置的制造方法的除去第一绝缘层及导电层的工序中，也可以将露出的所述配线层的表面进行粗面加工。
根据本发明，可抑制焊垫电极部的密封树脂层的剥离，且可提高电路装置的可靠性。
附图说明
图1是表示本发明第一实施例的电路装置的概略剖面结构的剖面图；
图2是将图1所示的电路装置的焊垫电极部放大后的剖面图；
图3是将图1所示的电路装置的焊垫电极部放大后的平面图；
图4(A)～(E)是用于说明第一实施例的电路装置的第一制造工艺的剖面图；
图5(A)～(D)是用于说明第一实施例的电路装置的第一制造工艺的剖面图；
图6(A)～(D)是用于说明第一实施例的电路装置的第二制造工艺的主要部分平面图；
图7(A)～(D)是用于说明第一实施例的电路装置的第二制造工艺的主要部分剖面图，图7(A)～(D)分别是图6(A)～(D)的A-A’线上的剖面图；
图8(A)～(B)是用于说明第一实施例的电路装置的第二制造工艺的主要部分平面图；
图9(A)～(B)是用于说明第一实施例的电路装置的第二制造工艺的主要部分剖面图，图9(A)～(B)分别是图8(A)～(B)的A-A’线上的剖面图；
图10是表示本发明第二实施例的电路装置的概略剖面结构的剖面图；
图11是将图6所示的电路装置的焊垫电极部放大后的剖面图；
图12是表示本发明第三实施例的电路装置的概略剖面结构的剖面图；
图13是将图12所示的电路装置的焊垫电极部放大后的剖面图；
图14是表示第四实施例的电路装置的结构的平面图；
图15是图14的A-A’线上的剖面图；
图16是表示第四实施例的电路装置的配线层及含金镀层的图形的图；
图17是表示第四实施例的电路装置的绝缘层的开口图形的图；
图18是表示现有的BGA型半导体装置的概略剖面结构的剖面图；
图19是将图18所示的半导体装置的焊垫电极部放大后的剖面图。
符号说明
1金属衬底；2绝缘层；3配线层；4含金镀层；5绝缘树脂层；6电路元件；7导电部件；8密封树脂层；
具体实施方式
下面，基于附图对具体化了本发明的实施例进行说明。需要说明的是，全部附图中，同样的构成要素使用相同的符号，适宜省略说明。
(第一实施例)
图1是本发明第一实施例的具有焊垫电极的电路装置的概略剖面图。另外，图2是将图1所示的电路装置的焊垫电极部(图1中X所示的剖面部分)放大后的剖面图。基于图1及图2对第一实施例的电路装置进行说明。
该第一实施例中的电路装置具有金属衬底1、绝缘层2、配线层3(焊垫电极3a)、含金镀层4、绝缘树脂层5、电路元件6、导电部件7、及密封树脂层8。
金属衬底1例如使用具有约1.5mm厚度的铜(Cu)衬底。需要说明的是，具有该金属衬底1和后述的绝缘层2的部分是本发明的“衬底”之一例。
绝缘层2采用以环氧树脂为主成分的膜，其厚度例如为约80μm。从提高电路装置的散热性的观点考虑，优选绝缘层2具有高导热性。因此，绝缘层2优选含有银、铋、铜、铝、镁、锡、锌、及它们的合金等、或二氧化硅、氧化铝、氮化硅、氮化铝等作为高导热性填料。
在此，第一实施例中，在后述的位于电路元件6下方的绝缘层2的区域，隔开规定的间隔形成有具有约70μm的直径(通孔直径)、且在厚度方向贯通绝缘层2的四个贯通孔2a。在该贯通孔2a内埋入有后述的构成配线层3的部件。配线层3经由该贯通孔2a与金属衬底1的上面接触。已埋入该贯通孔2a内的配线层3具有将来自电路元件6的热传递到金属衬底1而进行散热的功能。
配线层3例如采用铜铝等金属，其厚度例如约为20μm。配线层3在局部含有焊垫电极3a并且被加工成规定的配线图形。在配线层3的焊垫电极3a部分，在其表面形成有后述的含金镀层4。将该部分之外的表面实施粗糙加工。进行该粗面加工而得到的配线层3的算术平均粗糙度Ra优选约0.2μm～约10μm。在此，采用通过粗糙化而使Ra达到0.38μm的铜配线。另外，粗糙化之前的铜配线的Ra约为0.25μm。
含金镀层4采用电解镀Au/Ni膜，其膜厚例如约为0.5μm。含金镀层4在配线层3的焊垫电极3a部分覆盖其表面局部而形成。需要说明的是，该焊垫电极3a为本发明的“电极”之一例。在此，含金镀层4的Ra约为0.11μm。含金镀层4的表面与含有铜的配线层3的表面相比，其表面粗糙度(算术平均粗糙度Ra)小，因此，与后述的密封树脂层8之间的锚定效果小，与含有铜的配线层3相比，含金镀层4的密接强度小。
绝缘树脂层5采用由环氧树脂等构成的阻焊膜，其膜厚例如约为30μm。绝缘树脂层5具有形成于绝缘层2及配线层3上，且与含有配线层3的焊垫电极3a的形成区域对应的开口部5a。该绝缘树脂层5作为配线层3的保护膜起作用。另外，绝缘树脂层5形成于被表面粗糙化的配线层3上，因此，其界面具有良好的密接性。
电路元件6例如为IC芯片、LSI芯片等半导体元件、电容器、电阻等无源元件。在此采用其上面具有焊垫电极(未图示)的LSI芯片。电路元件6安装于规定区域的绝缘树脂层5上。
导电部件7采用金属线等，经由含金镀层4将配线层3的焊垫电极3a和电路元件6进行电气的引线连接。
密封树脂层8被整个面地形成为覆盖绝缘树脂层5、电路元件6及绝缘树脂层5的开口部5a。另外，在开口部5a部分，密封树脂层8被设置为与含金镀层4、绝缘层2及配线层3相接。该密封树脂层8保护电路元件6不受外部的影响。密封树脂层8的材料例如为环氧树脂等热固化性的绝缘性树脂。另外，也可以在密封树脂层8中添加用于提高导热性的填料。
图3是将图1所示的电路装置的焊垫电极部(图1中X所示的剖面部分)放大后的平面图。密封树脂层8和配线层3相接的面(区域8a)位于与导电部件7连接的区域8b与由绝缘树脂层5覆盖的配线图形部之间。
(制造方法)
(第一实施例的电路装置的第一制造工艺)
图4及图5是用于说明图1所示的第一实施例的电路装置的第一制造工艺的剖面图。其次，参照图1、图4及图5说明第一实施例的电路装置的第一制造工艺。
首先，如图4(A)所示，在金属衬底1上压接包括具有约80μm厚度的绝缘层2和具有约3μm厚度的铜箔3z的层叠膜。
如图4(B)所示，使用光刻技术及蚀刻技术除去位于贯通孔2a(参照图1)的形成区域的铜箔3z。由此使绝缘层2的贯通孔2a的形成区域露出。
如图4(C)所示，通过从铜箔3z的上方照射碳酸气体激光或UV激光，将从绝缘层2露出的表面到达金属衬底1表面的区域除去。由此，在绝缘层2上形成其表面直径约70μm、贯通绝缘层2的贯通孔2a。
如图4(D)所示，使用无电解镀敷法在铜箔3z的表面及贯通孔2a的内面上镀敷约0.5μm厚度的铜。接着，使用电解镀敷法在铜箔3z的表面及贯通孔2a的内部镀敷铜。另外，在本实施例中，通过向镀敷液中添加抑制剂及促进剂，使抑制剂吸附在铜箔3z的表面上，同时使促进剂吸附在贯通孔2a的内面上。由此，由于可增大贯通孔2a内面上的镀铜的厚度，故可向贯通孔2a内埋入铜。其结果是，如图4(D)所示，在绝缘层2上形成具有约20μm厚度的配线层3，并且在贯通孔2a内埋入配线层3。
如图4(E)所示，使用光刻技术及蚀刻技术将配线层3构图。由此形成具有规定配线图形(焊垫电极3a等)的配线层3。
其次，如图5(A)所示，使用选择镀敷法在规定区域(焊垫电极3a的区域)的配线层3的表面形成含金镀层(电解镀Au/Ni膜)4。含金镀层4的形成区域是之前的图3所示的区域。
如图5(B)所示，通过湿式处理等将含有铜的配线层3的表面粗糙化。例如当进行使用了酸类药液的表面处理时，其表面成为具有微小凹凸的粗糙面。由此，配线层3的表面具有微小的凹凸而被粗面化。进行该粗面化得到的配线层3的算术平均粗糙度Ra如上所述，约为0.38μm。配线层3表面的Ra可用触针式表面形状测定器测定。需要说明的是，该酸类药液进行的湿式处理不能将含金镀层4的表面粗面化。含金镀层4的Ra约为0.11μm。
如图5(C)所示，形成绝缘树脂层5，以使其覆盖绝缘层2及配线层3，且具有与配线层3的焊垫电极3a的形成区域对应的开口部5a。绝缘树脂层5的膜厚例如约为30μm。另外，绝缘树脂层5由于在将表面粗糙化了的配线层3上形成，因此其具有良好的密接性。
如图5(D)所示，在绝缘树脂层5上安装电路元件6。另外，电路元件6是在其上面具有焊垫电极(未图示)的LSI芯片。接着，使用导电部件7，经由含金镀层4将配线层3的焊垫电极和电路元件6引线连接。由此将电路元件6和配线层3电连接。
最后，如图1所示，在绝缘树脂层5上，形成密封树脂层8以覆盖电路元件6及焊垫电极3a的开口部5a。此时，在焊垫电极3a部分，密封树脂层8被设置为将含金镀层4及配线层3两者相接。如上所示，含有铜的配线层3的表面与含金镀层4的表面相比，表面粗糙度(算术平均粗糙度Ra)大。因此，在其与密封树脂层8之间，锚定效果进一步作用，从而密接性比含金镀层4的高。
通过进行这些工序，可得到第一实施例的电路装置。
根据以上说明的第一实施例的电路装置，可得到如下效果。
(1)焊垫电极3a中的密封树脂层8不仅被设置为与含金镀层4相接而且也与密接性比含金镀层4高的配线层3相接，因此，与如现有技术那样的只与含金镀层相接的情况相比，焊垫电极3a中的密封树脂层8的密接强度提高。其结果是，不会受到热应力或水分的影响，从而电路装置的可靠性提高。
(2)由于在焊垫电极3a表面设置了含金镀层4，从而可抑制采用含有铜的配线层3时产生的焊垫电极表面的恶化。因此，可使焊垫电极3a中密封树脂层8的密接强度提高，并且可抑制电路装置中的电路元件6和配线层3的连接不良。其结果可进一步提高电路装置的可靠性。
(3)由于对与密封树脂层8相接的配线层3的表面实施了粗面加工，故可实现配线层3和密封树脂层8的界面的密接性的进一步提高，且能够有效地抑制焊垫电极3a中的密封树脂层8的剥离。
(第一实施例的电路装置的第二制造工艺)
对第一实施例的电路装置的第二制造工艺进行说明。有关第二制造工艺的基本工序，对与上述第一制造工艺相同的工序适宜省略说明，以与第一制造工艺不同的点为中心进行说明。图6及图8是用于说明图1所示的第一实施例的电路装置的第二制造工艺的焊垫形成区域的平面图。图7及图9分别是图6及图8的A-A’线上的剖面图。另外，图7～图9中，将第一实施例的电路装置中的焊垫电极部的主要部分进行了图示。
第二制造工艺到图4(A)～图4(E)为止，与第一制造工艺是共通的。
在进行了图4(E)所示的工序之后，如图6(A)及图7(A)所示，利用无电解镀敷法在绝缘层2及配线层3上形成由薄(フラツシユ)铜构成的导电层100。导电层100的厚度例如为1μm。在配线层3的前端部分，如匹配棒的头部分，形成有圆状扩散的焊垫形成区域。需要说明的是，焊垫形成区域不限于圆状，例如也可以为矩形。
其次，如图6(B)及图7(B)所示，在导电层100上层叠对金具有耐性的抗蚀剂120之后，通过进行曝光及显影，在焊垫形成区域设置开口R。由此，导电层100在开口R露出。
其次，如图6(C)及图7(C)所示，通过使用硫酸和过氧化氢的混合液进行蚀刻，将开口R内的导电层100除去。由此，在开口R内，配线层3及其周围的绝缘层2露出。
其次，如图6(D)及图7(D)所示，将设于抗蚀层120下面的导电层100作为总线使用，通过电解镀敷法在露出于开口R内的配线层3上形成含金镀层(电解镀Au/Ni层)。
其次，如图8(A)及图9(A)所示，在将抗蚀剂120剥离后，使用硫酸和过氧化氢的混合液进行蚀刻，由此将导电层100除去。另外，如第一制造工艺所说明，利用蚀刻将配线层3的表面粗糙化。
其次，如图8(B)及图9(B)所示，在层叠绝缘树脂层(光致抗蚀剂)5后，进行曝光及显影，由此在焊垫形成区域设置开口R’。开口R’与开口R相比，开口区域宽，以使未由含金镀层4覆盖的配线层3的局部露出。由此，在开口R’部分，含金镀层4及与含金镀层4近接且实施了粗面加工的配线层3露出。由于绝缘树脂层5的下面与实施粗面加工的配线层3相接，故通过锚定效果使配线层3和绝缘树脂层5的密接性提高。
通过进行以上的工序，得到相当于第一制造工艺的图5(C)的结构。之后，通过应用与第一制造工艺相同的工序，可制造第一实施例的电路装置。
根据该第二制造工艺，可得到如下效果。
(4)在通过选择镀敷法在焊垫形成区域形成含金镀层4时，需要预先形成与焊垫形成区域连接的镀敷用的总线。通过切割进行的单片化，该镀敷用总线被切断，但从切割线到焊垫形成区域的镀敷用总线有部分残留。由于残留的总线具有天线的作用，从而可能产生噪声。但是，根据第二制造工艺，由于将由形成于配线层3上具有薄铜构成的导电层100作为总线使用，且在形成含金镀层4之后将导电层100除去，因此避免了镀敷用总线成为噪声源。
(5)在通过选择镀敷法在焊垫形成区域形成含金镀层4时，需要预先形成与焊垫形成区域连接的镀敷用的总线。因此，配线等的布线等可能会受到制约，或可能会防碍高密度化。但是，根据第二制造工艺，由于在形成含金镀层4之后将镀敷用导电层100除去，故配线等的布线不易受到制约，且也不易防碍高密度化。
(第二实施例)
图10是本发明第二实施例的电路装置的焊垫电极部的剖面图。图11是图10所示的电路装置的焊垫电极部的平面图。第二实施例的电路装置与之前的第一实施例的不同点在于，密封树脂层8与配线层3相接的区域8a设于与含金镀层4相接的连接区域8b的周围。除此之外，与之前的第一实施例相同。
根据该第二实施例的电路装置，可得到如下效果。
(6)由于含金镀层4的周围被实施了粗面加工的配线层3所包围，故可更有效地抑制密封树脂层8从焊垫电极3a的剥离。其结果提供可靠性提高的电路装置。
(第三实施例)
图12是本发明第三实施例的电路装置的焊垫电极部的剖面图。图13是图12所示的电路装置的焊垫电极部的平面图。第三实施例的电路装置与第一实施例的不同点在于，密封树脂层8与配线层3相接的区域8a设于与含金镀层4相接的连接区域8b的周围，且配线层3的终端部分覆盖绝缘树脂层5和含金镀层4之间的绝缘树脂层5。除此之外，与之前的第一实施例相同。
根据该第三实施例的电路装置，可得到如下效果。
(7)由于含金镀层4的周围被实施了粗面加工的更大面积的配线层3所包围，故可更有效地抑制密封树脂层8从焊垫电极3a的剥离。其结果提供可靠性提高的电路装置。
(第四实施例)
在上述实施例中，电路元件6和配线层3的焊垫电极经由含金镀层4进行引线连接，但也可以使电路元件6的电极形成面与配线层3的焊垫电极相对，使用焊料等倒装片连接电路元件6。另外，如上所述，电路元件6也可以是电阻、电容器等无源元件。再有，就衬底而言，作为一例，使用配线层2为两层的组合衬底，但不限于此。
图14是本发明第四实施例的电路装置的结构的平面图。图14中省略了密封树脂层。图15是图14的A-A’线上的剖面图。图16是表示第四实施例的电路装置的配线层及含金镀层的图形的图。另外，图17是表示第四实施例的电路装置的绝缘层的开口图形的图。图17中，虚线表示隐藏于绝缘层的不能识别到的部分。
第四实施例的电路装置含有LSI等电路元件6a、6b、及电阻、电容器等电路元件6C。如图16所示，在绝缘层2上将绝缘层3构图。在电路装置的中央部分设有用于倒装片连接的具有含金镀层4的倒装片焊垫200。在倒装片焊垫200的周围设有作为用于连接引线而具有含金镀层4的引线结合焊垫210。另外，在引线结合焊垫210的周围设有作为用于安装电路元件6c而具有含金镀层4的无源元件焊垫220。另外，倒装片焊垫200、引线结合焊垫210及无源元件焊垫220周边的详细结构也可以为第一～第三实施例中所示的任一种结构。
如图17所示，在绝缘树脂层5上设有开口，以使倒装片焊垫200、引线结合焊垫210及无源元件焊垫220及其周围的配线层3露出。
返回图14及图15，在第四实施例的电路装置中，电路元件6a经由焊料块250与倒装片焊垫用的含金镀层4倒装片连接。电路元件6b搭载于电路元件6a上，经由金属线等导电部件7与引线结合焊垫用的含金镀层4引线连接。另外，在电路元件6a及电路元件6b的周围设置的无源元件焊垫用的含金镀层4上，经由焊料260安装有电阻、电容器等电路元件6c。
在绝缘层2的下面侧设有规定图形的配线层270。配线层270经由通孔280与配线层3电连接。在配线层270的电极形成区域形成有含金镀层(电解镀Au/Ni膜)290。另外，在含金镀层290上形成有焊料块292。
根据该第四实施例的电路装置，可得到如下效果。
(8)倒装片连接用的焊垫电极、引线连接用的焊垫电极、及无源元件用的焊垫电极可享有上述(1)～(3)的效果。
(9)作为上述效果的结果，在叠加LSI等电路元件的多片组件中，可提高电路装置的可靠性。
另外，在第一～第三实施例中，显示了具有单层结构的配线层3的金属衬底的例子，但不限于此，例如在具有两层结构以上的结构的配线层中，若其最上层具有焊垫电极，则也可以应用。例如，上述实施例中也可以应用被称作ISB(Intcgrated System Board：注册商标)的封装结构。ISB是指，在以半导体裸片为中心的电子电路的封装中，具有采用铜的配线图形、并且不使用用于支承电路部件的芯材(基材)的独立的无芯系统封装(コアレスシステム·イン·パツケ一ジ)。例如，(日本)特开2002-110717号公报中公开的四层ISB结构应用于上述实施例是最佳的。
另外，在上述实施例中，表示了通过湿式处理进行的粗糙化的例子，但本发明不限于此，也可以通过等离子处理等将配线层3的表面粗糙化。该情况下，例如当进行采用了氩气的等离子照射的表面处理时，其表面成为具有微小凹凸的粗糙面。另外，该等离子处理中，含金镀层4的表面未粗面化。
再有，在上述实施例中，还可以将与密封树脂层8相接的配线层3、绝缘层2及绝缘树脂层5的面设为等离子处理面。由此，由于密封树脂层8的整个下面与等离子处理面相接，故锚定效果作用的面积增加，从而进一步改善密封树脂层8的密接性。

Claims (10)

1、一种电路装置，其特征在于，具有：
含有铜的配线层和具有在提供其表面进行电连接部分的局部形成的含金镀层的电极、
和覆盖所述电极整个面的密封树脂层，
所述密封树脂层被设置为与所述含金镀层及所述配线层相接。
2、一种电路装置，其特征在于，具有：
衬底；
形成于所述衬底上的含有铜的配线层；
形成于所述衬底及所述配线层上，在电极形成区域具有开口部的绝缘树脂层；
在提供设于所述开口部内的配线层的表面进行电连接的部分形成的含金镀层；
所述设于衬底上的电路元件；
经由所述含金镀层将所述电路元件和所述配线层电连接的导电部件；
形成于所述绝缘树脂层上，将所述电路元件及所述电极形成区域密封的密封树脂层，
所述密封树脂层被设置为与含金镀层及配线层相接。
3、如权利要求2所述的电路装置，其特征在于，所述电路元件是半导体元件。
4、如权利要求3所述的电路装置，其特征在于，使用所述导电部件将所述半导体元件引线连接。
5、如权利要求3所述的电路装置，其特征在于，使用所述导电部件将所述半导体元件倒装片连接。
6、如权利要求2所述的电路装置，其特征在于，所述电路元件是无源元件。
7、如权利要求1～6中任一项所述的电路装置，其特征在于，与所述密封树脂层相接的配线层的表面被实施粗面加工。
8、如权利要求1～7中任一项所述的电路装置，其特征在于，所述密封树脂层与所述配线层相接的区域设于与所述含金镀层相接的区域的周围。
9、一种电路装置的制造方法，其特征在于，具有：
在配线衬底的主面上形成配线层的工序；
在所述配线衬底的整个主面上形成导电层的工序；
在所述配线衬底的整个主面上形成在所述电极形成区域具有大于电极开口的第一绝缘层的工序；
将在所述开口露出的所述导电层除去，使所述配线层露出的工序；
将所述导电层作为镀敷用配线使用，在露出的所述配线层上形成含金镀层的工序；
除去所述第一绝缘层及所述导电层的工序；
在所述配线衬底的整个主面上形成具有使所述含金镀层和其附近的配线层露出的开口的第二绝缘层的工序；
将电路元件与所述含金镀层电连接的工序。
10、如权利要求9所述的电路装置的制造方法，其特征在于，在除去所述第一绝缘层及所述导电层的工序中，将露出的所述配线层的表面进行粗面加工。
CN2007101018784A 2006-04-27 2007-04-25 电路装置及电路装置的制造方法 Expired - Fee Related CN101064294B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP122954/06 2006-04-27
JP2006122954 2006-04-27
JP2007107649A JP4503039B2 (ja) 2006-04-27 2007-04-16 回路装置
JP107649/07 2007-04-16

Publications (2)

Publication Number Publication Date
CN101064294A true CN101064294A (zh) 2007-10-31
CN101064294B CN101064294B (zh) 2011-11-16

Family

ID=38647566

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101018784A Expired - Fee Related CN101064294B (zh) 2006-04-27 2007-04-25 电路装置及电路装置的制造方法

Country Status (4)

Country Link
US (2) US7612445B2 (zh)
JP (1) JP4503039B2 (zh)
KR (1) KR101061627B1 (zh)
CN (1) CN101064294B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104124561A (zh) * 2013-04-24 2014-10-29 泰科电子日本合同会社 电连接器组件及其安装构造
CN104218017A (zh) * 2013-05-31 2014-12-17 瑞萨电子株式会社 半导体装置

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4503039B2 (ja) * 2006-04-27 2010-07-14 三洋電機株式会社 回路装置
JP4498378B2 (ja) * 2007-03-30 2010-07-07 三洋電機株式会社 基板およびその製造方法、回路装置およびその製造方法
KR20090021605A (ko) * 2007-08-27 2009-03-04 삼성전기주식회사 반도체 메모리 패키지
JP4475364B2 (ja) 2008-03-14 2010-06-09 株式会社村田製作所 電極平滑化方法、セラミック基板の製造方法およびセラミック基板
US20090261462A1 (en) * 2008-04-16 2009-10-22 Jocel Gomez Semiconductor package with stacked die assembly
TWI365517B (en) * 2008-05-23 2012-06-01 Unimicron Technology Corp Circuit structure and manufactring method thereof
US8270176B2 (en) * 2008-08-08 2012-09-18 Stats Chippac Ltd. Exposed interconnect for a package on package system
KR101047139B1 (ko) * 2009-11-11 2011-07-07 삼성전기주식회사 단층 보드온칩 패키지 기판 및 그 제조방법
US8850196B2 (en) * 2010-03-29 2014-09-30 Motorola Solutions, Inc. Methods for authentication using near-field
US8411444B2 (en) * 2010-09-15 2013-04-02 International Business Machines Corporation Thermal interface material application for integrated circuit cooling
KR20120050755A (ko) * 2010-11-11 2012-05-21 삼성전기주식회사 반도체 패키지 기판 및 그 제조방법
US20120286416A1 (en) * 2011-05-11 2012-11-15 Tessera Research Llc Semiconductor chip package assembly and method for making same
KR20130078108A (ko) * 2011-12-30 2013-07-10 삼성전기주식회사 패키지 기판 및 그의 제조 방법
WO2013167653A1 (en) 2012-05-08 2013-11-14 Merck & Cie 18f-labelled folate/antifolate analogues
DE102012213917A1 (de) * 2012-08-06 2014-02-20 Robert Bosch Gmbh Bauelemente-Ummantelung für ein Elektronikmodul
KR20140060767A (ko) * 2012-11-12 2014-05-21 삼성전기주식회사 회로 기판 및 그 제조 방법
DE102013217892A1 (de) * 2012-12-20 2014-06-26 Continental Teves Ag & Co. Ohg Elektronische Vorrichtung und Verfahren zur Herstellung einer elektronischen Vorrichtung
JP5983523B2 (ja) * 2013-05-06 2016-08-31 株式会社デンソー 多層基板およびこれを用いた電子装置、電子装置の製造方法
JP6223909B2 (ja) * 2013-07-11 2017-11-01 新光電気工業株式会社 配線基板及びその製造方法
JP6131135B2 (ja) * 2013-07-11 2017-05-17 新光電気工業株式会社 配線基板及びその製造方法
KR20150019951A (ko) * 2013-08-16 2015-02-25 삼성디스플레이 주식회사 유기 발광 표시 장치
JP2019012712A (ja) * 2015-11-20 2019-01-24 三菱電機株式会社 電力用半導体装置および電力用半導体装置の製造方法
JP2016105512A (ja) * 2016-03-01 2016-06-09 京セラサーキットソリューションズ株式会社 配線基板の製造方法
US11476587B2 (en) * 2019-06-14 2022-10-18 City University Of Hong Kong Dielectric reflectarray antenna and method for making the same
JP7382170B2 (ja) 2019-08-02 2023-11-16 ローム株式会社 半導体装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2781020B2 (ja) * 1989-09-06 1998-07-30 モトローラ・インコーポレーテッド 半導体装置およびその製造方法
JPH06224325A (ja) * 1993-01-26 1994-08-12 Matsushita Electric Works Ltd 半導体装置
TW323432B (zh) * 1995-04-28 1997-12-21 Victor Company Of Japan
JP3366506B2 (ja) * 1995-09-01 2003-01-14 新光電気工業株式会社 半導体装置の製造方法
JP3483720B2 (ja) * 1997-02-12 2004-01-06 沖電気工業株式会社 半導体装置
JP3968788B2 (ja) 1997-03-21 2007-08-29 セイコーエプソン株式会社 半導体装置及びフィルムキャリアテープの製造方法
KR100328807B1 (ko) * 1998-05-08 2002-03-14 가네코 히사시 제조비용이 저렴하고 충분한 접착 강도가 수득될 수 있는 수지구조물 및 이의 제조 방법
JP2000294922A (ja) * 1999-04-01 2000-10-20 Victor Co Of Japan Ltd 多層プリント配線板用の絶縁樹脂組成物
JP3963655B2 (ja) 2001-03-22 2007-08-22 三洋電機株式会社 回路装置の製造方法
JP4044769B2 (ja) * 2002-02-22 2008-02-06 富士通株式会社 半導体装置用基板及びその製造方法及び半導体パッケージ
KR100499003B1 (ko) * 2002-12-12 2005-07-01 삼성전기주식회사 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법
US6853060B1 (en) 2003-04-22 2005-02-08 Amkor Technology, Inc. Semiconductor package using a printed circuit board and a method of manufacturing the same
JP2004327940A (ja) * 2003-04-28 2004-11-18 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
JP2005019648A (ja) 2003-06-25 2005-01-20 Kyocera Corp 光部品実装用基板およびその製造方法ならびに光モジュール
JP3770895B2 (ja) 2003-12-09 2006-04-26 新光電気工業株式会社 電解めっきを利用した配線基板の製造方法
JP2005183430A (ja) * 2003-12-16 2005-07-07 Matsushita Electric Ind Co Ltd 電子部品内蔵モジュール
JP2005235980A (ja) * 2004-02-19 2005-09-02 Dainippon Printing Co Ltd 配線基板の製造方法と配線基板、および半導体パッケージ
EP1619719B1 (en) * 2004-07-23 2012-04-25 Shinko Electric Industries Co., Ltd. Method of manufacturing a wiring board including electroplating
KR100785488B1 (ko) * 2005-04-06 2007-12-13 한국과학기술원 이미지 센서 모듈 및 이의 제조 방법
JP4503039B2 (ja) * 2006-04-27 2010-07-14 三洋電機株式会社 回路装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104124561A (zh) * 2013-04-24 2014-10-29 泰科电子日本合同会社 电连接器组件及其安装构造
CN104218017A (zh) * 2013-05-31 2014-12-17 瑞萨电子株式会社 半导体装置
CN104218017B (zh) * 2013-05-31 2018-12-18 瑞萨电子株式会社 半导体装置

Also Published As

Publication number Publication date
US8656581B2 (en) 2014-02-25
JP4503039B2 (ja) 2010-07-14
US20100005653A1 (en) 2010-01-14
CN101064294B (zh) 2011-11-16
KR20070105924A (ko) 2007-10-31
JP2007318098A (ja) 2007-12-06
US7612445B2 (en) 2009-11-03
KR101061627B1 (ko) 2011-09-01
US20070252249A1 (en) 2007-11-01

Similar Documents

Publication Publication Date Title
CN101064294A (zh) 电路装置及电路装置的制造方法
TWI453840B (zh) 半導體元件的製造方法
CN1574257A (zh) 半导体装置及其制造方法
US10490473B2 (en) Chip package module and circuit board structure comprising the same
CN1497717A (zh) 电路装置及其制造方法
CN1523665A (zh) 半导体装置及其制造方法
JP4498404B2 (ja) 素子搭載用基板およびその製造方法、半導体モジュールならびに携帯機器
CN1674277A (zh) 电路装置
CN1266752C (zh) 电路装置的制造方法
CN1722370A (zh) 半导体装置的制造方法
CN1658372A (zh) 半导体装置及其制造方法
CN1326225A (zh) 芯片倒装型半导体器件及其制造方法
CN1722429A (zh) 半导体器件
CN101060087A (zh) 电极及其制造方法,以及具有该电极的半导体器件
CN1638108A (zh) 一种制造半导体器件的方法
CN1531069A (zh) 电子装置及其制造方法
CN1700458A (zh) 具有第一和第二导电凸点的半导体封装及其制造方法
CN1819133A (zh) 半导体装置的制造方法以及电连接部的处理方法
CN1758431A (zh) 晶背上具有整合散热座的晶圆级封装以及晶片的散热方法
US9324636B2 (en) Resin-sealed semiconductor device and associated wiring and support structure
JP2009194079A (ja) 半導体装置用配線基板とその製造方法及びそれを用いた半導体装置
CN1254856C (zh) 电路装置的制造方法
CN1509134A (zh) 电路装置、电路模块及电路装置的制造方法
CN1531068A (zh) 电子装置及其制造方法
CN107210267A (zh) 半导体器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20111116