CN1658372A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1658372A
CN1658372A CN2005100093647A CN200510009364A CN1658372A CN 1658372 A CN1658372 A CN 1658372A CN 2005100093647 A CN2005100093647 A CN 2005100093647A CN 200510009364 A CN200510009364 A CN 200510009364A CN 1658372 A CN1658372 A CN 1658372A
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Prior art keywords
hole
pad electrode
interarea
semiconductor device
semiconductor substrate
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CN100385621C (zh
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龟山工次郎
铃木彰
冈山芳央
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract

一种半导体装置及其制造方法，谋求可靠性的提高。在形成有焊盘电极53的硅晶片(51)的表面粘接玻璃衬底(56)。其次，形成从硅晶片(51)的背面到达焊盘电极(53)的通孔(81)，同时，形成沿切割线中心DS延伸，且从硅晶片(51)的背面贯通硅晶片(51)的槽(82)。然后，利用含有伴随加热处理的工序的各种工序在硅晶片(51)的背面形成缓冲层(60)、配线层(63)、焊接掩模(65)、焊球(66)。最后，将支承在玻璃衬底(56)上的硅晶片(51)切割成各个硅片(51A)。

Description

半导体装置及其制造方法
技术领域
本发明涉及芯片尺寸封装型的半导体装置及其制造方法。
背景技术
近年来，作为三维安装技术且作为新的封装技术，CSP(芯片尺寸封装Chip Size Package)正引起人们的关注。所谓CSP是指具有与半导体芯片的外形尺寸大致相同尺寸的小型封装。
目前，作为CSP之一种，BGA型半导体装置是众所周知的。该BGA型半导体装置中，在封装的一主面上格子状排列多个由焊锡等金属部件构成的球状导电端子，使其与搭载于封装其它面上的半导体芯片电连接。
而且，在将该BGA型半导体装置装入电子设备时，通过在印刷线路板上的配线图案上压装各导电端子，将半导体芯片和搭载在印刷线路板上的外部电路电连接。
这种BGA型半导体装置与具有向侧部突出的引脚的SOP(Small OutlinePackage)或QFP(Quad Flat Package)等其它CSP型的半导体装置相比，可设置多个导电端子，而且具有可小型化的优点。该BGA型半导体装置具有例如作为搭载于手机上的数字相机的图像传感器芯片的用途。
图13是现有BGA型半导体装置的概略结构图，图13(A)是该BGA型半导体装置表面侧的立体图。图13(B)是该BGA型半导体装置背面侧的立体图。
该BGA型半导体装置101中，在第一及第二玻璃衬底102、103之间介由环氧树脂105a、105b密封有半导体芯片104。在第二玻璃衬底103的一主面上，即BGA型半导体装置101的背面上格子状配置多个导电端子106。该导电端子106介由第二配线110与半导体芯片104连接。多个第二配线110上分别连接从半导体芯片104内部引出的铝配线，将各导电端子106和半导体芯片104电连接。
参照图14进一步详细说明该BGA型半导体装置101的断面结构。图14显示沿切割线分割为一个个芯片的BGA型半导体装置101的断面图。
在配置于半导体芯片104表面上的绝缘膜108上设有第一配线107。该半导体芯片104通过树脂层105a与第一玻璃衬底102粘接。另外，该半导体芯片104的背面通过树脂层105b与第二玻璃衬底103粘接。
而且，第一配线107的一端与第二配线110连接。该第二配线110从第一配线107的一端延伸到第二玻璃衬底103的表面。在延伸到第二玻璃衬底103上的第二配线上形成有球状的导电端子106。
上述的技术记载于例如以下的专利文献1中。
专利文献1：特表2002-512436号公报
但是，在所述的BGA型半导体装置101中，由于第一配线107和第二配线110的接触面积非常小，故可能在该接触部分产生断线。另外，第二配线110的分步敷层也有问题。因此，本发明在具有BGA的半导体装置及其制造方法中，谋求可靠性的提高。
另外，在所述的半导体装置中，由于在半导体芯片104上介由环氧树脂粘接玻璃衬底102、103，粘接膨胀系数各不相同的物体，故在伴随热处理的各种操作工序中会产生半导体晶片的挠曲，操作性恶化。
发明内容
本发明提供一种半导体装置的制造方法，其包括：准备形成有焊盘电极的半导体衬底，并在所述半导体衬底的第一主面上粘接支承体的工序；在形成从所述半导体衬底的第二主面到达所述焊盘电极表面的通孔的同时，形成沿切割线延伸并从所述半导体衬底的第二主面贯通所述半导体衬底的槽的工序。
本发明在上述工序之外，还具有在进行形成所述槽的工序后，加热粘接有所述支承体的所述半导体衬底的工序。
本发明提供一种半导体装置，其包括：焊盘电极，其形成在半导体芯片的第一主面上；支承体，其粘接在所述半导体芯片的第一主面上；通孔，其从所述半导体芯片的第二主面贯通所述焊盘电极的表面；侧壁绝缘膜，其形成在所述通孔的侧壁及所述半导体芯片的侧面；配线层，其通过所述通孔，与所述焊盘电极电连接；保护层，其覆盖所述配线层上而形成；导电端子，其形成在所述配线层上。
本发明提供一种半导体装置，其包括：支承体，其被粘接在形成有焊盘电极的半导体衬底的第一主面上；通孔，其从所述半导体衬底的第二主面到达所述焊盘电极的表面；在沿切割线被切割的侧端部被蚀刻的面。
根据本发明，由于形成从半导体芯片的焊盘电极介由通孔直至其导电端子的配线，故可防止所述配线的断线或分步敷层的劣化。由此，可得到可靠性高的半导体装置。
另外，根据本发明，在加热粘接有支承衬底的半导体衬底的工序中，可最大限度地抑制支承衬底的热膨胀系数和半导体衬底的热膨胀系数的差异产生的挠曲。由此，可顺畅地进行向不同的工序搬运时的半导体衬底的运送，同时，可提高半导体装置的成品率。
根据本发明，由于在将粘接有支承衬底的半导体衬底分离成一个个半导体芯片后，半导体芯片的侧面被配线层及保护层覆盖，故可最大限度地防止水分侵入半导体芯片内。
附图说明
图1是说明本发明实施例的半导体装置制造方法的剖面图；
图2是说明本发明实施例的半导体装置制造方法的剖面图；
图3是说明本发明实施例的半导体装置制造方法的剖面图；
图4是说明本发明实施例的半导体装置制造方法的剖面图；
图5是说明本发明实施例的半导体装置制造方法的剖面图；
图6是说明本发明实施例的半导体装置制造方法的剖面图；
图7是说明本发明实施例的半导体装置制造方法的剖面图；
图8是说明本发明实施例的半导体装置制造方法的剖面图；
图9是说明本发明实施例的半导体装置制造方法的剖面图；
图10是说明本发明实施例的半导体装置制造方法的剖面图；
图11是说明本发明实施例的半导体装置及其制造方法的剖面图；
图12是说明本发明实施例的半导体装置制造方法的平面图；
图13(A)、(B)是说明现有的半导体装置的图；
图14是说明现有的半导体装置的图。
具体实施方式
其次，参照附图详细说明本实施例。首先，说明该半导体装置的结构。图11是该半导体装置的剖面图，其表示将经过后述的工序的半导体衬底即硅晶片51沿切割线区域DL的切割线中心DS分割成各个半导体芯片的情况。
作为半导体芯片的硅片51A是例如CCD(Charge Coupled Device)图像传感器芯片，在作为其第一主面的表面上介由BPSG等层间绝缘膜52形成有焊盘电极53。该焊盘电极53是将通常的用于引线接合的焊盘电极扩大到切割线区域DL的电极，其被称为扩张焊盘电极。
该焊盘电极53被氮化硅膜等钝化膜54覆盖。在形成有该焊盘电极53的硅片51A的表面上介由例如由环氧树脂构成的树脂层55粘接有玻璃衬底56。玻璃衬底56被作为保护硅片51A的保护衬底，及支承硅片51A的支承衬底使用。
在硅片51A为CCD图像传感器芯片时，由于必须利用硅片51A表面的CCD器件接收来自外部的光，故必须使用玻璃衬底56这样的透明衬底或半透明衬底。在硅片51A不接收或发射光时，也可以使用不透明衬底。
然后，形成从硅片51A的作为第二主面的背面到达焊盘电极53的通孔81。另外，在通孔81的侧壁及硅片51A的侧面形成侧壁绝缘膜59A。侧壁绝缘膜59A是使后述的配线层63和硅片51A电绝缘的绝缘膜。
另外，在硅片51A的背面与通孔81邻接的区域介由第一绝缘膜57形成缓冲层60。
然后，形成通过该通孔81电连接到焊盘电极53上，且从通孔81延伸到硅片51A的背面上及侧面的配线层63。配线层63也被称为再配线层，是例如在铜(Cu)上层积了Ni/Au等阻挡层64的结构。
在配线层63的下层设有籽晶层61，这是构成在利用电镀形成配线层63时使用的镀敷电极的金属层。配线层63向硅片51A的背面上延伸，覆盖缓冲层60。
然后，利用作为保护层的焊接掩模65覆盖配线层63，在焊接掩模65上，在缓冲层60上的部分形成开口部K。通过该焊接掩模65的开口部K搭载有作为导电端子的焊球66。由此，将焊球66和配线层63电连接。通过形成多个这种焊球66，可得到BGA结构。
这样，可进行从硅片51A的焊盘电极53直至形成在其背面的焊球66的配线。另外，由于通过通孔81进行配线，故不易引起断线，分步敷层也好。进而配线的机械强度也高。
由于硅片51A的侧面被配线层63及焊接掩模65覆盖，故可最大限度地防止水分向硅片51A内部侵入。
由于焊球66被配置在缓冲层60上，故在介由该焊球66将该半导体装置向印刷线路板上搭载时，缓冲层60作为一种缓冲器起作用，可缓和其冲击，防止损伤焊球66或作为主体的半导体装置。
另外，焊球66的形成位置比硅片51A的背面高出缓冲层60的厚度的量。由此，在将该半导体装置搭载于印刷线路板上时，可防止因印刷线路板和焊球66的热膨胀系数之差产生的应力而损伤焊球66或硅片51A。
另外，缓冲层60可使用有机绝缘物、无机绝缘物、金属、硅、光致抗蚀剂等各种材质，但要使其作为缓冲器起作用，则富有弹性的有机绝缘物、无机绝缘物、光致抗蚀剂等适合。
硅片51A也可以是GaAs、Ge、Si-Ge等其它材料的半导体芯片。
下面，说明上述本实施例的半导体装置的制造方法。如图1所示，在作为半导体衬底的硅晶片51的第一主面即表面上形成未图示的半导体集成电路(例如CCD图像传感器)。另外，图1表示在后述的切割工序中被切割的予定的邻接芯片的边界(即切割线区域DL附近)的剖面。
在该硅晶片51的表面上介由BPSG等层间绝缘膜52形成一对焊盘电极53。该一对焊盘电极53由铝、铝合金、铜等金属层构成，其厚度为1μm左右。另外，将一对焊盘电极53向切割线区域DL扩张，并将其扩张的端部配置在切割线区域DL的切割线中心DS的附近。
然后，形成覆盖一对焊盘电极53的氮化硅膜等的钝化膜54，进而在该钝化膜54上涂敷例如由环氧树脂构成的树脂层55。
然后，介由该树脂层55将玻璃衬底56粘接在硅晶片51的表面上。该玻璃衬底66作为硅晶片51的保护衬底或支承衬底起作用。另外，支承衬底不限于玻璃衬底56，也可以为例如金属衬底或由有机物构成的衬底状件或带状衬底。之后，在粘接了该玻璃衬底56的状态下，根据需要进行硅晶片51的背面蚀刻，即所谓的背面研磨，将其厚度加工为150μm左右。
然后，使用酸(例如HF和硝酸等的混合液)作为蚀刻剂，将硅晶片51蚀刻20μm左右。由此，机械地除去背面研磨产生的硅晶片51的机械性损伤层，对改善形成于硅晶片51表面上的器件的特性是有效的。在本实施例中，硅晶片51的最终完成的厚度为130μm左右，但也可以对应器件的种类进行适当的选择。
然后，在利用所述工序研削背面后的硅晶片51背面的整个面上形成第一绝缘膜57。该第一绝缘膜57通过例如等离子CVD法形成，且适用PE-SiO2膜或PE-SiN膜。另外，也可以省去第一绝缘膜57的形成。
其次，如图2所示，选择性地在第一绝缘膜57上形成光致抗蚀剂层58。以该光致抗蚀剂层58为掩模，进行第一绝缘膜57及硅晶片51的蚀刻。通过该蚀刻形成贯通硅晶片51的通孔81，同时，形成沿切割线区域DL的切割线中心DS附近延伸且贯通硅晶片51的槽82。另外，也可以省略所述第一绝缘膜57的形成工序，此时，以直接形成在硅晶片51上的光致抗蚀剂层58为掩模，进行硅晶片51的蚀刻。
要形成通孔81及槽82，有湿蚀刻方法和使用干蚀刻的方法。在本实施例中，使用至少包括SF6、O2或C2F4、C4F8或CHF3等CF系气体的蚀刻气体进行干蚀刻。关于通孔81，为了使后述的籽晶层61的包覆性良好，其断面形状也可以加工成正锥形。这样，通孔81和沿切割线形成的槽82具有被蚀刻的面。
在此，在通孔81的底部露出层间绝缘膜52，且与其相接具有焊盘电极53。通孔81的宽度为40μm左右，其长度为200μm左右。另外，在槽82的底部也露出层间绝缘膜52。槽82的深度与通孔81的长度相同(或相同程度)。即，利用槽82将硅晶片51在与玻璃衬底56粘接的状态下分离成各个硅片。由此，在后述的工序中，在进行加热处理(例如之后说明的喷溅工序中的加热处理或焊锡回流时的热处理)时，由于硅晶片51被单片化，故对应目前这样的硅晶片51的热膨胀系数的膨胀或收缩被分断，对应该热膨胀系数的膨胀或收缩被降低，只需考虑对应玻璃衬底56的热膨胀系数的膨胀或收缩即可，故与现有技术相比，可大幅度地降低挠曲的程度。另外，通过同时考虑对应作为粘接剂使用的环氧树脂的热膨胀系数的膨胀或收缩，进一步提高可靠性。
另外，在形成于硅晶片51上的通孔81、槽82及切割线区域DL的位置关系成为如从硅晶片51背面看时的平面图即图12所示。另外，焊盘电极53不限定于沿切割线形成。
其次，如图3所示，在形成有通孔81及槽82的硅晶片51的背面整体上形成第二绝缘膜59。第二绝缘膜59通过例如等离子CVD法形成，PE-SiO2膜或PE-SiN膜适用。第二绝缘膜59在通孔81的底部、侧壁、槽82的底部、侧壁及第一绝缘膜57上形成。
其次，如图4所示，邻接通孔81，在第二绝缘膜59上形成缓冲层60。缓冲层60可使用抗蚀剂薄膜，通过掩模曝光及显影处理形成在规定的区域。缓冲层60不限于此，也可以使用有机绝缘物或无机绝缘物、金属、硅、光致抗蚀剂等各种材料，但要使其具有缓冲器的功能，则富有弹性的有机绝缘物或无机绝缘物、光致抗蚀剂等适用。另外，也可以省略所述缓冲层60。
其次，如图5所示，不使用光致抗蚀剂层，进行各向异性干蚀刻。由此，仅在通孔81的侧壁及槽82的侧壁留下第二绝缘膜59，将其作为侧壁绝缘膜59A。另外，蚀刻除去位于通孔81和槽82底部的第二绝缘膜59及层间绝缘膜52。在通孔81的底部露出焊盘电极53。
这样，在本实施例中，在形成通孔81后，在通孔81内形成第二绝缘膜59，在形成缓冲层60后，蚀刻除去位于通孔81底部的第二绝缘膜59及层间绝缘膜52，露出焊盘电极53。
与此相对，也可以在蚀刻通孔81的底部并露出焊盘电极53之后，形成缓冲层60，但这种情况下，在形成缓冲层60时，露出的通孔81的底部被污染，之后，在通孔81内形成的配线层63和焊盘电极53的电连接可能产生不良。因此，如本实施例，最好在形成缓冲层60后，蚀刻通孔81的底部，由此可得到配线层63和焊盘电极53的良好的电连接。
另外，在图5的工序形成缓冲层60后，蚀刻通孔81内的绝缘膜，形成侧壁绝缘膜59A，利用该蚀刻将缓冲层60的表面粗糙化，还具有提高和后述的籽晶层61的附着性的优点。
其次，说明形成配线层63的工序。如图6所示，利用伴随加热处理的喷溅法、MOCVD法、无电解镀敷法等任意一种方法在从硅晶片51的背面侧到包括通孔81内及槽82内的硅晶片51的背面整体形成籽晶层61。籽晶层例如由铜(Cu)层、或钛钨(TiW)层或氮化钛(TiN)层、氮化钽(TaN)层等势垒金属层、或铜(Cu)层和势垒金属层的层积结构形成。在此，在通孔81内形成籽晶层61，使其与焊盘电极53电连接，且覆盖侧壁绝缘膜59A。
籽晶层61也覆盖缓冲层60。在此，构成籽晶层61的势垒金属层防止铜(Cu)通过侧壁绝缘膜59A扩散到硅晶片51中。但在侧壁绝缘膜59A有氮化硅膜(SiN膜)形成的情况下，由于氮化硅膜(SiN膜)构成相对铜扩散的势垒，故籽晶层61可仅由铜构成。
该籽晶层61为了后述的电镀时的镀敷成长而构成镀敷电极。其厚度为1μm左右即可。另外，在将通孔81加工成正锥形时，籽晶层61的形成可使用喷溅法。
其次，如图7所示，通过进行铜(Cu)的电镀形成配线层63。配线层63从通孔81引出到硅晶片51的背面，在该背面上延伸，覆盖缓冲层60。由此，配线层63与焊盘电极53电连接。另外，配线层53从硅晶片51的背面向槽82内延伸，覆盖其侧壁及底部。
另外，在图7中，配线层63被完全埋入通孔81内，但通过调整镀敷时间，也可以不完全埋入。另外，配线层63通过电镀被埋入通孔VH内而形成，但不限于此，也可以通过其它方法形成。例如，配线层63可通过CVD法或MOCVD法，或向通孔81内埋入铜(Cu)或铝(Al)等金属的方法形成。另外，配线层63可在硅晶片51背面的规定区域形成所希望的条数。
这样，由于介由通孔81形成从硅片51A的焊盘电极53到焊球66的配线层63，故与现有技术相比，可降低配线层63的断线或分布敷层的劣化。由此，与现有例相比，可得到可靠性高的BGA型半导体装置。
其次，如图8所示，利用镍(Ni)、金(Au)的无电解镀敷或喷溅法在配线层63上形成由Ni/Au层构成的阻挡层64。然后，如图9所示，在配线层63上覆盖作为保护层的焊接掩模65。焊接掩模65的缓冲层60上的部分被除去，设置开口部K。
然后，如图10所示，使用网印法在配线层63的规定区域上印刷焊锡，通过热处理使该焊锡回流，形成焊球66。焊球66不限于焊锡，也可以使用无铅低熔点金属材料形成。另外，焊球66可自由地选择其数量或形成区域而形成。不限于焊锡，也可以通过镀敷形成。
在此，焊球66形成在比硅片51A的背面高缓冲层60的膜厚的量的位置。由此，容易吸收该半导体装置向印刷线路板安装时产生的应力，可大幅度地防止焊球66的损伤。另外，由于焊球66形成在缓冲层60上，故可缓和向印刷线路板上安装半导体装置时的冲击，防止损伤半导体装置。
然后，如图11所示，沿切割线区域DL的切割线中心DS进行切割工序，将硅晶片51分割成多个硅片51A。在该切割工序中使用切割片进行切削。
在此，槽82形成各硅片51A的侧面。该硅片51A的侧面被侧壁绝缘膜59A、籽晶层61、配线层63、阻挡层64、焊接掩模65覆盖。由此，可最大限度地防止水分侵入硅片51内。
在所述的工序中，由于在伴随加热处理的工序，即利用喷溅法形成籽晶层61等时、或利用焊锡的回流形成焊球66时，硅晶片51在被槽82隔断的状态下支承在玻璃衬底56上(参照图12)，故玻璃衬底56和硅晶片51的热膨胀系数的差异产生的挠曲减小。由此，可顺畅地进行向不同工序前进时硅晶片51的搬运，同时，可提高半导体装置的成品率。
另外，在所述本实施例中，形成将通常用于引线接合的焊盘电极扩张到切割线区域DL而构成的焊盘电极53，但不限于此，也可以直接使用不扩张到切割线区域DL的通常用于引线接合的焊盘电极代替焊盘电极53。此时，只要使通孔81的形成位置与该焊盘电极对准即可，其它工序完全相同。
另外，本发明适用于形成有焊球66的BGA型半导体装置及其制造方法，但本发明不限于此，即，只要在形成贯通硅晶片的通孔的工序之后，包括伴随加热处理的工序，则本发明也适用于不形成焊球的半导体装置及其制造方法。例如也适用于LGA(Land Grid Array)型半导体装置及其制造方法。

Claims (9)

1、一种半导体装置的制造方法，其特征在于，包括：准备形成有焊盘电极的半导体衬底，并在所述半导体衬底的第一主面上粘接支承体的工序；在形成从所述半导体衬底的第二主面到达所述焊盘电极表面上的通孔的同时，形成沿切割线延伸并从所述半导体衬底的第二主面贯通所述半导体衬底的槽的工序。
2、如权利要求1所述的半导体装置的制造方法，其特征在于，具有在形成所述槽的工序后，加热粘接所述支承体的所述半导体衬底的工序。
3、一种半导体装置的制造方法，其特征在于，包括：准备形成有焊盘电极的半导体衬底，并在所述半导体衬底的第一主面上粘接支承体的工序；在形成从所述半导体衬底的第二主面到达所述焊盘电极表面的通孔的同时，形成沿切割线延伸并从所述半导体衬底的第二主面贯通所述半导体衬底的槽的工序；在包括所述通孔内的所述半导体衬底的第二主面的整个面上形成第一绝缘膜的工序；各向异性蚀刻所述第一绝缘膜，除去位于所述通孔底部的第一绝缘膜，在所述通孔及所述槽的侧壁形成侧壁绝缘膜的工序；形成通过所述通孔与所述焊盘电极电连接，且从所述通孔向所述槽内延伸的配线层的工序。
4、如权利要求3所述的半导体装置的制造方法，其特征在于，形成所述配线层的工序通过镀敷法或喷溅法进行。
5、如权利要求3所述的半导体装置的制造方法，其特征在于，具有形成覆盖在所述配线层上的保护层的工序和在所述配线层上形成导电端子的工序。
6、一种半导体装置，其特征在于，包括：焊盘电极，其形成在半导体芯片的第一主面上；支承体，其粘接在所述半导体芯片的第一主面上；通孔，其从所述半导体芯片的第二主面贯通所述焊盘电极的表面；侧壁绝缘膜，其形成在所述通孔的侧壁及所述半导体芯片的侧面；配线层，其通过所述通孔，与所述焊盘电极电连接。
7、如权利要求6所述的半导体装置，其特征在于，所述配线层由镀敷法或喷溅法形成。
8、如权利要求6所述的半导体装置，其特征在于，还包括：保护层，其覆盖所述配线层上；导电端子，其形成在所述配线层上。
9、一种半导体装置，其特征在于，包括：支承体，其粘接在形成有焊盘电极的半导体衬底的第一主面上；通孔，其从所述半导体衬底的第二主面到达所述焊盘电极的表面；在沿切割线被切割的侧端部被蚀刻的面。
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