CN100383938C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN100383938C
CN100383938C CNB2004100493984A CN200410049398A CN100383938C CN 100383938 C CN100383938 C CN 100383938C CN B2004100493984 A CNB2004100493984 A CN B2004100493984A CN 200410049398 A CN200410049398 A CN 200410049398A CN 100383938 C CN100383938 C CN 100383938C
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hole
wiring layer
semiconductor device
pad electrode
interarea
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CNB2004100493984A
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CN1574257A (zh
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高尾幸弘
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种半导体装置及其制造方法，该半导体装置具有可靠性高的BGA。在半导体衬底51的表面上形成焊盘电极53，将玻璃衬底56粘接在半导体衬底51的表面上。自半导体衬底51的背面至焊盘电极53的表面形成通孔VH。在包括通孔VH内的半导体衬底51背面的整个面上形成绝缘膜59。在绝缘膜59上形成缓冲层60。通过蚀刻除去通孔VH底部的绝缘膜59。形成与焊盘电极53电连接并自通孔VH在缓冲层60上延伸的配线层64。在配线层64上形成导电端子66。然后，将半导体衬底51分割为多个半导体芯片51A。

Description

半导体装置及其制造方法
技术领域
本发明涉及排列有多个球状导电端子的BGA(Ball Grid Array)型半导体装置及其制造方法。
背景技术
近年来，作为三维安装技术或作为新的封装技术，CSP(芯片尺寸封装(Chip Size Package))正在受到注目。所谓CSP是指具有和半导体芯片的外形尺寸大致相同尺寸的外形尺寸的小型封装。
目前，作为CSP的一种有BGA型半导体装置。该BGA型半导体装置将由焊料等金属部件构成的多个球状导电端子呈格子状排列在封装的一个主面上，并使其与搭载于封装另一主面上的半导体芯片电连接。
在将该BGA型半导体装置组装在电子设备中时，通过将各导电端子压装在印刷线路板上的配线图案上，使半导体芯片与搭载于印刷线路板上的外部电路电连接。
这种BGA型半导体装置与侧部具有突出的引线插头的SOP(SmallOutline Package)或QFP(Quad Flat Package)等其它CSP型半导体装置相比，可设置多个导电端子，且可小型化。该BGA型半导体装置具有作为例如搭载于手机上的数码相机的图像传感器芯片的用途。
图28是表示现有BGA型半导体装置的概略结构的图，图28(A)是该BGA型半导体装置的表面侧的立体图。图28(B)是该BGA型半导体装置的背面侧的立体图。
该BGA型半导体装置101将半导体芯片104介由环氧树脂层105a、105a密封在第一及第二玻璃衬底102、103之间。在第二玻璃衬底103的一个主面上即BGA型半导体装置101的背面上格子状配置有多个导电端子106。该导电端子106介由第二配线110与半导体芯片104连接。在多个第二配线110上连接有分别自半导体芯片104的内部引出的铝制的第一配线107，进行各导电端子106和半导体芯片104的电连接。
下面参照图29进一步详细说明该BGA型半导体装置101的断面结构。图29表示沿切割线分割为一个个芯片的BGA型半导体装置101的剖面图。
在配置于半导体芯片104表面的绝缘膜108上设有第一配线107。该半导体芯片104利用树脂层105a和第一玻璃衬底102粘接。该半导体芯片104的背面利用树脂层105b与第二玻璃衬底103粘接。
第一配线107的一端与第二配线110连接。该第二配线110自第一配线107的一端起在第二玻璃衬底103的表面延伸设置。在延伸设置于第二玻璃衬底103上的第二配线110上形成有球状导电端子106。
上述技术例如记载于以下的专利文献1中。
专利文献1：特表2002-512436号公报
但是，在上述BGA型半导体装置101中，由于第一配线107和第二配线110的接触面积非常小，故有可能在该接触部分断线。第二配线110的分步涂敷也有问题。
发明内容
本发明的半导体装置的制造方法包括：将支承衬底粘接在形成有焊盘电极的半导体衬底的第一主面上的工序；形成自所述半导体衬底的第二主面至所述焊盘电极的表面的通孔的工序；在包含所述通孔内部的所述半导体衬底的第二主面整个面上形成绝缘膜的工序；蚀刻所述绝缘膜，除去所述通孔底部的绝缘膜的工序；形成配线层的工序，所述配线层通过所述通孔与所述焊盘电极电连接，且自所述通孔延伸设置在所述第二主面上；在所述配线层上形成导电端子的工序；将所述半导体衬底分割成多个半导体芯片的工序。另外，还具有在所述绝缘膜上形成缓冲层的工序。
由此，可防止自半导体芯片的焊盘电极至所述导电端子的配线的断线或分步敷层的劣化，可得到可靠性高的BGA型半导体装置。由于导电端子形成于缓冲层上，故可缓和向印刷线路板安装时的冲击，防止半导体装置的损伤。
导电端子形成于比半导体芯片的第二主面高出缓冲层膜厚的量的位置。由此容易吸收该半导体装置向印刷线路板安装时产生的应力，可极大地防止导电端子的损伤。
另外，本发明提供一种半导体装置，包括：焊盘电极，其设于半导体衬底第一主面上；钝化膜，其覆盖所述焊盘电极；支承衬底，其粘接在所述半导体衬底的第一主面上；通孔，其形成于所述半导体衬底上，自所述半导体衬底的第二主面到达所述焊盘电极的表面；缓冲层，其形成于除所述通孔近旁外的所述半导体衬底第二主面整个面上；配线层，所述配线层通过所述通孔与所述焊盘电极电连接，并且自所述通孔延伸设置在所述缓冲层上；导电端子，其形成在于所述缓冲层上延伸的所述配线层部分上，与该配线层部分电连接。
附图说明
图1是说明本发明实施例1的半导体装置的制造方法的剖面图；
图2是说明本发明实施例1的半导体装置的制造方法的剖面图；
图3是说明本发明实施例1的半导体装置的制造方法的剖面图；
图4是说明本发明实施例1的半导体装置的制造方法的剖面图；
图5是说明本发明实施例1的半导体装置的制造方法的剖面图；
图6是说明本发明实施例1的半导体装置的制造方法的剖面图；
图7是说明本发明实施例1的半导体装置的制造方法的剖面图；
图8是说明本发明实施例1的半导体装置的制造方法的剖面图；
图9是说明本发明实施例1的半导体装置的制造方法的剖面图；
图10是说明本发明实施例1的半导体装置的制造方法的剖面图；
图11是说明本发明实施例1的半导体装置的制造方法的剖面图；
图12是说明本发明实施例1的半导体装置的制造方法的剖面图；
图13是说明本发明实施例2的半导体装置的制造方法的剖面图；
图14是说明本发明实施例2的半导体装置的制造方法的剖面图；
图15是说明本发明实施例2的半导体装置的制造方法的剖面图；
图16是说明本发明实施例3的半导体装置的制造方法的剖面图；
图17是说明本发明实施例3的半导体装置的制造方法的剖面图；
图18是说明本发明实施例3的半导体装置的制造方法的剖面图；
图19是说明本发明实施例3的半导体装置的制造方法的剖面图；
图20是说明本发明实施例3的半导体装置的制造方法的剖面图；
图21是说明本发明实施例3的半导体装置的制造方法的剖面图；
图22是说明本发明实施例3的半导体装置的制造方法的剖面图；
图23是说明本发明实施例3的半导体装置的制造方法的剖面图；
图24是说明本发明实施例3的半导体装置的制造方法的剖面图；
图25是说明本发明实施例3的半导体装置的制造方法的剖面图；
图26是说明本发明实施例3的半导体装置的制造方法的剖面图；
图27是说明本发明实施例3的半导体装置的制造方法的剖面图；
图28是说明现有半导体装置的图；
图29是说明现有半导体装置的图。
具体实施方式
下面参照附图详细说明本发明的实施例1。首先，说明该半导体装置的结构。图12是该半导体装置的剖面图，表示将经过后述工序的硅晶片沿切割线区域分割为一个个芯片的情况。图12中DS是切割线中心。
硅芯片51A是例如CCD图像传感器芯片，在其第一主面即表面上，介由BPSG等层间绝缘膜52形成有焊盘电极53。该焊盘电极53是将用于通常的引线接合的焊盘电极扩张至切割线区域而形成的，也称为扩张焊盘电极。
该焊盘电极53由氮化硅膜等钝化膜54被覆。在形成有该焊盘电极53的硅芯片51A的表面上，介由由例如环氧树脂构成的树脂层55粘接有玻璃衬底56。玻璃衬底56作为保护硅芯片51A的保护衬底或作为支承硅芯片51A的支承衬底使用。
在硅芯片51A为CCD图像传感器芯片的情况下，必须由硅芯片51A表面的CCD器件接收来自外部的光，故必须使用玻璃衬底56那样的透明衬底或半透明衬底。在硅芯片51A不是接收光或发光件的情况下也可为不透明衬底。
然后，自硅芯片51A的第二主面即背面至焊盘电极53形成通孔VH。在通孔VH的侧壁形成有侧壁绝缘膜59A。侧壁绝缘膜59A使后述的配线层63和硅芯片51A电绝缘。
在硅芯片51A的背面与通孔VH邻接的区域，介由第一绝缘膜57形成有缓冲层60。
然后，形成通过该通孔VH与焊盘电极53电连接并自通孔VH在硅芯片51A的背面上延伸设置的配线层63。配线层63也被称为再配线层，其结构为在例如铜(Cu)上层积Ni/Au等势垒层64的结构。
在配线层63的下层设有籽层61，其是构成利用电解镀敷形成配线层63时使用的镀敷电极的金属层。配线层63在硅芯片51A的背面上延伸，覆盖缓冲层60。
配线层63由作为保护膜的焊接掩模65覆盖，但在焊接掩模65上，在缓冲层60上的部分形成有开口部K。通过该焊接掩模65的开口部K搭载有作为导电端子的焊球66。由此使焊球66和配线层63电连接。通过形成多个这样的焊球66可得到BGA结构。
这样，可进行自硅芯片51A的焊盘电极53至形成于其背面的焊球66的配线。由于是通过通孔VH进行配线，故不容易产生断线，分步敷层也很优良。且配线的机械强度也高。
焊球66由于配置在缓冲层60上，故在介由该焊球66将该半导体装置搭载于印刷线路板时，缓冲层60作为一种缓冲器起作用，缓和其冲击，防止焊球66或作为本体的半导体装置损伤。
焊球66的形成位置比硅芯片51A的背面高出缓冲层60的厚度的量。由此，在将该半导体装置搭载于印刷线路板上时，可防止因由印刷线路板和焊球66的热膨胀系数之差产生的应力而损伤焊球66或硅芯片51A。
缓冲层60可使用有机绝缘物或无机绝缘物、金属、硅、光致抗蚀剂等各种材质，但为了作为缓冲器起作用最好为富有弹性的有机绝缘物或无机绝缘物、光致抗蚀剂等。
硅芯片51A也可是GaAs、Ge、Si-Ge等其它材料的半导体芯片。玻璃衬底56最好具有与硅芯片51A的热膨胀系数Ks接近的热膨胀系数Kg。其热膨胀系数Kg的范围在Si的热膨胀系数Ks(2.6～3.0ppm/°K)的±30％以内。也就是说，若玻璃衬底的热膨胀系数为Kg，所述晶片51的热膨胀系数为Ks，则0.7Ks≤Kg≤1.3Ks的关系成立。
由此，可防止玻璃衬底56和硅晶片51的热膨胀系数之差引起的玻璃衬底56的挠曲。在硅芯片51A为其它材料的半导体芯片时也同样如此。
下面说明该半导体装置的制造方法。如图1所示，在硅晶片51的第一主面即表面上形成有未图示的半导体集成电路(例如CCD图像传感器)。另外，图1表示要在后述切割工序切割的预定的邻接芯片的边界的断面。
在该硅晶片51的表面上介由BPSG等层间绝缘膜52形成一对焊盘电极53。该一对焊盘电极53例如由铝、铝合金、铜等金属层构成，其厚度为1μm左右。一对焊盘电极53被扩张至切割线区域DL，其扩张的端部配置在切割线中心DS的近前。
然后，形成覆盖一对焊盘电极53的氮化硅膜等钝化膜54，再在该钝化膜54上涂敷例如由环氧树脂构成的树脂层55。
然后，介由该树脂层55将玻璃衬底56粘接在硅晶片51的表面上。该玻璃衬底56作为硅晶片51的保护衬底或支承衬底起作用。然后，在粘接有该玻璃衬底56的状态下，根据需要进行硅晶片51的背面蚀刻或所谓背面研磨，将其厚度加工为150μm左右。
然后，使用酸(例如HF和硝酸等的混合液)作为蚀刻剂，将硅晶片51蚀刻20μm左右。由此除去背面研磨产生的硅晶片51的机械损伤层，有利于改善形成于硅晶片51表面上的器件的特性。在本实施例中，硅晶片51的最终成品的厚度为130μm左右，但这可根据器件的种类适当选择。
之后，在上述工序中背面被研削的硅晶片51的背面整个面上形成第一绝缘膜57。该第一绝缘膜57例如由等离子CVD法形成，最好为PE-SiO2膜或PE-SiN膜。
然后，如图2所示，在第一绝缘膜57上选择性形成光致抗蚀剂层58，以该光致抗蚀剂层58为掩模，进行第一绝缘膜57及硅晶片51的蚀刻，形成贯通硅晶片51的通孔VH。在通孔VH的底部露出层间绝缘膜52，焊盘电极53与其相接。通孔VH的宽度为40μm左右，其长度为200μm左右。
为了形成通孔VH，有使用激光束蚀刻的方法或使用干式蚀刻的方法。为了提高后述的籽层61的被覆性，该通孔VH的断面形状最好加工成正锥形。
然后，如图3所示，在形成有通孔VH的硅晶片51的整个背面形成第二绝缘膜59。第二绝缘膜59例如由等离子CVD法形成，最好为PE-SiO2膜或PE-SiN膜。第二绝缘膜59形成于通孔VH的底部、侧壁及第一绝缘膜57上。
之后，如图4所示，邻接通孔VH，在第二绝缘膜59上形成缓冲层60。缓冲层60使用薄膜抗蚀剂，可利用掩模曝光及显影处理形成于规定区域。缓冲层60不限于此，可采用有机绝缘物或无机绝缘物、金属、硅、光致抗蚀剂等各种材质，但为了作为缓冲器起作用最好为富有弹性的有机绝缘物或无机绝缘物、光致抗蚀剂等。
之后，如图5所示，不使用光致抗蚀剂层而进行各向异性的干式蚀刻。仅在通孔VH的侧壁留下第二绝缘膜59，这形成侧壁绝缘膜59A。在该蚀刻工序中，蚀刻除去通孔VH底部的第二绝缘膜59及层间绝缘膜52，露出焊盘电极53。另外，在蚀刻第二绝缘膜59时仅蚀刻除去通孔VH底部的第二绝缘膜59的工艺中可省略第一绝缘膜57的形成工序。
这样，本实施例中，在形成通孔VH后，在VH通孔中形成第二绝缘膜59，并形成缓冲层60，然后，蚀刻除去通孔VH底部的第二绝缘膜59及层间绝缘膜52，露出焊盘电极53。
与此相对，也可在蚀刻通孔VH的底部而露出焊盘电极53后，形成缓冲层60，这样，在形成缓冲层60时，露出的通孔VH的底部有可能被污染，之后形成于通孔VH内的配线层63和焊盘电极53的电连接有可能产生不良。因此，如本实施例这样，在形成缓冲层60后蚀刻通孔VH的底部对得到配线层63和焊盘电极53的良好电连接是理想的。
在图5的工序中，是在形成缓冲层60后蚀刻通孔VH内的绝缘膜形成侧壁绝缘膜59A，利用该蚀刻使缓冲层60的表面粗糙化，还有利于提高其与后述籽层61的粘附性。
下面说明形成配线层63的工序。如图6所示，利用喷溅法、MOCVD法、无电解镀敷等中的某种方法自硅晶片51的背面侧，在包含通孔VH的整个面上形成铜(Cu)层、或者钨化钛(TiW)层或氮化钛(TiN)层、氮化钽(TaN)层等势垒金属层、或者铜(Cu)层和势垒金属层的层积结构构成的籽层61。籽层61在通孔VH内与焊盘电极53电连接且覆盖侧壁绝缘膜59A。
籽层61也覆盖缓冲层60。这里，构成籽层61的势垒金属层防止铜(Cu)通过侧壁绝缘膜59A扩散到硅晶片51中。但在侧壁绝缘膜59A由SiN膜形成的情况下，由于SiN膜相对铜扩散形成势垒，故籽层61仅为铜(Cu)也没问题。
籽层61形成后述的电解镀敷时用于镀层成长的镀敷电极。其厚度为1μm左右即可。另外，在通孔VH加工成正锥形的情况下，形成籽层61时可使用喷溅法。
然后，进行铜(Cu)的电解镀敷，但之前要在不形成镀膜的区域选择性地形成光致抗蚀剂层62(图7)。该区域是除配线层63及焊球形成区域外的区域。
然后，如图8所示，通过进行图(Cu)的电解镀敷形成配线层63。配线层63自通孔VH被引出到硅晶片51的背面，在该背面上延伸，覆盖缓冲层60。这样，配线层63与焊盘电极53电连接。另外，在图8中，配线层63完全埋入通孔VH内，但也可通过调节镀敷时间而不完全埋入。
然后，除去光致抗蚀剂层62，以配线层63为掩模，利用蚀刻除去残留在光致抗蚀剂层62之下的籽层61。此时，配线层63也会被蚀刻，但由于配线层63比籽层61厚，故没有问题。
之后，如图9所示，通过镍(Ni)、金(Au)的无电解镀敷或利用喷溅法，在配线层63上形成由Ni/Au层构成的势垒层64。
然后，如图10所示，在配线层63上被覆焊接掩模65。除去焊接掩模65的位于缓冲层60上的部分，设置开口部K。
然后，如图11所示，利用网印法，在配线层63的规定区域上印刷焊料，通过热处理使该焊料回流，形成焊球66。焊球66不限于焊料，也可以用无铅的低熔点金属材料形成。
另外，配线层63可在硅晶片51背面的规定区域形成所需的条数，焊球66的数量或形成区域也可以自由选择。
然后，如图12所示，沿切割线中心DS进行切割工序，将硅晶片51分割为多个硅芯片51A。在该切割工序中，可使用切割刀或激光束。在切割工序中，玻璃衬底56的切断面被加工成倾斜状，从而可防止玻璃衬底56的开裂。
下面参照附图详细说明本发明的实施例2。首先说明该半导体装置的结构。图15是该半导体装置的剖面图，表示，将经过后述工序的硅晶片沿切割线分割为一个个芯片的状态。
图15中，DS是划线中心。另外，图15中对与实施例1的图12相同的结构部分赋予同一符号并省略详细说明。
在本实施例中，缓冲层60A形成于硅芯片51A背面的除通孔VH近旁外的整个面上。配线层63自通孔VH升到缓冲层60A，在缓冲层60A上延伸，其终端位于缓冲层60A上。由此，与实施例1相比，提高了形成于缓冲层60A上的配线层64及焊接掩模65的分步敷层。除此之外与实施例1相同。
下面说明本实施例的半导体装置的制造方法，最初的工序至形成第二绝缘膜59的工序(图1～图3的工序)与实施例1完全相同。
在形成第二绝缘膜59后，如图13所示，除通孔VH的近旁外，在硅芯片51A背面的整个面上形成缓冲层60A。
然后，如图14所示，与实施例1同样，形成配线层63、焊接掩模65、焊球66等。之后，如图15所示，沿切割线中心DS进行切割工序，将硅晶片51分割为多个硅芯片51A。
下面参照附图详细说明本发明的实施例3。在实施例1及2中是在通孔VH内形成配线层63之前，形成缓冲层60、60A，但在本实施例中是在通孔VH内形成埋入配线层后，形成缓冲层73。
下面，参照图16～图27详细说明。如图16所示，蚀刻除去通孔VH底部的第二绝缘膜59及层间绝缘膜52，露出焊盘电极53。此时，还未形成缓冲层73，这一点与实施例1不同，其余与实施例1相同。
如图17所示，利用喷溅法、MOCVD法、无电解镀敷等中的某种方法自硅晶片51的背面侧，在包含通孔VH内的整个面上形成铜(Cu)层、或者钨化钛(TiW)层或氮化钛(TiN)层、氮化钽(TaN)层等势垒金属层、或者铜(Cu)层和势垒金属层的层积结构构成的籽层61A。
籽层61A在通孔VH内与焊盘电极53电连接且覆盖侧壁绝缘膜59A。籽层61A形成电解镀敷时用于镀层成长的镀敷电极。其厚度为1μm左右即可。另外，在通孔VH加工成正锥形的情况下，形成籽层61时可使用喷溅法。
然后，如图18所示，在包含通孔VH内的硅晶片51的背面整个面上进行铜(Cu)的电解镀敷，形成镀层70。通孔VH内由镀层70完全或不完全充填。
然后如图19所示，在埋入通孔VH的镀层70的部分上，利用曝光、显影处理选择性地形成光致抗蚀剂层71。
然后，如图20所示，以光致抗蚀剂层71为掩模，蚀刻未由光致抗蚀剂层71被覆的镀层70的部分，并蚀刻其下层的籽层61A，除去它们。由此，在光致抗蚀剂层71下层形成选择性埋入通孔VH内的埋入电极72。
然后，如图21所示，除去光致抗蚀剂层71，与埋入电极72邻接，在第一绝缘膜57上形成缓冲层73。
然后，如图22所示，再次在硅晶片51背面整个面上形成籽层74。另外，为了提高籽层74和第一绝缘膜57的粘附性，也可以在籽层74和第一绝缘膜57之间夹设TiN等的势垒膜。尤其是在第一绝缘膜57由SiN膜构成的情况下很有效。
然后，在籽层74上形成光致抗蚀剂层75。光致抗蚀剂层75选择性地形成于不形成镀膜的区域。籽层74例如由Cu层或Cu/Cr层构成。
然后，如图23所示，通过进行铜(Cu)的电解镀敷，形成配线层76。配线层76通过被覆埋入电极72的全部或一部分，与其电连接，并延伸而被覆缓冲层73。
然后，如图24所示，在除去光致抗蚀剂层75后，通过镍(Ni)、金(Au)的无电解镀敷，在配线层76上形成由Ni/Au层构成的势垒层77。
这里，配线层76是由电解镀敷法形成的，但也可以利用喷溅法使铝或铝合金在硅晶片51的整个背面成膜，然后，利用刻蚀工艺及蚀刻，选择性地形成配线层76。这种情况下，最好在其与铝或铝合金和Cu构成的埋入电极72之间作为势垒膜(Cu的扩散防止膜)由电解镀敷形成Ni膜或TiN等的势垒膜。
之后，如图25所示，在由势垒层77覆盖的配线层76上被覆焊接掩模78。除去焊接掩模78的位于缓冲层73上的部分，设置开口部K。
然后，如图26所示，利用网印法，在由开口部K露出、由势垒层77覆盖的配线层76上印刷焊料，通过热处理使该焊料回流，形成焊球79。配线层76可在硅晶片51背面的规定区域形成所需的条数，焊球66的数量或形成区域也可以自由选择。
然后，如图27所示，沿切割线中心DS进行切割工序，将硅晶片51分割为多个硅芯片51A。在该切割工序中，可使用切割刀或激光束。在切割工序中，玻璃衬底56的切断面被加工成倾斜状，从而可防止玻璃衬底56的开裂。
在上述实施例1、2中，在通孔VH内利用电解镀敷埋入、形成配线层64、64A，在实施例3中，利用电解镀敷，在通孔VH内形成埋入电极71，但不限于此，也可以采用其它方法。例如可举出利用CVD法或MOCVD法将铜(Cu)等金属埋入通孔VH内的方法。
另外，在上述实施例1、2、3中，是形成将用于通常的引线接合的焊盘电极扩张至切割线区域构成的焊盘电极53，但不限于此，也可以直接利用不扩张至切割线区域DL的用于通常的引线接合的焊盘电极取代焊盘电极53。这种情况下，只要使通孔VH的形成位置与该焊盘电极对准即可，其它工序完全相同。
根据本发明，可防止自半导体芯片的焊盘电极至其导电端子的配线的断线或分步敷层的劣化，可得到可靠性高的BGA型半导体装置。由于导电端子形成于缓冲层上，故可缓和向印刷线路板安装时的冲击，防止半导体装置的损伤。
导电端子位于比半导体芯片的第二主面高出缓冲层膜厚的位置。这样容易吸收该半导体装置安装在印刷线路板上时产生的应力，可最大限度防止导电端子的损伤。

Claims (11)

1.一种半导体装置的制造方法，其特征在于，其包括：将支承衬底粘接在形成有焊盘电极的半导体衬底的第一主面上的工序；形成自所述半导体衬底的第二主面至所述焊盘电极的表面的通孔的工序；在所述通孔的内部和所述半导体衬底的第二主面整个面上形成绝缘膜的工序；蚀刻所述绝缘膜，除去所述通孔底部的绝缘膜的工序；形成配线层的工序，所述配线层通过所述通孔与所述焊盘电极电连接，且自所述通孔延伸设置在所述第二主面上；在所述配线层上形成导电端子的工序；将所述半导体衬底分割成多个半导体芯片的工序。
2.如权利要求1所述的半导体装置的制造方法，其特征在于，所述形成配线层的工序利用电解镀敷法或喷溅法进行。
3.如权利要求1所述的半导体装置的制造方法，其特征在于，还包括在所述绝缘膜上形成缓冲层的工序，所述缓冲层形成于除所述通孔近旁外的所述半导体衬底第二主面整个面上。
4.如权利要求1所述的半导体装置的制造方法，其特征在于，设所述支承衬底的热膨胀系数为Kg、所述半导体衬底的热膨胀系数为Ks，则
0.7Ks≤Kg≤1.3Ks的关系成立。
5.如权利要求1所述的半导体装置的制造方法，其特征在于，包括：在形成所述配线层的工序之前，形成埋入到所述通孔中并与所述焊盘电极电连接的埋入电极的工序；在所述第二主面上形成缓冲层的工序，
形成所述配线层的工序使配线层与所述埋入电极电连接并使其在所述缓冲层上延伸。
6.如权利要求5所述的半导体装置的制造方法，其特征在于，所述形成埋入电极的工序利用电解镀敷法或喷溅法进行。
7.如权利要求1所述的半导体装置的制造方法，其特征在于，所述配线层不完全地埋入所述通孔内。
8.一种半导体装置，其特征在于，其包括：焊盘电极，其设于半导体衬底第一主面上；钝化膜，其覆盖所述焊盘电极；支承衬底，其粘接在所述半导体衬底的第一主面上；通孔，其形成于所述半导体衬底上，自所述半导体衬底的第二主面到达所述焊盘电极的表面；缓冲层，其形成于除所述通孔近旁外的所述半导体衬底第二主面整个面上；配线层，所述配线层通过所述通孔与所述焊盘电极电连接，并且自所述通孔延伸设置在所述缓冲层上；导电端子，其形成在于所述缓冲层上延伸的所述配线层部分上，与该配线层部分电连接。
9.如权利要求8所述的半导体装置，其特征在于，还包括绝缘层，所述绝缘层形成于所述通孔的侧壁上，使所述配线层和所述半导体芯片电绝缘。
10.如权利要求8所述的半导体装置，其特征在于，设所述支承衬底的热膨胀系数为Kg、所述半导体衬底的热膨胀系数为Ks，则
0.7Ks≤Kg≤1.3Ks的关系成立。
11.如权利要求8所述的半导体装置，其特征在于，所述配线层不完全地埋入所述通孔内。
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US8101496B2 (en) 2012-01-24
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