CN100370607C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN100370607C
CN100370607C CNB2004100476315A CN200410047631A CN100370607C CN 100370607 C CN100370607 C CN 100370607C CN B2004100476315 A CNB2004100476315 A CN B2004100476315A CN 200410047631 A CN200410047631 A CN 200410047631A CN 100370607 C CN100370607 C CN 100370607C
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wiring layer
semiconductor
hole
interarea
semiconductor device
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CN1574324A (zh
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高尾幸弘
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Sanyo Electric Co Ltd
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Abstract

一种半导体装置及其制造方法，可防止断线或分步敷层的劣化，具有高可靠性的BGA。在硅芯片(51A)的表面形成有焊盘电极(53)。设有自硅芯片(51A)的背面贯通硅芯片(51A)到达焊盘电极(11)的通孔(VH)，在该通孔(VH)内通过硅芯片(51A)背面的配线层(64)，和焊盘电极(53)电连接。然后，配线层(64)覆盖硅芯片(51A)背面的硅凸部(58)，并在该硅凸部(58)上的配线层(64)的部分形成焊球(66)。

Description

半导体装置及其制造方法
技术领域
本发明涉及排列有多个球状导电端子的BGA(Ball Grid Array)型半导体装置及其制造方法。
背景技术
近年来，作为三维安装技术，并且作为新的封装技术，CSP(芯片尺寸封装(Chip Size Package))受到人们的关注。所谓CPS是指具有和半导体芯片外形尺寸大致相同外形尺寸的小型封装。
以前，作为CSP的一种，BGA型半导体装置是公知的。该BGA型半导体装置是在封装的一主面上格子状排列多个由焊锡等金属材料构成的球状导电端子，并使其和搭载于封装其它面上的半导体芯片电连接的装置。
在将该BGA型半导体装置装入电子设备中时，通过将各导电端子压装在印刷线路板上的配线图案上，将半导体芯片和搭载于印刷线路板上的外部电路电连接。
这样的BGA型半导体装置与侧部具有突出的引线插头的SOP(SmallOutline Package)或QFP(Quad Flat Package)等其它CSP型半导体装置相比，具有可设置多个导电端子，且可小型化的优点。该BGA型半导体装置具有作为搭载在例如手机中的数码相机的图象传感器芯片的用途。
图20是形成现有BGA型半导体装置的概略结构的图，图20(A)是BGA型半导体装置表面侧的立体图。图20(B)是该BGA型半导体装置背面侧的立体图。
该BGA型半导体装置101中，介由环氧树脂层105a、105b将半导体芯片104密封在第一及第二玻璃衬底102、103之间。在第二玻璃衬底103的一主面上，也就是BGA型半导体装置101的背面上以格子状配置有多个球状导电端子106。该导电端子106通过第二配线110连接至半导体芯片104。在多个第二配线110上各自连接有由半导体芯片104内部引出的铝配线，使各球状导电端子106和半导体芯片104电连接。
参照图21更加详细地说明该BGA型半导体装置101的剖面结构。图21显示沿切割线分离成一个个芯片的BGA型半导体装置101的剖面图。
在配置于半导体芯片104表面的绝缘膜108上设置有第一配线107。该半导体芯片104利用树脂层105a和第一玻璃衬底102粘接。该半导体芯片104的背面通过树脂层105和第二玻璃衬底103粘接。
第一配线107的一端和第二配线110连接。该第二配线110自第一配线107的一端在第二玻璃衬底103的表面延伸。然后，在延伸设置于第二玻璃衬底103上的第二配线上形成球状导电端子106。
所述的技术记载于例如如下的专利文献1中。
专利文献
特表2002-512436号公报
发明内容
但是，在所述的BGA型半导体装置101中，第一配线107和第二配线110的接触面积非常小，故有可能在该接触部分断线。在第二配线110的分步敷层方面也有问题。
因此，在本发明的半导体装置中，在半导体芯片的第一主面上设置焊盘电极，在半导体芯片的第二主面上设置半导体凸部，在设置有焊盘电极的半导体芯片的第一主面上粘接支承衬底。然后，自半导体芯片的第二主面至焊盘电极的表面形成通孔，通过该通孔和焊盘电极电连接，形成自该通孔在半导体芯片的第二主面上延伸的、覆盖半导体凸部的配线层。另外，在覆盖半导体凸部的配线层部分上形成和该配线层部分电连接的导电端子。
这样，可防止自半导体芯片的焊盘电极至该导电端子的配线的断线或分步敷层的劣化，可得到可靠性高的BGA型半导体装置。再有，由于导电端子形成在半导体凸部上，故导电端子形成于比半导体芯片的第二主面高出所述凸部的高度的位置。由此，容易缓和该半导体装置向印刷线路板安装时产生的热应力，可尽可能地防止导电端子的损伤。
附图说明
图1是说明本发明第一实施例的半导体装置制造方法的剖面图；
图2是说明本发明第一实施例的半导体装置制造方法的剖面图；
图3是说明本发明第一实施例的半导体装置制造方法的剖面图；
图4是说明本发明第一实施例的半导体装置制造方法的剖面图；
图5是说明本发明第一实施例的半导体装置制造方法的剖面图；
图6是说明本发明第一实施例的半导体装置制造方法的剖面图；
图7是说明本发明第一实施例的半导体装置制造方法的剖面图；
图8是说明本发明第一实施例的半导体装置制造方法的剖面图；
图9是说明本发明第一实施例的半导体装置制造方法的剖面图；
图10是说明本发明第一实施例的半导体装置制造方法的剖面图；
图11是说明本发明第一实施例的半导体装置制造方法的剖面图；
图12是说明本发明第一实施例的半导体装置制造方法的剖面图；
图13是说明本发明第一实施例的半导体装置制造方法的剖面图；
图14是说明本发明第一实施例的半导体装置及其制造方法的剖面图；
图15是说明本发明第二实施例的半导体装置制造方法的剖面图；
图16是说明本发明第二实施例的半导体装置制造方法的剖面图；
图17是说明本发明第二实施例的半导体装置制造方法的剖面图；
图18是说明本发明第二实施例的半导体装置制造方法的剖面图；
图19是说明本发明第二实施例的半导体装置及其制造方法的剖面图；
图20是说明现有的半导体装置的图；
图21是说明现有的半导体装置的图。
具体实施方式
下面，参照附图详细说明本发明第一实施例。首先，说明该半导体装置的结构。图14是该半导体装置的剖面图，沿切割线区域将经过后述的工序的硅晶片分割成一个个芯片，在图14中，DS是切割线的中心。
硅芯片51A是例如CCD图象传感器芯片，在作为其第一主面的表面上介由BPSG等层间绝缘膜52形成有焊盘电极53。该焊盘电极53是将用于通常的引线结合的焊盘电极扩张至切割线区域的电极，也被称为扩张电极。
该焊盘电极53被硅氮化膜等钝化膜54覆盖。在形成该焊盘电极53的硅芯片51的表面介由由例如环氧树脂构成的树脂层55粘接有玻璃衬底56。玻璃衬底56被作为支承硅芯片51A的支承衬底使用。硅芯片51A在CCD图象传感器的情况下，必须由硅芯片51A表面的CCD器件接收来自外部的光，故必须使用玻璃衬底56那样的透明衬底或半透明衬底。在硅芯片51A不接收光、不发光的情况下，也可以使用不透明衬底。
然后，形成自作为硅芯片51A的第二主面的背面到焊盘电极53的通孔VH。在通孔VH的侧壁形成有侧壁绝缘膜61A。侧壁绝缘膜61A使后述的配线层64和硅芯片51A电绝缘。
在硅芯片51A的背面，和通孔VH邻接的区域形成有硅凸部58。如后所述，通过选择性地蚀刻硅衬底形成硅凸部58，以硅芯片51A的背面为基准，其高度h为35um左右，但该高度越高对缓和向印刷线路板安装时产生的热应力越有效。另外，硅凸部58的底部宽度W1为400um左右，其根据焊球的直径来决定。硅凸部58的上部宽度W2为340um左右。硅芯片51A的厚度为135um左右。
然后，利用第一绝缘膜59覆盖硅芯片51A的背面及硅凸部58。该第一绝缘膜59是电绝缘配线层64和硅芯片51A的绝缘膜。
然后形成通过该通孔VH与焊盘电极53电连接，且自通孔VH起在硅芯片51A的背面上延伸的配线层64。配线层64也被称为再配线层，其是在例如铜(Cu)上层积Ni/Au等势垒金属构成的结构。在配线层64的下层设置有种层62，这是作为由利用电镀形成配线层64时使用的电镀电极的金属层。
在采用如Cu配线那样对硅的扩散倾向强的金属时，为防止Cu扩散产生的器件特性的恶化，必须在种层62下形成势垒层(例如TiN层、TiW层)。配线层64覆盖硅凸部58在硅芯片51A的背面上延伸。
配线层64利用作为保护膜的焊接掩膜65覆盖，在焊接掩膜65上，在硅凸部58上的部分形成开口部K。通过该焊接掩膜65的开口部K搭载作为导电端子的焊球66。由此，将焊球66和配线层64电连接。通过形成多个这样的焊球66，可得到BGA结构。
这样，自硅芯片51A的焊盘电极53至形成在其背面的焊球66的配线成为可能。另外，由于是通过通孔VH配线，故不容易产生断线，分步敷层也优良。配线的机械强度也高。再有，焊球66被配置在硅凸部58上，故其形成位置比硅芯片51A的背面高出该凸部的量。由此，在印刷线路板上安装该半导体装置时，可防止由印刷线路板和焊球66的热膨胀率差产生的应力损伤焊球66或硅芯片51A。
其次，说明该半导体装置的制造方法。如图1所示，在硅晶片51的表面形成有未图示的半导体集成电路(例如CCD图象传感器)。图1显示在后述的切割工序分割的预定的邻接芯片的分界的剖面。
介由BPSG等层间绝缘膜52，在该硅晶片51的表面形成一对焊盘电极53。该一对焊盘电极53由例如铝、铝合金、铜等金属层构成，其厚度为1um左右。一对焊盘电极53扩张至切割线区域DL，其扩张的端部被配置在切割线中心DS的近前。
然后，形成覆盖一对焊盘电极53的硅氮化膜等钝化膜54，进一步在该钝化膜54上涂敷由例如环氧树脂构成的树脂层55。介由该树脂层55将玻璃衬底56粘接到硅晶片51的表面。该玻璃衬底56作为硅晶片51的保护衬底或支承衬底起作用。在粘接了该玻璃衬底56的状态下，根据需要进行硅晶片51的背面蚀刻、所谓背面研磨，将其厚度加工为170um左右。
向背面研磨后的硅晶片51背面的整个面涂敷光致抗蚀剂，将其曝光及显影，从而选择性形成光致抗蚀剂层57。
然后，如图2所示，将该光致抗蚀剂层57作为掩膜，蚀刻硅晶片51的背面，形成硅凸部58。该蚀刻可采用使用自旋电蚀刻器等的湿蚀刻或干蚀刻。硅凸部58的高度h为35um左右，但其可通过调整蚀刻量进行任意地变更。
然后，如图3所示，在使用抗蚀剂剥离液除去光致抗蚀剂层57后，使用自旋电蚀刻器等将硅晶片51的背面湿蚀刻5um左右。由此，硅凸部58上边的角部形成圆形，可使后述的第一绝缘膜59的台阶覆盖性优良。
如图4所示，在硅晶片51的整个背面形成第一绝缘膜59。第一绝缘膜59为例如等离子CVD膜，PE-SiO2膜或PE-SiN膜是适用的。
然后，如图5所示，在第一绝缘膜59上选择性地形成光致抗蚀剂层60，以该光致抗蚀剂层60为掩膜，进行第一绝缘膜59及硅晶片51的蚀刻，形成贯通硅晶片51的通孔VH。在通孔VH的底部层间绝缘膜52露出，与其相接有焊盘电极53。通孔VH的宽度为40um左右，其长度为200um左右。
形成通孔VH的方法有使用激光束蚀刻的方法或使用干蚀刻的方法。为了使后述的种层62的包覆性优良，理想的是该通孔VH的断面形状通过激光束控制加工成顺锥形。
然后，如图6所示，在形成通孔VH的硅晶片51的背面整面形成第二绝缘膜61。第二绝缘膜61为例如等离子CVD膜，PE-SiO2膜或PE-SiN膜是适用的。第二绝缘膜61被形成于通孔VH的底部、侧壁及第一绝缘膜59上。
然后，如图7所示，当不使用光致抗蚀剂层进行各向异性的干蚀刻时，仅在通孔VH的侧壁保留第二绝缘膜61，其形成侧壁绝缘膜61A。由该蚀刻工序蚀刻除去通孔VH底部的第二绝缘膜61及层间绝缘膜52，使焊盘电极53露出。
另外，露出焊盘电极53的方法也可以是，在各向异性蚀刻层间绝缘膜52后，形成第二绝缘膜61，然后，各向异性蚀刻第二绝缘膜61，使焊盘电极53露出。这是为了良好地确保壁侧绝缘膜61A的分步涂敷。
其次，说明形成配线层64的工序。如图8所示，在利用溅射法或CVD法形成势垒层(例如TiN层)后，通过无电解镀敷法或CVD法整面形成由铜(Cu)构成的种层62。种层62形成在后述的电镀时用于镀膜成长的镀敷电极。其厚度为数百nm即可。另外，在将通孔VH加工成顺锥形时，种层62的形成可以使用溅射法。势垒层和上述相同，为防止Cu向硅的扩散而形成，其厚度为数十nm。
然后，进行铜(Cu)的电镀，但之前要在不形成镀敷的区域选择地形成光致抗蚀剂层63(图9)。该区域是除去配线层64及焊球形成区域外的区域。
如图10所示，通过进行铜(Cu)的电镀，并接着进行镍(Ni)、金(Au)的无电解镀敷，形成完全装入通孔VH内的配线层64。所述Ni、Au是势垒金属64a，也可以通过溅射法形成。配线层64自通孔VH向硅晶片的背面引出，并在该背面上延伸，覆盖硅凸部58。这样，配线层64介由种层62和焊盘电极53电连接。
该方法对工序消减有益，但由于不能独立控制配线层64的镀敷厚度和在通孔VH中成长的镀敷厚度，故有两者不能最优化的缺点。因此，通孔VH内的配线层64(也被称为柱状端子)通过电镀形成，其余部分的配线层64也可以通过Al溅射法或电镀法形成。
然后，参照图11，将光致抗蚀剂层63除去。然后，将配线层64作为掩膜，利用蚀刻除去残留于光致抗蚀剂层63下的种层62。此时，虽然配线层64也被蚀刻，但配线层64比种层62厚，因而没有问题。
然后，如图12所示，在配线层64上附着焊接掩膜65。将焊接掩膜65的硅凸部58上的部分除去，设置开口部K。
如图13所示，使用网印法在配线层64的规定区域上印刷焊锡，通过利用热处理使该焊锡回流，形成焊球66。配线层64可在硅晶片51背面的规定区域形成规定的条数，焊球66的数量或形成区域也可以自由地选择。
之后，如图14所示，沿切割线中心DS进行切割工序，将硅晶片51分割成多个硅芯片51A。在该切割工序中，可使用激光束。另外，在使用激光束的切割工序中，通过将玻璃衬底56的切断面加工成锥形，可防止玻璃衬底56的破裂。
其次，参照附图详细说明本发明的第二实施例。首先，说明该半导体装置的结构。图19是该半导体装置的剖面图，沿切割线将经过后述工序的硅晶片分割成一个个芯片。在图19中，DS是划线的中心。另外，在图19中，和第一实施例的图14相同的构成部分使用相同的符号，省略详细说明。
根据第一实施例，配线层64完全填埋通孔VH，与此相对，本实施例中配线层64A不完全地填埋在通孔VH内，这一点和第一实施例不同。即，配线层64虽然覆盖通孔VH的底部及侧壁，但由于其膜厚的2倍小于通孔VH的宽度，故其自身之间有缝隙。然后，焊接掩膜65的一部分埋入该缝隙。根据该结构，与配线层64A完全填埋通孔VH时相比，抵抗向印刷线路板等安装时产生的机械应力的抵抗力强。
其次，说明本实施例半导体装置的制造方法，自最初的工序至形成光致抗蚀剂层63的工序(图1～图9的工序)完全和第一实施例相同。
即，在形成光致抗蚀剂层63后，如图15所示，通过进行铜(Cu)电镀，然后进行镍(Ni)、金(Au)的无电解镀敷，形成不完全地填埋通孔VH的配线层64A。在该工序中，通过调整镀敷时间可在通孔VH内不完全地填埋配线层64。
然后，和第一实施例相同，如图16所示，除去光致抗蚀剂层63，将配线层64作为掩膜，利用蚀刻除去残留在光致抗蚀剂层63下的种层62。如图17所示，在配线层64A上附着焊接掩膜65。
然后，如图18所示，利用网印法在配线层64A的规定区域上印刷焊锡，通过由热处理使该焊锡回流，形成焊球66。
之后，如图19所示，沿切割线中心DS进行切割工序，将硅晶片51分割成多个硅芯片51A。
在所述的第一及第二实施例中，利用电镀将配线层64、64A填埋形成在通孔VH内，但不限于此，也可以采用其它的方法。例如，利用CVD法或MOCVD法向通孔VH内填埋铜(Cu)等金属的方法。
在所述的实施例中，在自通孔VH引出的配线层64、64A上形成焊球66，但不限于此，也可以在埋入通孔VH的配线层64、64A上形成焊球66。
在所述的实施例中，形成有将在通常的引线结合中使用的焊盘电极扩张至切割线区域DL而成的焊盘电极53，但不限于此，也可以取代焊盘电极53，仍然利用不扩张至切割线区域DL的通常的引线结合中使用的焊盘电极。此时，只要使通孔VH的形成位置与该焊盘电极匹配即可，其它工序完全相同。
根据本发明，可防止自半导体芯片的焊盘电极至其背面的导电端子的配线的断线或分步涂敷的劣化，可得到高可靠性的具有BGA的半导体装置。
另外，由于导电端子形成在设置于半导体芯片背面的半导体凸部上，故其形成于比半导体芯片背面高的位置。由此，容易吸收该半导体装置向印刷线路板进行安装时产生的应力，可最大限度地防止导电端子的损伤。

Claims (14)

1.一种半导体装置，其特征在于，包括：焊盘电极，其被设置于半导体芯片的第一主面上；半导体凸部，其被设置于所述半导体芯片的第二主面上；支承衬底，其被粘接于所述半导体芯片的第一主面上；配线层，其通过自所述半导体芯片的第二主面直至所述焊盘电极的表面而形成在所述半导体芯片上的通孔，与所述焊盘电极电连接，且自所述通孔在所述半导体芯片的第二主面上延伸，覆盖所述半导体凸部；导电端子，其形成在覆盖所述半导体凸部的配线层部分之上，与该配线层部分电连接。
2.如权利要求1所述的半导体装置，其特征在于，具有形成于所述通孔的侧壁，且将所述配线层和所述半导体芯片电绝缘的绝缘层。
3.如权利要求1所述的半导体装置，其特征在于，所述配线层完全填充所述通孔。
4.如权利要求1所述的半导体装置，其特征在于，所述配线层不完全地填充所述通孔。
5.一种半导体装置的制造方法，其包括：在半导体衬底的第一主面上形成焊盘电极的工序；在所述半导体衬底的第一主面上粘接支承衬底的工序；在所述半导体衬底的第二主面的规定区域形成光致抗蚀剂层的工序；通过以所述光致抗蚀剂层为掩膜，蚀刻所述半导体衬底，形成半导体凸部的工序；形成自所述半导体衬底的第二主面到达所述焊盘电极表面的通孔的工序；形成通过所述通孔和所述焊盘电极电连接，且自所述通孔起在所述半导体衬底的第二主面上延伸，覆盖所述半导体凸部的配线层的工序；在所述配线层上形成导电端子的工序；将所述半导体衬底分割成多个半导体芯片的工序。
6.如权利要求5所述的半导体装置的制造方法，其特征在于，形成所述配线层的工序利用电镀法或溅射法进行。
7.如权利要求5所述的半导体装置的制造方法，其特征在于，具有在所述通孔形成后，在该通孔的侧壁形成使所述配线层和所述半导体衬底电绝缘的侧壁绝缘膜的工序。
8.如权利要求5或6所述的半导体装置的制造方法，其特征在于，在形成所述配线层的工序中，使该配线层完全填充所述通孔。
9.如权利要求5或6所述的半导体装置的制造方法，其特征在于，在形成所述配线层的工序中，使该配线层不完全地填充所述通孔。
10.如权利要求5所述的半导体装置的制造方法，其特征在于，具有在形成所述半导体凸部后，将该半导体凸部的角形成园角的工序。
11.一种半导体装置的制造方法，其包括：在半导体衬底的第一主面上形成焊盘电极的工序；在所述半导体衬底的第一主面上粘接支承衬底的工序；在所述半导体衬底的第二主面的规定区域形成光致抗蚀剂层的工序；通过以所述光致抗蚀剂层为掩膜蚀刻所述半导体衬底，形成半导体凸部的工序；在除去所述光致抗蚀剂层后，在所述半导体衬底的第二主面上形成绝缘膜的工序；形成自所述半导体衬底的第二主面到达所述焊盘电极表面的通孔的工序；在所述通孔壁侧形成侧壁绝缘膜的工序；在所述通孔内形成种层的工序；利用电镀，形成通过所述通孔和所述焊盘电极电连接，且自所述通孔起在所述半导体芯片的第二主面上延伸，覆盖所述半导体凸部的配线层的工序；在所述配线层上形成导电端子的工序；将所述半导体衬底分割成多个半导体芯片的工序。
12.如权利要求11所述的半导体装置的制造方法，其特征在于，在形成所述配线层的工序中，使该配线层完全填埋所述通孔。
13.如权利要求11所述的半导体装置的制造方法，其特征在于，在形成所述配线层的工序中，使该配线层不完全填埋所述通孔。
14.如权利要求11所述的半导体装置的制造方法，其特征在于，具有在形成所述半导体凸部后，将该半导体凸部的角形成园角的工序。
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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4130158B2 (ja) 2003-06-09 2008-08-06 三洋電機株式会社 半導体装置の製造方法、半導体装置
DE10356885B4 (de) 2003-12-03 2005-11-03 Schott Ag Verfahren zum Gehäusen von Bauelementen und gehäustes Bauelement
JP2006093367A (ja) 2004-09-24 2006-04-06 Sanyo Electric Co Ltd 半導体装置の製造方法
JP4708009B2 (ja) * 2004-12-14 2011-06-22 株式会社フジクラ 配線基板の製造方法
JP2007036060A (ja) * 2005-07-28 2007-02-08 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4745007B2 (ja) * 2005-09-29 2011-08-10 三洋電機株式会社 半導体装置及びその製造方法
JP2007311771A (ja) * 2006-04-21 2007-11-29 Sanyo Electric Co Ltd 半導体装置及びその製造方法
KR100828027B1 (ko) * 2006-06-28 2008-05-08 삼성전자주식회사 스택형 웨이퍼 레벨 패키지 및 그의 제조 방법, 및 웨이퍼레벨 스택 패키지 및 그의 제조 방법
US9034729B2 (en) * 2006-08-25 2015-05-19 Semiconductor Components Industries, Llc Semiconductor device and method of manufacturing the same
US8653612B2 (en) * 2006-08-25 2014-02-18 Sanyo Semiconductor Co., Ltd. Semiconductor device
US8212331B1 (en) * 2006-10-02 2012-07-03 Newport Fab, Llc Method for fabricating a backside through-wafer via in a processed wafer and related structure
KR100843240B1 (ko) * 2007-03-23 2008-07-03 삼성전자주식회사 웨이퍼 레벨 스택을 위한 반도체 소자 및 웨이퍼 레벨스택을 위한 반도체 소자의 관통전극 형성방법
US7923645B1 (en) * 2007-06-20 2011-04-12 Amkor Technology, Inc. Metal etch stop fabrication method and structure
US8784636B2 (en) 2007-12-04 2014-07-22 Ebara Corporation Plating apparatus and plating method
JP5281831B2 (ja) * 2008-06-30 2013-09-04 株式会社荏原製作所 導電材料構造体の形成方法
WO2011111308A1 (ja) * 2010-03-09 2011-09-15 パナソニック株式会社 半導体装置の製造方法及び半導体装置
US9293678B2 (en) 2010-07-15 2016-03-22 Micron Technology, Inc. Solid-state light emitters having substrates with thermal and electrical conductivity enhancements and method of manufacture
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
US20130313710A1 (en) * 2012-05-22 2013-11-28 Micron Technology, Inc. Semiconductor Constructions and Methods of Forming Semiconductor Constructions
US20140151095A1 (en) * 2012-12-05 2014-06-05 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method for manufacturing the same
JP6359444B2 (ja) * 2014-12-25 2018-07-18 東京エレクトロン株式会社 配線層形成方法、配線層形成システムおよび記憶媒体
US10204886B2 (en) * 2016-01-29 2019-02-12 Mitsubishi Electric Corporation Semiconductor device
TWI623049B (zh) * 2016-11-04 2018-05-01 英屬開曼群島商鳳凰先驅股份有限公司 封裝基板及其製作方法
JP6963396B2 (ja) * 2017-02-28 2021-11-10 キヤノン株式会社 電子部品の製造方法
KR102420586B1 (ko) 2017-07-24 2022-07-13 삼성전자주식회사 반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법
JP2019160893A (ja) * 2018-03-09 2019-09-19 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、半導体装置、電子機器、および製造方法
JP7279306B2 (ja) * 2018-06-28 2023-05-23 凸版印刷株式会社 配線基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1295344A (zh) * 1999-11-04 2001-05-16 日本电气株式会社 由树脂制成应力吸收层的倒装片型半导体器件及制造方法
US6350633B1 (en) * 2000-08-22 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US6426562B2 (en) * 1996-03-07 2002-07-30 Micron Technology, Inc. Mask repattern process

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761782A (en) * 1971-05-19 1973-09-25 Signetics Corp Semiconductor structure, assembly and method
JPH0321859A (ja) 1989-06-20 1991-01-30 Nippondenso Co Ltd 酸素センサー
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
DE4312976A1 (de) * 1993-04-21 1994-10-27 Bosch Gmbh Robert Kontaktierung von elektrisch leitenden Schichten eines Schichtsystems
US6124179A (en) * 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US5684331A (en) * 1995-06-07 1997-11-04 Lg Semicon Co., Ltd. Multilayered interconnection of semiconductor device
US5946555A (en) * 1996-11-04 1999-08-31 Packard Hughes Interconnect Company Wafer level decal for minimal packaging of chips
US5904496A (en) 1997-01-24 1999-05-18 Chipscale, Inc. Wafer fabrication of inside-wrapped contacts for electronic devices
IL120514A (en) * 1997-03-25 2000-08-31 P C B Ltd Electronic interconnect structure and method for manufacturing it
JPH10303327A (ja) * 1997-04-23 1998-11-13 Yamaichi Electron Co Ltd 半導体チップの接点変換構造と該接点変換構造を有する半導体チップの製造法
US6586829B1 (en) * 1997-12-18 2003-07-01 Si Diamond Technology, Inc. Ball grid array package
IL123207A0 (en) 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
US6114221A (en) * 1998-03-16 2000-09-05 International Business Machines Corporation Method and apparatus for interconnecting multiple circuit chips
US6303988B1 (en) * 1998-04-22 2001-10-16 Packard Hughes Interconnect Company Wafer scale burn-in socket
KR100266698B1 (ko) * 1998-06-12 2000-09-15 김영환 반도체 칩 패키지 및 그 제조방법
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6263566B1 (en) * 1999-05-03 2001-07-24 Micron Technology, Inc. Flexible semiconductor interconnect fabricated by backslide thinning
JP3879816B2 (ja) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
JP2002094082A (ja) * 2000-07-11 2002-03-29 Seiko Epson Corp 光素子及びその製造方法並びに電子機器
US6693358B2 (en) * 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
US6444489B1 (en) 2000-12-15 2002-09-03 Charles W. C. Lin Semiconductor chip assembly with bumped molded substrate
US6433427B1 (en) * 2001-01-16 2002-08-13 Industrial Technology Research Institute Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication
JP4053257B2 (ja) 2001-06-14 2008-02-27 新光電気工業株式会社 半導体装置の製造方法
JP2002373957A (ja) 2001-06-14 2002-12-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4000507B2 (ja) 2001-10-04 2007-10-31 ソニー株式会社 固体撮像装置の製造方法
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426562B2 (en) * 1996-03-07 2002-07-30 Micron Technology, Inc. Mask repattern process
CN1295344A (zh) * 1999-11-04 2001-05-16 日本电气株式会社 由树脂制成应力吸收层的倒装片型半导体器件及制造方法
US6350633B1 (en) * 2000-08-22 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint

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