TWI564978B - 改善冠狀缺陷之線路結構及其製作方法 - Google Patents

改善冠狀缺陷之線路結構及其製作方法 Download PDF

Info

Publication number
TWI564978B
TWI564978B TW100142385A TW100142385A TWI564978B TW I564978 B TWI564978 B TW I564978B TW 100142385 A TW100142385 A TW 100142385A TW 100142385 A TW100142385 A TW 100142385A TW I564978 B TWI564978 B TW I564978B
Authority
TW
Taiwan
Prior art keywords
layer
copper
barrier layer
barrier
oxidation
Prior art date
Application number
TW100142385A
Other languages
English (en)
Other versions
TW201222692A (en
Inventor
張義民
林義閔
林柏伸
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201222692A publication Critical patent/TW201222692A/zh
Application granted granted Critical
Publication of TWI564978B publication Critical patent/TWI564978B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02317—Manufacturing methods of the redistribution layers by local deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02319—Manufacturing methods of the redistribution layers by using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Description

改善冠狀缺陷之線路結構及其製作方法
本發明是有關於一種線路結構及其製作方法，且特別是有關於一種改善冠狀缺陷之線路結構及其製作方法。
銅導線隨著線寬越來越窄，使得微影及蝕刻的製程的困難度增加，因而容易發生對位失準或過渡蝕刻的現象，造成晶片的產能下降及線路出現冠狀缺陷(crown-like defect)的問題。出現冠狀缺陷的原因之一是裸露的銅導線與線路表面的鍍金層同時接觸到蝕刻液時，由於銅與金的氧化電位不同，而使銅導線產生伽凡尼反應(Galvanic reaction)。也就是說，不同氧化電位的金屬同時在蝕刻液中，會因電位差而產生電化學反應。氧化電位高的金屬(例如銅)形成陽極，而氧化電位低的金屬(例如金)形成陰極。氧化電位高的銅金屬在電化學反應中，會形成銅離子而溶解在蝕刻液中，因此銅導線的底部快速地被腐蝕而出現冠狀缺陷。此外，蝕刻液中的銅離子得到電子之後還原而沈積在氧化電位低的金屬上，造成鍍金層的顏色變深。上述之線路蝕刻製程有待進一步解決。
本發明係有關於一種改善冠狀缺陷之線路結構及其製作方法，用以避免發生伽凡尼反應及抗氧化層變色的情形。
根據本發明之一方面，提出一種改善冠狀缺陷之線路結構，包括一基材、一電鍍種子層、一銅層、一阻障層以及一抗氧化層。電鍍種子層形成於基材上。銅層形成於電鍍種子層上，銅層及部分電鍍種子層經蝕刻而形成一線路層。阻障層至少覆蓋銅層之一頂部，阻障層的氧化電位大於銅層的氧化電位。抗氧化層全面性覆蓋阻障層以及線路層所顯露的表面上。
根據本發明之另一方面，提出一種改善冠狀缺陷之線路製作方法，包括下列步驟：提供一基材，基材上形成有一電鍍種子層以及一圖案化光阻層，圖案化光阻層具有一開口。形成一銅層於開口中，銅層的底部覆蓋於電鍍種子層上。形成一阻障層於銅層上，阻障層至少覆蓋銅層的一頂部，其中阻障層的氧化電位大於銅層的氧化電位。移除圖案化光阻層，以進行一蝕刻製程，其中裸露的銅層及部分電鍍種子層經蝕刻而形成一線路層。進行一浸漬製程，以全面性形成一抗氧化層於阻障層以及線路層所顯露的表面上。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
請參考第1及2圖，其中第1圖繪示依照一實施例之改善冠狀缺陷之線路結構的剖面示意圖，第2圖繪示依照一實施例之改善冠狀缺陷之線路製作方法的流程圖。上述之線路結構100包括一基材110、一電鍍種子層120、一銅層130、一阻障層140以及一抗氧化層150。銅層130形成於電鍍種子層120上。銅層130及部分電鍍種子層120經蝕刻而形成一線路層132。阻障層140至少覆蓋銅層130之一頂部131。阻障層140的氧化電位大於該銅層130的氧化電位。抗氧化層150全面性覆蓋阻障層140以及線路層132所顯露的表面上。
請參考第1及2圖，上述之線路製作方法包括步驟S110～S160，其中步驟S110為電鍍，用以形成預定厚度的銅層130於電鍍種子層120上以及形成阻障層140於銅層130之頂部131上。步驟S120為去光阻(PR striping)，用以去除覆蓋於電鍍種子層120上的圖案化光阻層。步驟S130為蝕刻(etching)，例如是濕式蝕刻，用以蝕刻銅層130及部分電鍍種子層120，以形成一具有預定線寬的線路層132。步驟S140為浸漬(immersion)，用以將抗氧化層150全面性覆蓋阻障層140以及線路層132所顯露的表面上。
此外，請參考第2及3圖，其中第3圖繪示依照一實施例之改善冠狀缺陷之線路結構的剖面示意圖。在步驟S150中，更可形成一防銲層160(solder mask layer)於基材110上，防銲層160至少覆蓋形成有抗氧化層150之線路層132及阻障層140的側壁。另外，在步驟S160中，更可形成一銲料凸塊170於形成有抗氧化層150之阻障層140之一上表面141。銲料凸塊170之材質例如是錫鉛凸塊或錫、銀、銅等金屬所組成之無鉛凸塊。
在一實施例中，阻障層140的材質例如為鎳或氧化電位大於銅的金屬，電鍍種子層120的材質例如為銅。在步驟S130的蝕刻製程中，當裸露的電鍍種子層120、銅層130接觸到蝕刻液，裸露的電鍍種子層120及銅層130因蝕刻液的電化學反應，形成銅離子而溶解在蝕刻液中，以形成線路層132。蝕刻液可使用氯化銅與鹽酸的溶液、氯化鐵溶液、硫酸與過氧化氫之溶液、過硫酸銨溶液等化學蝕刻液。此外，由於阻障層140對於銅蝕刻液不會產生電化學反應，因此銅層130的頂部131受到阻障層140的保護。另外，由於阻障層140的氧化電位大於銅的氧化電位，阻障層140形成氧化反應的陽極，而銅層130形成還原反應的陰極，使得銅層130不容易發生伽凡尼反應而被腐蝕，因此可抑止銅層130的底部快速地被腐蝕而出現冠狀缺陷的情形。
請參考第2及4A～4E圖，其中第4A～4E圖繪示依照一實施例之改善冠狀缺陷之線路製作方法的流程圖。根據第2圖之製程順序，線路製作方法包括下列步驟：(1)在第4A圖中，提供一基材110，基材110上形成有一電鍍種子層120以及一圖案化光阻層112，圖案化光阻層112具有一開口112a；(2)在第4B圖中，形成一銅層130於開口112a中，銅層130的底部覆蓋於電鍍種子層120上，且形成一阻障層140於銅層130上，阻障層140至少覆蓋銅層130的一頂部131，其中阻障層140的氧化電位大於銅層130的氧化電位；(3)在第4C圖中，移除圖案化光阻層112，以進行一蝕刻製程，其中銅層130及部分電鍍種子層120經蝕刻而形成一線路層132；(4)在第4D圖中，進行一浸漬(immersion)製程，以全面性形成一抗氧化層150於阻障層140以及線路層132所顯露的表面上。
請參考第4A圖，基材110110例如為矽、砷化鎵等半導體材料或其他電路板，其內佈設有適當的電路，可做為積體電路晶片、發光二極體晶片、光感測晶片或印刷電路板之基材110。接著，形成一電鍍種子層120於基材110上。電鍍種子層120之材質例如為銅，其以濺鍍或無電電鍍的方式形成在基材110上。接著，形成一圖案化光阻層112於電鍍種子層120上。圖案化光阻層112例如先以旋塗、壓膜或印刷的方式形成在電鍍種子層120上，再以曝光、顯影等圖案化製程去除部分光阻，以形成一預定尺寸的開口112a。
接著，請參考第4B圖，形成一銅層130於開口112a中。銅層130例如以硫酸銅電鍍液中的銅離子經過還原反應而沈積在開口112a中的電鍍種子層120上，以形成一線路圖案。接著，形成一阻障層140於銅層130上，阻障層140例如以電鍍或無電電鍍的方式形成在銅層130的頂部131。在一實施例中，阻障層140例如為鎳，可降低銅導線表面氧化，並可與銅導線形成銅鎳合金層，以改善銅導線之電致遷移(migration)的影響。
接著，請參考第4C圖，移除圖案化光阻層112，以進行一蝕刻製程。如上所述，當裸露的電鍍種子層120、銅層130與阻障層140同時接觸到蝕刻液時，裸露的電鍍種子層120及銅層130因蝕刻液的電化學反應，形成銅離子而溶解在蝕刻液中。電鍍種子層120被蝕刻而形成寬度與銅層130的寬度幾乎一致的底金屬層122，其與上方的銅層130共同形成具有一預定線寬的線路層132。
此外，進行蝕刻製程時，由於阻障層140的氧化電位大於銅的氧化電位，阻障層140形成氧化反應的陽極，而銅層130形成還原反應的陰極，使得銅層130不容易發生伽凡尼反應而被腐蝕，因此可抑止銅層130的底部快速地被腐蝕而出現冠狀缺陷的情形。
接著，請參考第4D圖，進行一浸漬製程，以形成一抗氧化層150。抗氧化層150之材質例如是金，其藉由電敷液中金屬離子產生靜電吸附或離子交換，並吸收還原劑所提供的電子，而全面性地分佈在阻障層140以及線路層132所顯露的表面上。在一實施例中，由於無電鍍之浸漬沈積所產生的抗氧化層150具有自催化特性，不論欲鍍表面的幾何形狀為何，其鍍膜的厚度可近乎一致，且可鍍到阻障層140暴露之下表面及向內凹陷之線路層132的側表面。因此，抗氧化層150可避免阻障層140之下表面及線路層132的側表面產生氧化或鈍化，如第1圖所示之區域A。
此外，由於抗氧化層150(鍍金層)係在蝕刻製程之後形成的，因此在蝕刻裸露的電鍍種子層120及銅層130時，不會發生習知氧化電位高於金的銅金屬因伽凡尼反應溶解在蝕刻液中，導致銅導線的底部被腐蝕而出現冠狀缺陷。另外，習知蝕刻液中的銅離子得到電子之後還原而沈積在鍍金層上，造成鍍金層的顏色變深的情形亦不會發生。
接著，請參考第4E圖，基材110上更可形成一防銲層160。防銲層160至少覆蓋形成有抗氧化之線路層132及阻障層140的側壁。另外，一銲料凸塊170更可形成於形成有抗氧化層150之阻障層140之一上表面。銲料凸塊170之材質例如是錫鉛凸塊或錫、銀、銅等金屬所組成之無鉛凸塊。
本發明上述實施例所揭露之改善冠狀缺陷之線路結構及其製作方法，係利用阻障層的氧化電位大於銅層的氧化電位的特性，避免銅層發生伽凡尼反應而被腐蝕，因此可抑止銅層的底部快速地被腐蝕而出現冠狀缺陷的情形。此外，抗氧化層係在蝕刻製程之後形成的，因此不會發生抗氧化層變色的問題，以提高線路抗氧化變色的能力。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．線路結構
110．．．基材
112．．．圖案化光阻層
112a．．．開口
120．．．電鍍種子層
122．．．底金屬層
130．．．銅層
131．．．頂部
132．．．線路層
140．．．阻障層
141．．．上表面
150．．．抗氧化層
160．．．防銲層
170．．．銲料凸塊
A．．．區域
第1圖繪示依照一實施例之改善冠狀缺陷之線路結構的剖面示意圖。
第2圖繪示依照一實施例之改善冠狀缺陷之線路製作方法的流程圖。
第3圖繪示依照一實施例之改善冠狀缺陷之線路結構的剖面示意圖。
第4A～4E圖繪示依照一實施例之改善冠狀缺陷之線路製作方法的流程圖
S110~S160．．．各個步驟

Claims (11)

  1. 一種改善冠狀缺陷之線路製作方法，包括：提供一基材，該基材上形成有一電鍍種子層以及一圖案化光阻層，該圖案化光阻層具有一開口；形成一銅層於該開口中，該銅層的底部覆蓋於該電鍍種子層上；形成一阻障層於該銅層上，該阻障層至少覆蓋該銅層的一頂部，其中該阻障層的氧化電位大於該銅層的氧化電位；移除該圖案化光阻層，以進行一蝕刻製程，其中裸露的該銅層及部分該電鍍種子層經蝕刻而形成一線路層，該阻障層的部分下表面顯露於該銅層的該頂部之外；以及進行一浸漬製程，以全面性形成一抗氧化層於該阻障層以及該線路層所顯露的表面上，其中該表面包括該阻障層的該部分下表面。
  2. 如申請專利範圍第1項所述之製作方法，更包括形成一防銲層於該基材上，該防銲層至少覆蓋於形成有該抗氧化之該線路層及該阻障層的側壁。
  3. 如申請專利範圍第1項所述之製作方法，更包括形成一銲料凸塊於覆蓋有該抗氧化層之該阻障層之一上表面。
  4. 如申請專利範圍第1項所述之製作方法，其中該銲料凸塊之材質係選自由錫、銀、銅、金或其組合所組成的群組。
  5. 如申請專利範圍第1項所述之製作方法，其中該 阻障層之材質係為鎳。
  6. 如申請專利範圍第1項所述之製作方法，其中該抗氧化層之材質係為金。
  7. 一種改善冠狀缺陷的線路結構，包括：一基材；一電鍍種子層，形成於該基材上；一銅層，形成於該電鍍種子層上，該銅層及部分該電鍍種子層經蝕刻而形成一線路層；一阻障層，至少覆蓋該銅層之一頂部，且該阻障層的部分下表面顯露於該銅層的該頂部之外，該阻障層的氧化電位大於該銅層的氧化電位；以及一抗氧化層，全面性覆蓋該阻障層以及該線路層所顯露的表面上，其中該表面包括該阻障層的該部分下表面，該抗氧化層為一膜層，以浸漬金的方式形成。
  8. 如申請專利範圍第7項所述之結構，更包括一防銲層，形成於該基材上，該防銲層至少覆蓋形成有該抗氧化之該線路層及該阻障層的側壁。
  9. 如申請專利範圍第7項所述之結構，更包括一銲料凸塊，形成於覆蓋有該抗氧化層之該阻障層之一上表面。
  10. 如申請專利範圍第9項所述之結構，其中該銲料凸塊之材質係選自由錫、銀、銅、金或其組合所組成的群組。
  11. 如申請專利範圍第7項所述之結構，其中該阻障層之材質係為鎳。
TW100142385A 2010-11-18 2011-11-18 改善冠狀缺陷之線路結構及其製作方法 TWI564978B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US41507910P 2010-11-18 2010-11-18

Publications (2)

Publication Number Publication Date
TW201222692A TW201222692A (en) 2012-06-01
TWI564978B true TWI564978B (zh) 2017-01-01

Family

ID=46063264

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100142385A TWI564978B (zh) 2010-11-18 2011-11-18 改善冠狀缺陷之線路結構及其製作方法

Country Status (3)

Country Link
US (2) US8760882B2 (zh)
CN (1) CN102569171B (zh)
TW (1) TWI564978B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102040605B1 (ko) 2015-07-15 2019-12-05 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
KR102326505B1 (ko) * 2015-08-19 2021-11-16 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
DE102016103585B4 (de) * 2016-02-29 2022-01-13 Infineon Technologies Ag Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt
US10057985B2 (en) * 2016-06-10 2018-08-21 Denso Corporation Printed substrate and electronic device
US10593638B2 (en) * 2017-03-29 2020-03-17 Xilinx, Inc. Methods of interconnect for high density 2.5D and 3D integration
WO2018230534A1 (ja) * 2017-06-16 2018-12-20 株式会社村田製作所 回路基板および回路モジュール、ならびに回路基板の製造方法および回路モジュールの製造方法
TWI669994B (zh) * 2017-12-04 2019-08-21 希華晶體科技股份有限公司 Method for manufacturing miniaturized circuit and its products
US11127688B2 (en) * 2019-08-22 2021-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
CN112928438B (zh) * 2019-11-20 2023-10-20 华为技术有限公司 盖板及电子设备
CN110854066A (zh) * 2019-11-28 2020-02-28 无锡微视传感科技有限公司 一种半导体电镀方法
TWI797049B (zh) * 2022-09-21 2023-03-21 頎邦科技股份有限公司 軟性電路基板之線路結構

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW558821B (en) * 2002-05-29 2003-10-21 Via Tech Inc Under bump buffer metallurgy structure
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface
US20050003649A1 (en) * 2003-06-09 2005-01-06 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US20060214296A1 (en) * 2005-03-28 2006-09-28 Fujitsu Limited Semiconductor device and semiconductor-device manufacturing method
TW200847368A (en) * 2007-03-23 2008-12-01 Renesas Tech Corp Interposer substrate, LSI chip and information terminal device using the interposer substrate, interposer substrate manufacturing method, and LSI chip manufacturing method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
US6727593B2 (en) * 2001-03-01 2004-04-27 Kabushiki Kaisha Toshiba Semiconductor device with improved bonding
DE10158809B4 (de) * 2001-11-30 2006-08-31 Infineon Technologies Ag Herstellungsverfahren für eine Leiterbahn auf einem Substrat und eine entsprechende Leiterbahn
TWI240977B (en) * 2004-07-23 2005-10-01 Advanced Semiconductor Eng Structure and formation method for conductive bump

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW558821B (en) * 2002-05-29 2003-10-21 Via Tech Inc Under bump buffer metallurgy structure
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface
US20050003649A1 (en) * 2003-06-09 2005-01-06 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US20060214296A1 (en) * 2005-03-28 2006-09-28 Fujitsu Limited Semiconductor device and semiconductor-device manufacturing method
TW200847368A (en) * 2007-03-23 2008-12-01 Renesas Tech Corp Interposer substrate, LSI chip and information terminal device using the interposer substrate, interposer substrate manufacturing method, and LSI chip manufacturing method

Also Published As

Publication number Publication date
US8760882B2 (en) 2014-06-24
US9426894B2 (en) 2016-08-23
US20120125668A1 (en) 2012-05-24
TW201222692A (en) 2012-06-01
CN102569171A (zh) 2012-07-11
CN102569171B (zh) 2015-02-04
US20140251946A1 (en) 2014-09-11

Similar Documents

Publication Publication Date Title
TWI564978B (zh) 改善冠狀缺陷之線路結構及其製作方法
US9391036B2 (en) Semiconductor device and manufacturing method thereof
TWI395531B (zh) 印刷配線基板、其製造方法以及半導體裝置
WO2010052973A1 (ja) 半導体装置及びその製造方法
KR20060048174A (ko) 극세선 패턴을 갖는 배선 기판의 제조 방법 및 배선 기판
JP2010093284A (ja) 半導体装置の製造方法
JP4493516B2 (ja) 半導体装置の製造方法
JP4695675B2 (ja) プリント配線基板の製造方法
TWI512847B (zh) 製造半導體元件和結構的方法
JP6015239B2 (ja) 端子構造、並びにこれを備える半導体素子及びモジュール基板
TWI425889B (zh) 線路結構及其製作方法
JP5675521B2 (ja) タブテープおよびその製造方法
JP2011166028A (ja) Ｃｏｆ基板の製造方法
US9041166B2 (en) Manufacturing method of circuit structure
JPH09199505A (ja) 半導体装置およびその製造方法
JP5169894B2 (ja) 半導体装置用テープキャリアおよびその製造方法
US8431029B2 (en) Circuit board and method of manufacturing the same
KR20160016479A (ko) 포토레지스트 박리 방법
JP2006120803A (ja) 半導体装置及び半導体装置の製造方法
JP2005129665A (ja) 半導体装置およびその製造方法
JP2000049181A (ja) 半導体装置および半導体装置の製造方法
JP4730262B2 (ja) 半導体装置用ノンリードタイプのリードフレームの製造方法
JP4157693B2 (ja) 半導体装置及びその製造方法
JP2007201216A (ja) フレキシブル配線基板およびその製造方法
JP2009253236A (ja) 積層半導体回路基板およびそれを用いた積層半導体装置の製造方法