TWI459485B - 晶片封裝體的形成方法 - Google Patents

晶片封裝體的形成方法 Download PDF

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TWI459485B
TWI459485B TW101101926A TW101101926A TWI459485B TW I459485 B TWI459485 B TW I459485B TW 101101926 A TW101101926 A TW 101101926A TW 101101926 A TW101101926 A TW 101101926A TW I459485 B TWI459485 B TW I459485B
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substrate
layer
chip package
forming
holes
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TW201232684A (en
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Chien Hui Chen
Ming Kun Yang
Tsang Yu Liu
Yen Shih Ho
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Xintec Inc
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Description

晶片封裝體的形成方法
本發明係有關於晶片封裝體，且特別是有關於具穿基底導電結構之晶片封裝體。
晶片封裝製程是形成電子產品過程中之一重要步驟。晶片封裝體除了將晶片保護於其中，使免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
隨著晶片尺寸的縮小化與內部線路密度的提升，晶片封裝體的尺寸與導線密度亦需隨之調整。於有限空間之內形成所需的導電通路，且兼顧所形成導電通路之品質已成為重要課題。
本發明一實施例提供一種晶片封裝體的形成方法，包括：提供一基底，具有一第一表面及一第二表面，其中至少二個導電墊設置於基底之第一表面上；自該基底之該第二表面部分移除該基底以形成朝該第一表面延伸之至少二個孔洞，其中該些孔洞分別對齊於其中一對應的該些導電墊；在形成該些孔洞之後，自該基底之該第二表面部分移除該基底以形成朝該第一表面延伸之至少一凹陷，該凹陷與該些孔洞重疊；於該凹陷之側壁與底部上及該孔洞之側壁上形成一絕緣層；以及於該絕緣層上形成一導電層，該導電層電性接觸其中一該些導電墊。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間必然具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝各種晶片。例如，其可用於封裝各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package;WSP)製程對影像感測元件、發光二極體(light-emitting diodes;LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率晶片(power IC)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
第1A-1L圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第1A圖所示，提供基底100，具有表面100a及表面100b。基底100可為半導體基底，例如是半導體晶圓。基底100上可形成有至少一元件區(未顯示)。元件區可與基底100之表面100a上之導電墊104電性連接。導電墊104可形成於表面100a上之介電層102之上或之中。在一實施例中，導電墊104可為多層導電墊之疊層。
如第1A圖所示，為了於基底100中定義凹陷，可於基底100之表面100b上形成圖案化遮罩層105，其具有露出部分基底100之開口。開口可與下方之至少兩導電接墊104重疊。
接著，如第1B圖所示，可例如以蝕刻製程自基底100之表面100b移除未由遮罩層105所覆蓋之部分，因而形成出自基底100之表面100b朝表面100a延伸之凹陷106。接著，移除遮罩層105。
如第1C圖所示，為了於基底100之凹陷106的底部定義孔洞，可於基底100之表面100b上形成圖案化遮罩層107，其具有露出部分基底100之至少兩開口。這些開口可分別大抵對齊於其下之對應的導電接墊104。
接著，如第1D圖所示，可例如以蝕刻製程自凹陷106之底部移除未由遮罩層107所覆蓋之部分，因而形成出自基底100之表面100b朝表面100a延伸之孔洞108。在一實施例中，孔洞108露出介電層102。在一實施例中，孔洞108大抵對齊於下方之對應的導電墊104。
如第1E圖所示，接著可例如以蝕刻製程移除孔洞108下方之介電層102以使對應的導電墊104露出。在一實施例中，移除介電層102之蝕刻製程所採用的蝕刻劑可大抵不會蝕刻移除或僅會微量蝕刻移除導電墊104。接著，可移除遮罩層107。
接著，如第1F圖所示，於凹陷106之側壁與底部及孔洞108之側壁上形成絕緣層110。例如，可以化學氣相沉積製程於基底100之表面100b上形成順應性的絕緣層110。在此實施例中，由基底100之表面100b朝表面100b延伸之穿孔係由凹陷106與孔洞108所共同形成，因此穿孔之深寬比較小，有利於絕緣層110之沉積。在一實施例中，絕緣層110會覆蓋導電墊104。在此情形下，可進一步透過圖案化製程移除孔洞108底部上之絕緣層110而使導電墊104露出。
如第1G圖所示，可例如以物理氣相沉積製程於基底100之表面100b上形成晶種層112。在此實施例中，由基底100之表面100b朝表面100b延伸之穿孔係由凹陷106與孔洞108所共同形成，因此穿孔之深寬比較小，有利於晶種層112之沉積。晶種層112可延伸至凹陷106之側壁與底部，並進一步延伸至孔洞108之側壁與底部上而與導電墊104電性接觸。接著，可於晶種層112上形成遮罩層113。
接著，如第1H圖所示，可透過電鍍製程及/或無電鍍製程於未由遮罩層113所覆蓋之晶種層112上沉積導電材料而形成出厚度較厚之導電層112a。接著，移除遮罩層113而露出下方之晶種層。
如第1I圖所示，可例如以蝕刻製程移除原由遮罩層113所覆蓋之晶種層而使導電層112a具有所需之圖案。導電層112a在移除原由遮罩層113所覆蓋之晶種層的蝕刻製程中亦會被些微移除。接著，可以化學鍍鎳或化學鍍金之方法於導電層112a之表面上沉積導電材料層以形成厚度較厚之圖案化導電層112b，其中化學鍍鎳或化學鍍金製程可增加導電層之可靠度與提升與後續材料層之接合。應注意的是，上述與導電層有關之製程僅舉例說明，圖案化導電層112b之形成方式不限於上述製程。
接著，如第1J圖所示，於基底100之表面100b上形成圖案化保護層114。保護層114具有至少一開口，露出下方之導電層112b。在一實施例中，保護層114延伸進入凹陷106之中。在一實施例中，保護層114延伸進入孔洞108之中。在一實施例中，位於凹陷106中之保護層114具有一溝槽，其位置大抵與基底100之預定切割道SC重疊。
如第1K圖所示，於保護層114露出導電層112b之開口中形成導電凸塊116。
接著，如第1L圖所示，沿著基底100之預定切割道SC切割基底100以形成至少一獨立的晶片封裝體10。由於保護層114於切割道處具有溝槽，因此切割過程中不會切割保護層114，可提升晶片封裝體之品質。在此情形下，保護層114之一側壁與基底100之一側壁不共平面。
在上述實施例中，穿孔之形成過程係先形成凹陷，隨後形成孔洞。然而，本發明實施例不限於此。例如，第2A-2H圖顯示根據本發明另一實施例之晶片封裝體的製程剖面圖，其中相同或相似之標號用以標示相同或相似之元件。
如第2A圖所示，提供基底100，具有表面100a及表面100b。基底100可為半導體基底，例如是半導體晶圓。基底100上可形成有至少一元件區(未顯示)。元件區可與基底100之表面100a上之導電墊104電性連接。導電墊104可形成於表面100a上之介電層102之上或之中。在一實施例中，導電墊104可為多層導電墊之疊層。
如第2A圖所示，為了於基底100中定義孔洞，可於基底100之表面100b上形成圖案化遮罩層103，其具有露出部分基底100之至少兩開口。開口可大抵分別對齊於下方之對應的兩導電接墊104。
接著，如第2B圖所示，可例如以蝕刻製程自基底100之表面100b移除未由遮罩層103所覆蓋之部分，因而形成出自基底100之表面100b朝表面100a延伸之孔洞108。接著，移除遮罩層103。在一實施例中，孔洞108露出介電層102。在一實施例中，孔洞108大抵對齊於下方之對應的導電墊104。
如第2C圖所示，為了於基底100之表面100b定義凹陷，可於基底100之表面100b上形成圖案化遮罩層107，其具有露出部分基底100之至少一開口。開口可與下方之至少兩導電接墊104重疊。
接著，如第2D圖所示，可例如以蝕刻製程自基底100之表面100b移除未由遮罩層107所覆蓋之部分，因而形成出自基底100之表面100b朝表面100a延伸之凹陷106。在形成凹陷106的過程中，孔洞108之側壁亦可能會受到影響。例如，在一實施例中，孔洞108之側壁相對於表面100b之傾斜程度會增加。如第2C-2D圖所示，孔洞108之側壁與表面100b之間的夾角由θ1增加到θ2。
如第2E圖所示，接著可以化學氣相沉積製程於基底100之表面100b上形成順應性的絕緣層110。在此實施例中，由基底100之表面100b朝表面100b延伸之穿孔係由凹陷106與孔洞108所共同形成，因此穿孔之深寬比較小，有利於絕緣層110之沉積。在一實施例中，絕緣層110會覆蓋下方之介電層102及導電墊104。
接著，如第2F圖所示，於基底100之表面100b上設置遮罩層111。遮罩層111具有露出孔洞108之底部處的絕緣層110之開口。接著，可以遮罩層111為遮罩而進行蝕刻製程以移除孔洞108之底部處的絕緣層110而使導電墊104露出。在一實施例中，可於同一蝕刻製程中移除孔洞108之底部處的絕緣層110與下方之介電層102而使導電墊104露出。接著，可移除遮罩層111。
如第2G圖所示，可於基底100之表面100b上形成圖案化導電層112b。在此實施例中，由基底100之表面100b朝表面100b延伸之穿孔係由凹陷106與孔洞108所共同形成，因此穿孔之深寬比較小，有利於導電層112b之沉積。導電層112b可延伸至凹陷106之側壁與底部，並進一步延伸至孔洞108之側壁與底部上而與導電墊104電性接觸。導電層112b可以(但不限於)類似於第1G-1I圖所示之方式形成。
接著，如第2H圖所示，於基底100之表面100b上形成圖案化保護層114。保護層114具有至少一開口，露出下方之導電層112b。在一實施例中，保護層114延伸進入凹陷106之中。在一實施例中，保護層114延伸進入孔洞108之中。在一實施例中，位於凹陷106中之保護層114具有一溝槽，其位置大抵與基底100之預定切割道SC重疊。接著，於保護層114露出導電層112b之開口中形成導電凸塊116。接著，沿著基底100之預定切割道SC切割基底100以形成至少一獨立的晶片封裝體10。由於保護層114於切割道處具有溝槽，因此切割過程中不會切割保護層114，可提升晶片封裝體之品質。在此情形下，保護層114之一側壁與基底100之一側壁不共平面。
本發明實施例可有許多變化。例如，請參照第3圖實施例，其類似於第2圖之實施例。主要差異在於第3圖實施例包括設置於基底之下表面上之間隔層(DAM)302及設置於間隔層上之基板，其例如是玻璃基板(Glass)304。導電墊104係位於間隔層302之中。此外，孔洞108係進一步穿過導電墊104並延伸進入間隔層302之中。因此，所形成之導電層112b亦延伸進入間隔層302之中。
第4圖顯示另一實施例，其類似於第3圖之實施例。主要差異在於孔洞108僅到達間隔層(DAM)302之表面而露出導電墊104。因此，所形成之導電層112b亦僅到達間隔層302之表面而未延伸進入間隔層302。
此外，應注意的是，第3圖及第4圖實施例中，關於孔洞到達間隔層或延伸進入間隔層之技術亦可應用至第1圖實施例之中。
在本發明實施例中，由基底100之表面100b朝表面100b延伸之穿孔係由凹陷106與孔洞108所共同形成。因此，穿孔之深寬比較小，有利於後續材料層之沉積，可於有限空間之內形成所需的導電通路，並可兼顧所形成導電通路之品質。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．晶片封裝體
100．．．基底
100a、100b．．．表面
102．．．介電層
103．．．遮罩層
104．．．導電墊
105．．．遮罩層
106．．．凹陷
107．．．遮罩層
108．．．孔洞
110．．．絕緣層
111．．．遮罩層
112．．．晶種層
112a、112b．．．導電層
113．．．遮罩層
114．．．保護層
116．．．導電凸塊
302．．．間隔層
304．．．基板
SC．．．切割道
θ1、θ2．．．角度
第1A-1L圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第2A-2H圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第3圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
第4圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
10．．．晶片封裝體
100．．．基底
100a、100b．．．表面
102．．．介電層
104．．．導電墊
106．．．凹陷
108．．．孔洞
110．．．絕緣層
112b．．．導電層
114．．．保護層
116．．．導電凸塊

Claims (10)

  1. 一種晶片封裝體的形成方法，包括：提供一基底，具有一第一表面及一第二表面，其中至少二個導電墊設置於基底之第一表面上；自該基底之該第二表面部分移除該基底以形成朝該第一表面延伸之至少二個孔洞，其中該些孔洞分別對齊於其中一對應的該些導電墊；在形成該些孔洞之後，自該基底之該第二表面部分移除該基底以形成朝該第一表面延伸之至少一凹陷，該凹陷與該些孔洞重疊；於該凹陷之側壁與底部上及該些孔洞之側壁上形成一絕緣層；以及於該絕緣層上形成一導電層，該導電層電性接觸其中一該些導電墊。
  2. 如申請專利範圍第1項所述之晶片封裝體的形成方法，更包括：於該基底之該第二表面上形成一保護層，該保護層具有露出該導電層之至少一開口；以及於該保護層之該開口中形成一導電凸塊。
  3. 如申請專利範圍第1項所述之晶片封裝體的形成方法，更包括沿著該基底之一預定切割道切割該基底以形成至少一晶片封裝體。
  4. 如申請專利範圍第3項所述之晶片封裝體的形成方法，其中該預定切割道位於其中兩個該些孔洞之間。
  5. 如申請專利範圍第3項所述之晶片封裝體的形成方 法，更包括於該基底之該第二表面上形成一保護層，其中該保護層具有一溝槽，重疊於該預定切割道。
  6. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中在形成該些孔洞之後及形成該凹陷之前，其中一該些孔洞之一側壁與該第二表面之間夾有一第一角度，且在形成該凹陷之後，該孔洞之該側壁與該第二表面之間夾有一大於該第一角度之一第二角度。
  7. 如申請專利範圍第2項所述之晶片封裝體的形成方法，更包括沿著該基底之一預定切割道切割該基底以形成至少一晶片封裝體。
  8. 如申請專利範圍第7項所述之晶片封裝體的形成方法，其中該預定切割道位於其中兩個該些孔洞之間。
  9. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中該凹陷與該些孔洞彼此連通。
  10. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中該些孔洞與該凹陷在該基底之該第一表面上之投影彼此重疊。
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US9711403B2 (en) 2017-07-18
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US20120184070A1 (en) 2012-07-19

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