TWI512920B - 晶片封裝體及其形成方法 - Google Patents

晶片封裝體及其形成方法 Download PDF

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TWI512920B
TWI512920B TW101116463A TW101116463A TWI512920B TW I512920 B TWI512920 B TW I512920B TW 101116463 A TW101116463 A TW 101116463A TW 101116463 A TW101116463 A TW 101116463A TW I512920 B TWI512920 B TW I512920B
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substrate
conductive
layer
chip package
conductive layer
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TW201246478A (en
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Chien Hung Liu
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Xintec Inc
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Description

晶片封裝體及其形成方法
本發明係有關於晶片封裝體，且特別是有關於微機電系統晶片封裝體(MEMS chip packages)。
隨著電子產品朝向輕、薄、短、小發展的趨勢，半導體晶片的封裝結構也朝向多晶片封裝(multi-chip package,MCP)結構發展，以達到多功能和高性能要求。多晶片封裝結構係將不同類型的半導體晶片，例如邏輯晶片、類比晶片、控制晶片或記憶體晶片，整合在單一封裝基底之上。
不同晶片之間可透過銲線而彼此電性連接。然而，隨著需整合的晶片數量上升，將多晶片以銲線相連接會造成封裝體體積無法有效縮小，且亦會佔去過多面積而造成製作成本增加，不利於可攜式電子產品的應用。
本發明一實施例提供一種晶片封裝體，包括：一第一基底；一第二基底，設置於該第一基底之上，其中該第二基底具有貫穿該第二基底之至少一開口，該至少一開口於該第二基底之中劃分出彼此電性絕緣的複數個導電區；一承載基底，設置於該第二基底之上；一絕緣層，設置於該承載基底之一表面及一側壁之上，其中該絕緣層填充於該第二基底之該至少一開口之中；以及一導電層，設置於該承載基底上之該絕緣層之上，且電性接觸其中一該些導電區。
本發明一實施例提供一種晶片封裝體的形成方法，包括：提供一第一基底；將一第二基底設置於該第一基底之上，其中該第二基底具有貫穿該第二基底之至少一開口，該至少一開口於該第二基底之中劃分出彼此電性絕緣的複數個導電區；將一承載基底設置於該第二基底之上；部分移除該承載基底以形成露出該第二基底之該至少一開口及該些導電區之至少一溝槽；於該承載基底上形成一絕緣層，其中該絕緣層延伸於該至少一溝槽之一側壁之上，且填充於該第二基底之該至少一開口之中；以及於該絕緣層之上形成一導電層，其中該導電層電性接觸其中一該些導電區。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此技藝人士自本揭露書之申請專利範圍中所能推及的所有實施方式皆屬本揭露書所欲揭露之內容。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝各種晶片。例如，其可用於封裝各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package;WSP)製程對影像感測元件、發光二極體(light-emitting diodes;LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率金氧半場效電晶體模組(power MOSFET modules)等半導體晶片進行封裝。
上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。在一實施中，上述切割後的封裝體係為一晶片尺寸封裝體(CSP;chip scale package)。晶片尺寸封裝體(CSP)之尺寸可僅略大於所封裝之晶片。例如，晶片尺寸封裝體之尺寸不大於所封裝晶片之尺寸的120%。
第1A-1K圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。在下述說明中，以採用晶圓級封裝製程的實施例為例。然應注意的是，本發明實施例亦可採用別於晶圓級封裝製程的其他適合製程。
如第1A圖所示，提供基底100。基底100可為半導體基底(例如，矽基底)或半導體晶圓(例如，矽晶圓)。採用半導體晶圓可利於晶圓級封裝製程的進行，可確保封裝品質，並節省製程成本及時間。在一實施例中，基底100中形成有複數個CMOS元件(未顯示)。基底100之表面上形成有複數個接墊102。這些接墊102分別電性連接至相應的CMOS元件。基底100之表面上還形成有保護層104，其可覆蓋基底100之表面，並具有露出接墊102之開口。保護層104之材質例如是氧化物、氮化物、氮氧化物、高分子材料、或前述之組合。
如第1A圖所示，提供基底200。基底200可為半導體基底(例如，矽基底)或半導體晶圓(例如，矽晶圓)。在一實施例中，基底100中形成有複數個CMOS元件(未顯示)。在一實施例中，基底200中形成有複數個MEMS元件。基底200之上表面上可形成有絕緣層206及承載基底204。絕緣層206之材質例如為氧化物、氮化物、氮氧化物、高分子材料、或前述之組合。在一實施例中，絕緣層206之材質為氧化矽。承載基底204例如可為半導體基底，例如是矽晶圓。基底200可透過形成於下表面上之接墊202而接合於基底100之上。如第1A圖所示，接墊202與接墊102係彼此接合。在一實施例中，接墊202及接墊102皆為導電材料。因此，接墊202及接墊102還可形成基底100與基底200之間的導電通路。例如，基底100中之CMOS元件與基底200中之MEMS元件可透過接墊202與接墊102而彼此傳遞電性訊號。在一實施例中，可分別對基底100及承載基底204進行薄化製程。
在一實施例中，複數個預定切割道SC將基底100與基底200之堆疊晶圓劃分成複數個區域。在後續封裝與切割製程之後，每一區域將成為一晶片封裝體。在基底200之每一區域之中，可形成有複數條貫穿基底200之縫隙(或開口)，其於基底200中劃分出複數個彼此不電性連接之導電區。每一導電區可電性連接至相應的接墊202。在一實施例中，這些導電區為基底200中之高摻雜區域。
如第1B圖所示，可部分移除承載基底204以形成至少一溝槽208。溝槽208可大抵沿著其中一預定切割道SC延伸。溝槽208可露出絕緣層206。在一實施例中，可透過微影及蝕刻製程(例如，乾式蝕刻)形成溝槽208。
第2圖顯示相應於第1B圖之結構的立體示意圖。如第2圖所示，基底200於溝槽208之下可具有至少一開口，其於基底200中劃分出複數個彼此不電性連接的導電區。在一實施例中，複數個開口201a、201b、及201c將溝槽208下之基底200劃分成複數個導電區203a、203b、203c、及203d。這些導電區因開口之隔離而彼此電性絕緣。在一實施例中，基底200之下表面上可形成有複數個接墊202，這些接墊202可延著溝槽208(或沿著預定切割道SC)而設置。每一導電區可電性連接至其中一相應的接墊而與基底100中之相應的CMOS元件電性連接。例如，在一實施例中，導電區203a可透過第2圖所示之接墊202及接墊102而與基底100中之相應的CMOS元件電性連接。
接著，如第1C圖所示，例如以蝕刻製程移除部分的絕緣層206以形成露出基底200之溝槽208a。請參照第2圖及第1C圖，溝槽208a可露出貫穿基底200之開口以及複數個彼此電性絕緣之導電區。例如，溝槽208a可露出開口201a、201b、及201c與導電區203a、203b、203c、及203d。
如第1D圖所示，於承載基底204之上形成絕緣層210。絕緣層210之材質可為高分子材料，例如是環氧樹脂。絕緣層210亦可為氧化物、氮化物、氮氧化物、其他適合高分子材料、或前述之組合。絕緣層210之形成方式例如是塗佈、氣相沉積、噴塗、或印刷等。絕緣層210可填入溝槽208a之中，並透過基底200之開口(例如，開口201a、201b、及201c)而填充於基底200與基底100之間的間隙。在一實施例中，絕緣層210可僅填充並封住基底200之開口(例如，開口201a、201b、及201c)而不填滿基底200與基底100之間的間隙。
接著，如第1E圖所示，移除部分的絕緣層210以自絕緣層210之表面形成朝基底200延伸之開口212。開口212之形成方式可為切割或蝕刻。開口212露出基底200。在一實施例中，開口212可延伸進入基底200之中。開口212可為一溝槽，並順著溝槽208a(或預定切割道SC)而延伸。開口212可露出基底200中之開口(例如，開口201a、201b、及201c)及導電區(例如，導電區203a、203b、203c、及203d)，其中所露出之開口中填充有先前所形成之絕緣層210。在採用切割製程形成開口212之實施例中，由於先前形成之絕緣層210已填充並封住基底200之開口(例如，開口201a、201b、及201c)，因此切割過程所造成之顆粒將不會經由基底200之開口而落至基底200與基底100之間的間隙而影響晶片封裝體的運作。
接著，可於承載基底204之上形成圖案化導電層。導電層之材質可包括鋁、銅、金、鎳、或前述之組合。導電層之形成方式可包括物理氣相沉積、化學氣相沉積、塗佈、電鍍、無電鍍、或前述之組合。以下，以採用電鍍製程為例說明一實施例之圖案化導電層的形成過程。
如第1F圖所示，於承載基底204之上形成晶種層214。晶種層214之材質例如為鋁或銅，其形成方式例如為濺鍍。晶種層214可沿著開口212之側壁而延伸於開口212之底部上，並與所露出之導電區(例如，導電區203a、203b、203c、及203d)電性接觸。
接著，如第1G圖所示，例如透過微影及蝕刻製程而將晶種層214圖案化以形成圖案化晶種層214a。圖案化晶種層214a可僅電性接觸其中一導電區，例如是導電區203a。晶種層214經圖案化之後，還可形成出電性連接其他導電區(例如，導電區203b、203c、或203d)之圖案化晶種層。由於先前所形成之絕緣層210已填充並封住基底200於溝槽208a底部處之開口(例如，開口201a、201b、及201c)，因此晶種層214之圖案化過程中所需採用之蝕刻液及/或蝕刻氣體將不會經由基底200之開口而到達接墊202與接墊102，可確保基底100與基底200之間的接合與電性連接。
如第1H圖所示，接著可透過電鍍製程而於晶種層214a之表面上電鍍導電材料以形成導電層214b。在一實施例中，導電層214b可包括鎳、金、銅、或前述之組合。
接著，如第1I圖所示，於導電層214b上形成防銲層216。防銲層216具有露出導電層214b之開口。如第1J圖所示，可於開口所露出之導電層214b之上形成導電凸塊218。
如第1K圖所示，可沿著預定切割道SC切割顯示於第1J圖之結構而形成複數個彼此分離的晶片封裝體。在一實施例中，晶片封裝體包括：一第一基底100；一第二基底200，設置於該第一基底100之上，其中該第二基底200具有貫穿該第二基底200之至少一開口(例如，開口201a、201b、及201c)，該至少一開口於該第二基底之中劃分出彼此電性絕緣的複數個導電區(例如，導電區203b、203c、及203d)；一承載基底204，設置於該第二基底200之上；一絕緣層210，設置於該承載基底之一表面及一側壁之上，其中該絕緣層210填充於該第二基底之該至少一開口之中；以及一導電層(214a及214b)，設置於該承載基底204及該絕緣層210之上，且電性接觸其中一該些導電區。
本發明實施例還可有許多變化。例如，在形成圖案化晶種層214a時，可使開口212底部上之圖案化晶種層214a不觸及預定切割道SC而使後續電鍍之導電層214b亦不觸及預定切割道SC。換言之，可透過圖案化製程之調整使所形成之圖案化導電層與預定切割道SC之間隔有間距而不直接接觸。在此情形下，所形成之防銲層216將於開口212之底部處包覆導電層之側邊。換言之，防銲層216包覆導電層之鄰近所接觸導電區之部分的一側邊。如此，在後續切割製程中，切割刀片將不會切割到圖案化導電層，可避免導電層因切割製程而受損或脫落。此外，由於防銲層216包覆導電層之側邊，可避免導電層氧化或受損。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．基底
102．．．接墊
104．．．保護層
200．．．基底
201a、201b、201c．．．開口
202．．．接墊
203a、203b、203c、203d．．．導電區
204．．．承載基底
206．．．絕緣層
208、208a．．．溝槽
210．．．絕緣層
212．．．開口
214、214a．．．晶種層
214b．．．導電層
216．．．防銲層
218．．．導電凸塊
SC．．．切割道
第1A-1K圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第2圖顯示相應於第1B圖之結構的立體示意圖。
100．．．基底
102．．．接墊
104．．．保護層
200．．．基底
202．．．接墊
204．．．承載基底
206．．．絕緣層
208a．．．溝槽
210．．．絕緣層
212．．．開口
214a．．．晶種層
214b．．．導電層
216．．．防銲層
218．．．導電凸塊

Claims (20)

  1. 一種晶片封裝體，包括：一第一基底；一第二基底，設置於該第一基底之上，其中該第二基底具有貫穿該第二基底之至少一開口，該至少一開口於該第二基底之中劃分出彼此電性絕緣的複數個導電區；一承載基底，設置於該第二基底之上；一絕緣層，設置於該承載基底之一表面及一側壁之上，其中該絕緣層填充於該第二基底之該至少一開口之中，且該絕緣層填滿該第二基底之該至少一開口；以及一導電層，設置於該承載基底上之該絕緣層之上，且電性接觸其中一該些導電區。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該導電層自該承載基底之該表面上之該絕緣層沿著該承載基底之該側壁朝該第二基底延伸。
  3. 如申請專利範圍第1項所述之晶片封裝體，更包括：一防銲層，設置於該導電層之上，其中該防銲層具有露出該導電層之一開口；以及一導電凸塊，設置於該防銲層之該開口之中，且電性接觸該導電層。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該防銲層包覆該導電層之鄰近其中一該些導電區之一部分的一側邊。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該導電層延伸進入該第二基底之中。
  6. 如申請專利範圍第1項所述之晶片封裝體，更包括一第一接墊及一第二接墊，設置於該第一基底與該第二基底之間，其中該第二接墊接合於該第一接墊之上，且電性連接其中一該些導電區。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該第一基底與該第二基底之間隔有一間隙。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該絕緣層填充於該間隙之中。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該承載基底之該側壁傾斜於該承載基底之該表面。
  10. 如申請專利範圍第1項所述之晶片封裝體，更包括一第二導電層，設置於該承載基底及該絕緣層之上，且電性接觸其中一該些導電區，其中該第二導電層不電性連接該導電層。
  11. 一種晶片封裝體的形成方法，包括：提供一第一基底；將一第二基底設置於該第一基底之上，其中該第二基底具有貫穿該第二基底之至少一開口，該至少一開口於該第二基底之中劃分出彼此電性絕緣的複數個導電區；將一承載基底設置於該第二基底之上；部分移除該承載基底以形成露出該第二基底之該至少一開口及該些導電區之至少一溝槽；於該承載基底上形成一絕緣層，其中該絕緣層延伸於該至少一溝槽之一側壁之上，且填充於該第二基底之該至少一開口之中，且該絕緣層填滿該第二基底之該至少一開 口；以及於該絕緣層之上形成一導電層，其中該導電層電性接觸其中一該些導電區。
  12. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括在形成該至少一溝槽之前，薄化該承載基底。
  13. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括薄化該第一基底。
  14. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括：於該導電層之上形成一防銲層，該防銲層具有露出該導電層之一開口；以及於該防銲層之該開口中形成一導電凸塊，該導電凸塊電性接觸該導電層。
  15. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括切割移除部分的該絕緣層以於該絕緣層中形成一溝槽開口，該溝槽開口露出該第二基底之該至少一開口及該些導電區。
  16. 如申請專利範圍第15項所述之晶片封裝體的形成方法，其中該溝槽開口延伸進入該第二基底之中。
  17. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括於該絕緣層之上形成一第二導電層，其中該第二導電層電性接觸其中一該些導電區，且該第二導電層不電性連接該導電層。
  18. 如申請專利範圍第17項所述之晶片封裝體的形成方法，其中該導電層及該第二導電層之形成步驟包括： 於該絕緣層上形成一導電材料層；以及將該導電材料層圖案化以形成該導電層及該第二導電層。
  19. 如申請專利範圍第18項所述之晶片封裝體的形成方法，更包括於該導電層及該第二導電層之上電鍍一導電材料。
  20. 如申請專利範圍第11項所述之晶片封裝體的形成方法，更包括於該至少一溝槽之一底部進行一切割製程以形成複數個彼此分離的晶片封裝體。
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US9117809B1 (en) 2014-03-09 2015-08-25 Alpha & Omega Semiconductor (Cayman), Ltd. Ultra-thin semiconductor device and preparation method thereof
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