TWI578478B - 晶片封裝體及其形成方法 - Google Patents
晶片封裝體及其形成方法 Download PDFInfo
- Publication number
- TWI578478B TWI578478B TW100102071A TW100102071A TWI578478B TW I578478 B TWI578478 B TW I578478B TW 100102071 A TW100102071 A TW 100102071A TW 100102071 A TW100102071 A TW 100102071A TW I578478 B TWI578478 B TW I578478B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- hole
- insulating layer
- chip package
- pad
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 28
- 239000010410 layer Substances 0.000 claims description 78
- 239000000758 substrate Substances 0.000 claims description 75
- 239000000853 adhesive Substances 0.000 claims description 18
- 230000001070 adhesive effect Effects 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 11
- 230000003287 optical effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000000463 material Substances 0.000 description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OGZARXHEFNMNFQ-UHFFFAOYSA-N 1-butylcyclobutene Chemical compound CCCCC1=CCC1 OGZARXHEFNMNFQ-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 150000001252 acrylic acid derivatives Chemical class 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000417 polynaphthalene Polymers 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Led Device Packages (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Electroluminescent Light Sources (AREA)
Description
本發明係有關於晶片封裝體及其形成方法,且特別是有關於具有導通孔之晶片封裝體及其形成方法。
晶片封裝體中,例如是感光晶片封裝體或發光晶片封裝體,其光線之接收與發射常受其上之介質(例如,玻璃)影響,使光線之接收與發射不順利。此外,晶片封裝體亦常受到應力之影響而使可靠度下降。再者,晶片封裝體的形成過程中,常需繁雜的圖案化製程,增加了製作成本上的負擔。
因此,業界亟需能減輕或解決上述問題之晶片封裝技術。
本發明一實施例提供一種晶片封裝體,包括一基底,具有一上表面及一下表面;一晶片,設置於該基底中或上;一接墊,設置於該基底中或上,其中該接墊與該晶片電性連接;一孔洞,自該下表面朝該上表面延伸,且該孔洞露出該接墊,其中該孔洞之靠近該下表面之一下開口之口徑小於該孔洞之靠近該上表面之一上開口之口徑;一絕緣層,位於該孔洞之一側壁上;以及一導電層,位於該絕緣層上,且電性連接至該接墊。
本發明一實施例提供一種晶片封裝體的形成方法,包括提供一基底,具有一上表面及一下表面,該基底中或上包括一晶片及一接墊,該接墊與該晶片電性連接;自該基底之該下表面移除部份的該基底以形成一孔洞,該孔洞露出該接墊,其中該孔洞之靠近該下表面之一下開口之口徑小於該孔洞之靠近該上表面之一上開口之口徑;於該孔洞之一側壁及一底部上形成一絕緣層;移除該孔洞之該底部上之部分的該絕緣層以露出部分的該接墊;以及於該孔洞之該側壁及該底部上形成一導電層,該導電層與該接墊電性接觸。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是,本發明提供許多可供應用的發明概念,其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式,非用以限制本發明之範圍。此外,在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明,不代表所討論之不同實施例及/或結構之間具有任何關連性。再者,當述及一第一材料層位於一第二材料層上或之上時,包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
第1A-1G圖顯示本發明一實施例之晶片封裝體的一系列製程剖面圖。如第1A圖所示,首先,提供基底100,其具有上表面100a及相反之下表面100b。基底100可包括半導體材料、陶瓷材料、或高分子材料等。在一實施例中,基底100為矽基底。在另一實施例中,基底100為矽晶圓,並較佳以晶圓級封裝配合切割步驟,以同時形成出複數個晶片封裝體,可節約製程成本與時間。
如第1A圖所示,基底100中或上可設置或形成有晶片102。晶片102例如包括(但不限於)邏輯運算晶片、微機電系統晶片、微流體系統晶片、或利用熱、光線及壓力等物理變化量來測量的物理感測器晶片、射頻元件晶片、加速計晶片、陀螺儀晶片、微制動器晶片、表面聲波元件晶片、壓力感測器晶片、噴墨頭晶片、發光元件晶片、或太陽能電池晶片等。在此實施例中,晶片102係採用感光晶片為例,例如是一影像感測晶片。在此情形下,可選擇性於晶片102上設置光學透鏡106。光學透鏡106可包括透鏡陣列(lens array)。例如,光學透鏡106可為微透鏡陣列(micro lens array)。或者,在另一實施例中,晶片102係採用發光晶片,例如是一發光二極體晶片。
如第1A圖所示,基底100中或上還包括接墊104,其與晶片102電性連接。雖然,在圖式中未見晶片102與接墊104之間的導電通路,然此技藝人士當可明瞭可透過任何適合導電線路圖案之形成而使接墊104與晶片102電性連接。此外,在一實施例中,不同於第1A圖所示之實施例,接墊104本身可為晶片102之一部分。接墊104之材質一般為金屬材料,例如是鋁、銅、金、前述之相似物、或前述之組合。
此外,如第1A圖所示,在一實施例中,可選擇性以
黏著膠110將暫時基底108貼合於基底100之上。暫時基底108將於後續的研磨製程中暫時性地用作基底,因此較佳具有大抵平坦之上表面。暫時基底108之材質可例如包括半導體材料、陶瓷材料、或金屬材料等。在一實施例中,暫時基底108較佳採用矽基底。由於紅外線可穿透矽基底,當採用矽基底作為暫時基底108時,可進一步透過紅外線偵測下方基底100中所預先形成之對準標記(未顯示),有助於使暫時基底108與基底100之間的貼合準確。在一實施例中,較佳採用晶圓級封裝來形成晶片封裝體,因此較佳採用矽晶圓作為暫時基底108。黏著膠110較佳選用可輕易移除之材質,例如可透過能量的施加而使之斷鍵,有助於連同暫時基底108自基底100上移除。在一實施例中,可例如以加熱或照射光線(如雷射、紫外線等)等方式移除黏著膠110。在一實施例中,黏著膠110移除後,可取下暫時基底108回收再利用。此外,當以晶圓級封裝形成晶片封裝體時,較佳先取下暫時基底108之後,接著才進行切割晶圓之步驟以形成複數個晶片封裝體。
接著,如第1B圖所示,自基底100之下表面100b移除部份的基底100以形成孔洞112,其露出接墊104。在一實施例中,孔洞112靠近下表面100b之下開口的口徑小於孔洞112靠近上表面100a之上開口的口徑,而具有“倒角”結構(即,具有倒圓錐或例角錐之輪廓,且具陡峭側壁)。因此,孔洞112之側壁係傾斜於基底100之表面。孔洞112之形成方式包括以乾蝕刻移除基底100。
例如,可先以主要蝕刻移除基底,並接著改變蝕刻製程條件以進行過蝕刻。例如,可調整蝕刻製程中之功率、壓力、蝕刻反應氣體之濃度等製程參數以獲得具有“倒角”結構(即,具有倒圓錐或倒角錐之輪廓,且具陡峭側壁)之孔洞。
第2A圖顯示相應於第1B圖之局部放大剖面圖,其更清楚顯示本發明一實施例之孔洞112。如第2A圖所示,孔洞112之下開口的口徑W1小於孔洞112之上開口的口徑W2。孔洞112之開口可具有各種形狀,例如是圓形、橢圓性、正方形、或長方形等。當開口為圓形時,上述口徑即為圓形開口之直徑。
如第2A圖所示,在此實施例中,由於接墊104之下表面大抵平行於基底100之上表面,因此孔洞112之側壁與接墊104之下表面之間的夾角θ大抵相同於孔洞112之側壁與上表面100a之間的夾角。在一實施例中,夾角θ係大於90度且小於等於92度。夾角θ之決定方式例如可利用三角函數作計算。可先量測孔洞112之深度d、下開口口徑W1、及上開口口徑W2。接著,如圖所示,夾角ψ係等於tan-1[2d/(W2-W1)]。因此,可知夾角θ係等於(π-ψ)。
在形成孔洞112之後,接著如第1C圖所示,於孔洞112之側壁及底部上形成絕緣層114。絕緣層114之材質例如包括環氧樹脂、防銲材料、或其他適合之絕緣物質,例如無機材料之氧化矽層、氮化矽層、氮氧化矽層、金屬氧化物、或前述之組合;或亦可為有機高分子材料之
聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene,BCB,道氏化學公司)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates)等。絕緣層114的形成方式可包含塗佈方式,例如旋轉塗佈(spin coating)、噴塗(spray coating)、或淋幕塗佈(curtain coating),或其他適合之沈積方式,例如,液相沈積、物理氣相沈積、化學氣相沈積、低壓化學氣相沈積、電漿增強式化學氣相沈積、快速熱化學氣相沈積、或常壓化學氣相沈積等製程。在一實施例中,基底100為一矽基底,而絕緣層114可為對矽基底進行熱氧化製程而得之氧化矽層。在此實施例中,絕緣層114蓋住接墊104,並延伸在基底100之下表上100b。
第2B圖顯示對應至第1C圖之局部放大剖面圖,其顯示孔洞112側壁上之絕緣層114靠近下表面100b的部分P1之厚度為t1。
接著,如第1D圖所示,移除孔洞112底部上之部分的絕緣層以形成圖案化絕緣層114a,其露出部分的接墊104。第2C圖顯示對應至第1D圖之局部放大剖面圖。請參照第2B及2C圖,在一實施例中,係以絕緣層114靠近下表面100b之部分P1為遮罩,並對絕緣層114進行蝕刻製程以移除孔洞112底部上之部分的絕緣層114而露出接墊104。由於孔洞112靠近下表面100b之開口的口徑較小,因此絕緣層114a之部分P1可自然擋住部分的蝕刻劑,可避免側壁上之絕緣層受到蝕刻移除。因此,可不需形成圖案化光阻層於絕緣層114上便可將之圖案
化為圖案化絕緣層114a,並形成露出接墊104之開口。
在一實施例中,由於不形成圖案化光阻層於絕緣層114上便進行蝕刻製程,因此在孔洞112底部上之部分絕緣層被移除之後,絕緣層之其他與蝕刻劑接觸之部分的厚度將會變薄。例如,絕緣層之部分P1的厚度由厚度t1縮減至厚度t2。此外,絕緣層靠近下表面100b之部分P1的厚度t2還大於絕緣層靠近上表面100a之部分的厚度t3。此外,在一實施例中,在移除部份的絕緣層之後,還使絕緣層形成出轉角部分P3。轉角部分P3位於孔洞112之側壁與接墊104之間的轉角上,且延伸於部分的接墊104上。在一實施例中,絕緣層之轉角部分P3包括斜面115,且斜面115之法向量N朝向基底100之下表面100b。
接著,請參照第1E圖,於孔洞112之側壁及底部上形成導電層116。導電層116與接墊104電性接觸,因此亦與晶片102電性連接。導電層116之材質例如包括銅、鋁、金、鉑、或前述之組合,其形成方式例如為物理氣相沉積、化學氣相沉積、電鍍、或無電鍍等。
如第1F圖所示,接著於基底100之下表面100b上形成圖案化保護層118,其露出部分延伸在下表面100b上的導電層116。可於露出之導電層116上進行凸塊製程以形成導電凸塊120,其可用以與其他電子元件整合。例如,可以覆晶之方式將晶片封裝體設置於印刷電路板上。
第3圖顯示第1F圖實施例之下表面100b的上視圖,其中保護層118係與基底100之邊緣隔有間距d1而不與基底100之邊緣接觸。由於基底之邊緣或其中之材料層
堆疊之邊緣處較易受應力破壞,因此於圖案化保護層之同時,移除邊緣處之具較高應力的保護層118,將有助於提升晶片封裝體之可靠度。
接著,如第1G圖所示,移除黏著膠110及暫時基底108。如上所述,可以加熱或照射光線之方式而使黏著膠110中之化合物發生斷鍵,從而移除黏著膠110,並可將暫時基底回收再利用。在一實施例中,基底100係採用矽晶圓以進行晶圓級封裝。此時,在移除黏著膠110及暫時基底108之後,可進一步進行切割製程以分離所形成之複數個晶片封裝體。
如第1G圖所示,在一實施例中,晶片102係感光晶片(或發光晶片)。感光晶片(或發光晶片)之感光表面(或出光表面)不與黏著膠直接接觸。因此,光線大抵不受到其他介質之吸收或折射。在另一情形中,晶片102上設置有光學透鏡106及/或鏡頭模組(未顯示)。此時,感光晶片(或發光晶片)之感光表面(或出光表面)仍不與黏著膠直接接觸,因而光線大抵不受到其他介質(如黏著膠)之吸收或折射,可使光線之接收或發出順利。
本發明實施例透過使用可輕易移除之黏著膠與暫時基底,可使晶片之封裝順利進行。在移除黏著膠與暫時基底之後,可使晶片封裝體對於光線之接收或發射更為順利。透過形成具“倒角結構”之孔洞(即,具有倒圓錐或倒角錐之輪廓,且具陡峭側壁),可使後續形成露出接墊之絕緣層開口時,不需額外的微影製程,可大幅減少製程成本與時間。透過形成圖案化保護層,使之不與基底之邊緣接觸,可避免晶片封裝體中之各材料層受到應力破壞,有效提升晶片封裝體之良率與可靠度。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100...基底
100a、100b...表面
102...晶片
104...接墊
106...光學透鏡
110...黏著膠
112...孔洞
114、114a...絕緣層
115...斜面
116...導電層
118...保護層
120...導電凸塊
d...深度
d1...間距
N...法向量
P1、P2、P3...部分
t1、t2、t3...厚度
W1、W2...口徑
θ、ψ...夾角
第1A-1G圖顯示本發明一實施例之晶片封裝體的一系列製程剖面圖。
第2A-2C圖顯示分別相應於第1B-1D圖實施例之晶片封裝體的一系列局部放大剖面圖。
第3圖顯示第1F圖實施例之下表面的上視圖。
100...基底
100a、100b...表面
102...晶片
104...接墊
106...光學透鏡
112...孔洞
114a...絕緣層
116...導電層
118...保護層
120...導電凸塊
Claims (16)
- 一種晶片封裝體,包括:一基底,具有一上表面及一下表面;一晶片,設置於該基底中或上;一接墊,設置於該基底中或上,其中該接墊與該晶片電性連接;一孔洞,自該下表面朝該上表面延伸,且該孔洞露出該接墊,其中該孔洞之靠近該下表面之一下開口之口徑小於該孔洞之靠近該上表面之一上開口之口徑;一絕緣層,位於該孔洞之一側壁上,該絕緣層包括一轉角部分,位於該孔洞之該側壁與該接墊之間的一轉角上,且延伸在該接墊的部分表面上,該絕緣層之該轉角部分包括一斜面,該斜面之一法向量朝向該基底之該下表面,且該斜面使該孔洞之該上開口之口徑漸減;以及一導電層,位於該絕緣層上,且電性連接至該接墊。
- 如申請專利範圍第1項所述之晶片封裝體,其中該孔洞之該側壁與該基底之該上表面之間的一夾角大於90度且小於等於92度。
- 如申請專利範圍第1項所述之晶片封裝體,其中該絕緣層靠近該下表面之一第一部分之厚度大於該絕緣層靠近該上表面之一第二部分之厚度。
- 如申請專利範圍第1項所述之晶片封裝體,其中該導電層之靠近該下表面之一第一部分之厚度大於該絕緣層靠近該上表面之一第二部分之厚度。
- 如申請專利範圍第1項所述之晶片封裝體,其中該晶片為一感光晶片或一發光晶片。
- 如申請專利範圍第5項所述之晶片封裝體,其中該晶片之一感光表面或一出光表面不與黏著膠直接接觸。
- 如申請專利範圍第5項所述之晶片封裝體,更包括一光學透鏡,位於該晶片之上方,且該該晶片不與黏著膠直接接觸。
- 如申請專利範圍第1項所述之晶片封裝體,更包括一保護層,位於該基底之該下表面上,且與該基底之一邊緣隔有一間距而不與該邊緣接觸。
- 一種晶片封裝體的形成方法,包括:提供一基底,具有一上表面及一下表面,該基底中或上包括一晶片及一接墊,該接墊與該晶片電性連接;自該基底之該下表面移除部份的該基底以形成一孔洞,該孔洞露出該接墊,其中該孔洞之靠近該下表面之一下開口之口徑小於該孔洞之靠近該上表面之一上開口之口徑;於該孔洞之一側壁及一底部上形成一絕緣層;移除該孔洞之該底部上之部分的該絕緣層以露出部分的該接墊,且使該絕緣層形成出一轉角部分,位於該孔洞之該側壁與該接墊之間的一轉角上,且延伸在該接墊的部分表面上,該絕緣層之該轉角部分包括一斜面,該斜面之一法向量朝向該基底之該下表面,且該斜面使該孔洞之該上開口之口徑漸減;以及 於該孔洞之該側壁及該底部上形成一導電層,該導電層與該接墊電性接觸。
- 如申請專利範圍第9項所述之晶片封裝體的形成方法,其中該絕緣層之移除包括以該絕緣層靠近該下表面之一第一部分為遮罩,並對該絕緣層進行一蝕刻製程以移除該孔洞之該底部上之部分的該絕緣層以露出部分的該接墊。
- 如申請專利範圍第10項所述之晶片封裝體的形成方法,其中在部分的該絕緣層被移除之後,該絕緣層之該第一部分的厚度變薄。
- 如申請專利範圍第9項所述之晶片封裝體的形成方法,其中形成該絕緣層與移除部份的該絕緣層之步驟之間,不包括於該絕緣層上形成一圖案化光阻層之步驟。
- 如申請專利範圍第9項所述之晶片封裝體的形成方法,更包括在形成該孔洞之前,自該基底之該下表面薄化該基底。
- 如申請專利範圍第13項所述之晶片封裝體的形成方法,其中在薄化該基底之前,更包括:以一黏著膠將一暫時基底貼合於該基底之該上表面上;以及以該暫時基底為支撐,自該基底之該下表面進行該薄化步驟。
- 如申請專利範圍第14項所述之晶片封裝體的形成方法,其中在形成該導電層之後,更包括在該基底之 該下表面上形成一保護層,該保護層與該基底之一邊緣隔有一間距而不與該邊緣接觸。
- 如申請專利範圍第15項所述之晶片封裝體的形成方法,在形成該保護層之後,更包括移除該黏著膠及該暫時基底。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US29685710P | 2010-01-20 | 2010-01-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201126676A TW201126676A (en) | 2011-08-01 |
TWI578478B true TWI578478B (zh) | 2017-04-11 |
Family
ID=43899593
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100102071A TWI578478B (zh) | 2010-01-20 | 2011-01-20 | 晶片封裝體及其形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8207615B2 (zh) |
EP (1) | EP2357665A3 (zh) |
CN (1) | CN102157483B (zh) |
TW (1) | TWI578478B (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112010003715T8 (de) * | 2009-09-20 | 2013-01-31 | Viagan Ltd. | Baugruppenbildung von elektronischen Bauelementen auf Waferebene |
CN102592982B (zh) * | 2011-01-17 | 2017-05-03 | 精材科技股份有限公司 | 晶片封装体的形成方法 |
US8487410B2 (en) * | 2011-04-13 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon vias for semicondcutor substrate and method of manufacture |
TWI485818B (zh) * | 2011-06-16 | 2015-05-21 | Xintec Inc | 晶片封裝體及其形成方法 |
DE102011116409B3 (de) | 2011-10-19 | 2013-03-07 | Austriamicrosystems Ag | Verfahren zur Herstellung dünner Halbleiterbauelemente |
TWI480990B (zh) * | 2011-11-15 | 2015-04-11 | Xintec Inc | 晶片封裝體及其形成方法 |
TWI523208B (zh) * | 2013-01-10 | 2016-02-21 | 精材科技股份有限公司 | 影像感測晶片封裝體及其製作方法 |
CN103633038B (zh) * | 2013-11-29 | 2016-08-17 | 苏州晶方半导体科技股份有限公司 | 封装结构及其形成方法 |
US9397138B2 (en) | 2014-03-25 | 2016-07-19 | Xintec Inc. | Manufacturing method of semiconductor structure |
TWI582677B (zh) * | 2014-12-15 | 2017-05-11 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
CN105070667A (zh) * | 2015-09-02 | 2015-11-18 | 华天科技(昆山)电子有限公司 | 图像传感芯片封装方法 |
TWI649856B (zh) * | 2016-05-13 | 2019-02-01 | 精材科技股份有限公司 | 晶片封裝體與其製造方法 |
JP2018107227A (ja) * | 2016-12-26 | 2018-07-05 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、半導体装置の製造方法、及び、固体撮像素子 |
CN108511409B (zh) * | 2018-04-19 | 2021-03-02 | 苏州晶方半导体科技股份有限公司 | 半导体芯片的晶圆级封装方法及其封装结构 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060108695A1 (en) * | 2004-10-26 | 2006-05-25 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of the same |
US20080296714A1 (en) * | 2007-05-31 | 2008-12-04 | Samsung Electro-Mechanics Co., Ltd. | Wafer level package of image sensor and method for manufacturing the same |
US20090302430A1 (en) * | 2008-06-06 | 2009-12-10 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20090305502A1 (en) * | 2008-06-10 | 2009-12-10 | Ho-Jin Lee | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW437097B (en) * | 1999-12-20 | 2001-05-28 | Hannstar Display Corp | Manufacturing method for thin film transistor |
US6350386B1 (en) * | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly |
JP3646071B2 (ja) * | 2001-03-19 | 2005-05-11 | シャープ株式会社 | 化合物半導体装置の製造方法および化合物半導体装置 |
WO2006013731A1 (ja) * | 2004-08-06 | 2006-02-09 | A. L. M. T. Corp. | 集合基板、半導体素子搭載部材、半導体装置、撮像装置、発光ダイオード構成部材、および発光ダイオード |
CN101414597B (zh) * | 2004-08-06 | 2010-09-15 | 联合材料公司 | 半导体元件搭载部件、半导体装置及摄像装置 |
JP4966487B2 (ja) * | 2004-09-29 | 2012-07-04 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
JP2008053568A (ja) * | 2006-08-25 | 2008-03-06 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP5302522B2 (ja) * | 2007-07-02 | 2013-10-02 | スパンション エルエルシー | 半導体装置及びその製造方法 |
-
2011
- 2011-01-20 US US13/010,478 patent/US8207615B2/en active Active
- 2011-01-20 CN CN201110025975.6A patent/CN102157483B/zh active Active
- 2011-01-20 TW TW100102071A patent/TWI578478B/zh active
- 2011-01-20 EP EP11151515.1A patent/EP2357665A3/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060108695A1 (en) * | 2004-10-26 | 2006-05-25 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of the same |
US20080296714A1 (en) * | 2007-05-31 | 2008-12-04 | Samsung Electro-Mechanics Co., Ltd. | Wafer level package of image sensor and method for manufacturing the same |
US20090302430A1 (en) * | 2008-06-06 | 2009-12-10 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20090305502A1 (en) * | 2008-06-10 | 2009-12-10 | Ho-Jin Lee | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby |
Also Published As
Publication number | Publication date |
---|---|
US8207615B2 (en) | 2012-06-26 |
EP2357665A2 (en) | 2011-08-17 |
TW201126676A (en) | 2011-08-01 |
CN102157483A (zh) | 2011-08-17 |
EP2357665A3 (en) | 2014-01-01 |
CN102157483B (zh) | 2015-11-25 |
US20110175236A1 (en) | 2011-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI578478B (zh) | 晶片封裝體及其形成方法 | |
JP6110889B2 (ja) | チップパッケージおよびその製造方法 | |
TWI512932B (zh) | 晶片封裝體及其製造方法 | |
US8237187B2 (en) | Package structure for chip and method for forming the same | |
TWI546925B (zh) | 晶片封裝體及其形成方法 | |
TWI512930B (zh) | 晶片封裝體及其形成方法 | |
US8872196B2 (en) | Chip package | |
TWI459485B (zh) | 晶片封裝體的形成方法 | |
TWI512918B (zh) | 晶片封裝體及其形成方法 | |
US9165890B2 (en) | Chip package comprising alignment mark and method for forming the same | |
TWI529821B (zh) | 晶片封裝體及其形成方法 | |
US9006896B2 (en) | Chip package and method for forming the same | |
US9633935B2 (en) | Stacked chip package including substrate with recess adjoining side edge of substrate and method for forming the same | |
TWI485818B (zh) | 晶片封裝體及其形成方法 | |
TW201436142A (zh) | 晶片封裝體及其形成方法 | |
JP2012160734A (ja) | インターポーザ及びその形成方法 | |
TWI434440B (zh) | 晶片封裝體及其形成方法 | |
US10937760B2 (en) | Method for manufacturing a chip package | |
CN110970362B (zh) | 芯片封装体的制造方法 |