TW201436142A - 晶片封裝體及其形成方法 - Google Patents

晶片封裝體及其形成方法 Download PDF

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Publication number
TW201436142A
TW201436142A TW103107152A TW103107152A TW201436142A TW 201436142 A TW201436142 A TW 201436142A TW 103107152 A TW103107152 A TW 103107152A TW 103107152 A TW103107152 A TW 103107152A TW 201436142 A TW201436142 A TW 201436142A
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Taiwan
Prior art keywords
recess
layer
chip package
light shielding
semiconductor substrate
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TW103107152A
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English (en)
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TWI546921B (zh
Inventor
Yi-Min Lin
Yi-Ming Chang
Shu-Ming Chang
Yen-Shih Ho
Tsang-Yu Liu
Chia-Ming Cheng
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Xintex Inc
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Publication of TW201436142A publication Critical patent/TW201436142A/zh
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Publication of TWI546921B publication Critical patent/TWI546921B/zh

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Abstract

本發明一實施例提供一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；一第一凹陷，自該第一表面朝該第二表面延伸；一第二凹陷，自該第一凹陷之一底部朝該第二表面延伸，其中該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入該第一凹陷及/或該第二凹陷；一絕緣層，位於該導線層與該半導體基底之間；以及一金屬遮光層，設置於該第一表面上，且具有至少一孔洞，其中該至少一孔洞之形狀為一四邊形。

Description

晶片封裝體及其形成方法
本揭露書是有關於晶片封裝體，且特別是有關於採用晶圓級封裝製程製作之晶片封裝體。
晶片封裝製程是形成電子產品過程中之一重要步驟。晶片封裝體除了將晶片保護於其中，使免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
由於電子產品縮小化之需求仍持續，如何於有限空間中設置更多的導電線路成為重要課題。此外，亦有避免外界光線影響晶片封裝體之運作之需求。
本發明一實施例提供一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；一第一凹陷，自該第一表面朝該第二表面延伸；一第二凹陷，自該第一凹陷之一底部朝該第二表面延伸，其中該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入該第一凹陷及/或該第二凹陷；一絕緣層，位於該導線層與該半導體基底之間；以及一金屬遮光層，設置於該第一表面上，且具有至少一孔洞，其中該至少一孔洞之形狀為一四邊形。
本發明一實施例提供一種晶片封裝體，包括：一 半導體基底，具有一第一表面及一第二表面；一第一凹陷，自該第一表面朝該第二表面延伸；一第二凹陷，自該第一凹陷之一底部朝該第二表面延伸，其中該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入該第一凹陷及/或該第二凹陷；一絕緣層，位於該導線層與該半導體基底之間；以及一金屬遮光層，設置於該第一表面上，且具有至少一孔洞，其中該至少一孔洞之形狀為一三邊形、一五邊形、一六邊形、或一七邊形。
本發明一實施例提供一種晶片封裝體的形成方法，包括：提供至少一半導體基底，具有一第一表面及一第二表面；自該第一表面移除部分的該半導體基底以於該半導體基底之中形成一第一凹陷及一第二凹陷，其中該第一凹陷朝該第二表面延伸，而該第二凹陷自該第一凹陷之一底部朝該第二表面延伸；於該第一表面上形成一絕緣層，該絕緣層延伸進入該第一凹陷及該第二凹陷；於該絕緣層上形成一導線層，該導線層延伸進入該第一凹陷及/或該第二凹陷；於該絕緣層上形成一金屬遮光層，該具有至少一孔洞，其中該至少一孔洞之形狀為一四邊形；以及沿著該半導體基底之至少一預定切割道進行一切割製程以形成至少一晶片封裝體，其中在該切割製程之後，該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面。
100‧‧‧基底
100a、100b‧‧‧表面
101‧‧‧介電層
102‧‧‧元件區
104a、104G‧‧‧導電墊
116‧‧‧絕緣層
117‧‧‧金屬層
118‧‧‧導線層
130a、130b‧‧‧凹陷
204‧‧‧銲線
260a、260b‧‧‧金屬遮光層
262‧‧‧孔洞
302‧‧‧容器
304‧‧‧蝕刻液
306‧‧‧放置台
SC‧‧‧預定切割道
第1A-1D圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第2圖顯示根據本發明一實施例之晶片封裝體的上視圖。
第3圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第4A及4B圖分別顯示根據本發明實施例之晶片封裝體的局部上視圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本揭露書提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，本揭露書可能於許多實施例重複使用標號及/或文字。此重複僅為了簡化與清楚化，不代表所討論之不同實施例之間必然有關聯。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。為了簡單與清楚化，許多結構可能會繪成不同的尺寸。
本發明一實施例之晶片封裝體可用以封裝影像感測器晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率金氧半場效電晶體模組(power MOSFET modules)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。在一實施中，上述切割後的封裝體係為一晶片尺寸封裝體(CSP；chip scale package)。晶片尺寸封裝體(CSP)之尺寸可僅略大於所封裝之晶片。例如，晶片尺寸封裝體之尺寸不大於所封裝晶片之尺寸的120%。
第1A-1D圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第1A圖所示，提供半導體基底100，其具有表面100a及表面100b。半導體基底100例如包括矽基底、矽鍺基底、砷化鎵基底、其他適合的半導體基底、或前述之組合。 在一實施例中，半導體基底100為一半導體晶圓(例如，矽晶圓)。因此，可進行晶圓級封裝製程以節省製作成本與製作時間。半導體基底100可定義有至少一預定切割道SC。在後續製程中，可沿著預定切割道SC切割半導體基底100以形成複數個彼此分離之晶片封裝體。
半導體基底100中可形成有元件區102。元件區102中可形成有主動元件或被動元件、數位電路或類比電路等積體電路的電子元件，例如是有關於光電元件、微機電系統、微流體系統、或利用熱、光線及壓力等物理量變化來測量的物理感測器。在一實施例中，元件區102中形成有影像感測元件。或者，元件區102中可形成有發光二極體、太陽能電池、射頻元件、加速計、陀螺儀、微制動器、表面聲波元件、壓力感測器、噴墨頭、或功率金氧半場效電晶體模組。
半導體基底100之表面100a上可形成有介電層101。介電層101之材質可包括(但不限於)氧化矽、氮化矽、氮氧化矽、或前述之組合。介電層101中可形成有複數個導電墊104a。每一導電墊104a可包括複數個導電層之疊層。導電墊104a可透過介電層101中之內連線結構(未顯示)而與元件區102中之對應的元件電性連接。換言之，導電墊104a電性連接元件區102，可用於輸入及/或輸出電性訊號。在一實施例中，可移除部分的介電層101而使導電墊104a露出。
如第1B圖所示，在一實施例中，可透過圖案化製程及/或切割製程移除部分的半導體基底100以形成複數個凹陷。這些凹陷可自表面100a朝表面100b延伸，並彼此相連通。 此外，在後續沿著預定切割道SC進行之切割製程之後，這些凹陷之側壁與底部可共同形成半導體基底100之外側表面。即，在切割製程之後，半導體基底100之部分的外側表面係由這些凹陷之側壁與底部所共同形成。在第1B圖之實施例中，以兩個凹陷130b及130a為例做說明。然應注意的是，在其他實施例中，半導體基底100可具有三個或三個以上之相連通凹陷，且在切割製程之後，這些凹陷之底部及側邊可共同形成半導體基底100之外側表面。
如第1B圖所示，凹陷130b可自半導體基底100之表面100a朝表面100b延伸。凹陷130a可自凹陷130b之底部朝表面100b延伸。在後續沿著預定切割道SC進行切割製程之後，凹陷130b之側壁及底部與凹陷130a之側壁及底部可共同形成半導體基底100之外側表面。
接著，如第1C圖所示，可於半導體基底100之表面100a上形成絕緣層116。絕緣層116可延伸進入凹陷130b及凹陷130a。在一實施例中，絕緣層116可順應性形成於凹陷130 b及凹陷130a之側壁及底部上。在一實施例中，可採用化學氣相沉積製程、旋轉塗佈製程、噴塗製程、熱氧化製程、氮化製程、其他適合製程、或前述之組合以形成絕緣層116。絕緣層116之材質可包括(但不限於)氧化矽、氮化矽、氮氧化矽、高分子材料、或前述之組合。絕緣層116可具有露出導電墊104a之開口。
接著，可於半導體基底100之表面100a上之絕緣層116上形成金屬層117。金屬層117之材質可包括(但不限於)銅、鋁、金、鉑、鎳、錫、鈦、或前述之組合。在一實施例中，金 屬層117可包括鋁銅層(其可例如具有1.2μm之厚度)及晶種層。晶種層例如為鈦層或鈦鎢(TiW)層。金屬層117可延伸進入凹陷130b及/或凹陷130a。例如，在一實施例中，金屬層117可延伸於凹陷130b之側壁與底部上，且更進一步延伸於凹陷130a之側壁與底部上，如第1C圖所示。
接著，如第1D圖所示，將金屬層117圖案化以形成至少一導線層118。在一實施例中，導線層118可電性連接導電墊104a，且延伸於凹陷130b及/或凹陷130a之中。在一實施例中，複數個導線層118可分別電性連接對應的導電墊104a，並延伸於凹陷130a之底部上。
第2圖顯示根據本發明一實施例之晶片封裝體的上視圖，其中相同或相似之標號用以標示相同或相似之元件。第1D圖可相應於第2圖中之切線a-b處之剖面圖。如第2圖及第1D圖所示，導線層118可透過絕緣層116及介電層101之開口而電性接觸所露出之導電墊104a。雖然第2圖僅顯示出一導線層118，然更多的導線層118可形成於絕緣層116之上，且可分別電性連接對應的導電墊104a，並延伸於凹陷130a之底部上。在另一實施例中，半導體基底100可形成有其他不與凹陷130b及130a連通之其他凹陷，其中部分的導線層118亦可延伸進入其他凹陷之中。換言之，在其他實施例中，不同的導線層可能延伸進入不同的凹陷。
如第2圖及第1D圖所示，在一實施例中，可於半導體基底100之表面100a上之絕緣層116上形成金屬遮光層260a及/或金屬遮光層260b。或者，在其他實施例中，可形成更多 的金屬遮光層。金屬遮光層260a及/或金屬遮光層260b可不電性接觸導線層118。在一實施例中，金屬遮光層260a及/或金屬遮光層260b之位於表面100a上之投影可位於元件區102在表面100a上之投影與導電墊104a在表面100a上之投影之間。金屬遮光層260a及/或金屬遮光層260b可用以阻擋部分的外界光線照射元件區102，以避免影響元件區102之運作。在一實施例中，金屬遮光層260a及/或金屬遮光層260b可選擇性透過絕緣層116及介電層101之開口而電性接觸介電層101中之接地導電墊104G。
如第2圖所示，金屬遮光層260a或金屬遮光層260b之寬度通常較寬，因此容易具有較高的內應力而可能導致缺陷。在一實施例中，為了減輕金屬遮光層260a或金屬遮光層260b中之內應力，可於金屬遮光層260a或金屬遮光層260b中形成應力釋放圖案(stress release pattern)，其可例如為形成於金屬遮光層中之孔洞。
如第2圖及第1D圖所示，金屬遮光層260a或金屬遮光層260b可具有至少一孔洞262。在一實施例中，可透過圖案化製程移除部分的金屬遮光層260a或金屬遮光層260b以形成孔洞262。孔洞262例如可貫穿金屬遮光層260a。然本發明實施例不限於此。在其他實施例中，孔洞262未完全貫穿金屬遮光層260a。
在一實施例中，金屬遮光層260a可於形成導線層118之後，另以其他沉積製程及圖案化製程而形成於絕緣層116之上。或者，在其他實施例中，金屬遮光層260a可與導線層118 同時形成。例如，在一實施例中，金屬遮光層260a及導線層118可皆由圖案化金屬層117而形成。在此情形下，金屬遮光層260a之材質可相同於導線層118之材質。在一實施例中，金屬遮光層260a之厚度可相同於導線層118之厚度。在一實施例中，金屬遮光層260a、金屬遮光層260a中之孔洞262、及導線層118係同時形成。
第3圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖，其中相同或相似之標號用以標示相同或相似之元件。如第3圖所示，可提供容器302，並於其中注入蝕刻液304。接著，可提供複數個類似於第1C圖所示之半導體基底100，並可於半導體基底100之表面形成具有所需圖案之光阻層。接著，可於平台306設置複數個半導體基底100，並浸泡於蝕刻液304之中以將金屬層107圖案化為複數個導線層118及具有至少一孔洞262之至少一金屬遮光層260a。如此，可同時定義出數個半導體基底(或晶圓)上之導線層與金屬遮光層，可減少製程時間與成本。在一實施例中，可反覆升起平台306與放下平台306。即，可對半導體基底100進行反覆地蝕刻液浸泡以完成金屬層117之圖案化。
在一實施例中，金屬遮光層260a之孔洞262之形狀係設計為四邊形。因此，可較輕易地移除蝕刻液或蝕刻劑蝕刻金屬層117時所產生之氣泡，使金屬層117之圖案化可順利進行。在一實施例中，金屬遮光層260a中可形成有複數個孔洞262，且孔洞262之尺寸或形狀可彼此不同，如第2圖所示。然應注意的是，本發明實施例不限於此。在其他實施例中，金屬 遮光層260a之孔洞262的尺寸或形狀可大抵彼此相同。
例如，第4A及4B圖分別顯示根據本發明實施例之晶片封裝體的局部上視圖，其中相同或相似之標號用以標示相同或相似之元件。如第4A及4B圖所示，金屬遮光層260a之孔洞262的尺寸或形狀可大抵彼此相同，其可例如為長方形或具有至少一圓角之長方形。在其他實施例中，孔洞262之形狀可為其他四邊形，例如正方形、菱形、梯形、平行四邊形、或其他四邊形，且可(但不限於)皆分別具有至少一圓角。在一實施例中，金屬遮光層260a之孔洞262可大抵均勻分佈於金屬遮光層260a之中。應注意的是，本發明實施例不限於此。在其他實施例中，金屬遮光層260a之孔洞262的形狀可為三邊形、五邊形、六邊形、或七邊形。在一實施例中，金屬遮光層260a之孔洞262的形狀為非圓形且為邊數少於八邊之形狀。如此，可避免蝕刻金屬層117以形成孔洞262之過程中，蝕刻金屬層117所產生之氣泡附著於孔洞262而不易移除，影響孔洞262之形成。
接著，回到第1D圖，在一實施例中，可選擇性形成銲線204。銲線204可電性接觸延伸進入凹陷130b及/或凹陷130a中之導線層118。在一實施例中，銲線204可直接接觸這些凹陷中之最接近表面100b之最低凹陷(例如，凹陷130a)之底部正上方的導線層118。最低凹陷(例如，凹陷130a)之底部可大抵平行於表面100b。銲線204可用於使其他電子構件(例如，印刷電路板)之電性訊號透過導線層118而傳遞至晶片封裝體。接著，可沿著半導體基底100之預定切割道SC進行切割製程以形成至少一晶片封裝體。或者，在其他實施例中，可於形成銲線 204之前，進行半導體基底100之切割製程。
在本發明實施例中，透過堆疊晶片與將導線層導引至凹陷之中，可於有限空間之中，設置更多的導電線路，有助於晶片封裝體之縮小化。由於導線線路之傳遞距離減小，訊號傳遞速度可獲提升。此外，由於銲線形成於凹陷之中，可受到凹陷之保護而使晶片封裝體的可靠度提升。由於銲線係形成於凹陷之中，可使晶片封裝體之整體體積縮小。本發明實施例所形成之凹陷包括複數個相連通之凹陷，可使導線層於更為緩和之輪廓上沉積，可提升導線層之可靠度。本發明實施例所形成之金屬遮光層可避免光線影響元件區之運作，可提升效能。金屬遮光層之孔洞有助於釋放金屬遮光層中之應力以增進晶片封裝體的可靠度。透過金屬遮光層之孔洞的形狀設計，可使晶片封裝體之製作時間與製作成本顯著降低。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧元件區
104a、104G‧‧‧導電墊
116‧‧‧絕緣層
118‧‧‧導線層
130a、130b‧‧‧凹陷
260a、260b‧‧‧金屬遮光層
262‧‧‧孔洞

Claims (20)

  1. 一種晶片封裝體，包括：一半導體基底，具有一第一表面及一第二表面；一第一凹陷，自該第一表面朝該第二表面延伸；一第二凹陷，自該第一凹陷之一底部朝該第二表面延伸，其中該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入該第一凹陷及/或該第二凹陷；一絕緣層，位於該導線層與該半導體基底之間；以及一金屬遮光層，設置於該第一表面上，且具有至少一孔洞，其中該至少一孔洞之形狀為一四邊形。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該四邊形具有至少一圓角。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該四邊形為一長方形。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該至少一孔洞貫穿該金屬遮光層。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該金屬遮光層之材質相同於該導線層之材質。
  6. 如申請專利範圍第1項所述之晶片封裝體，其中該金屬遮光層之厚度相同於該導線層之厚度。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該至少 一孔洞包括複數個孔洞，且該些孔洞之尺寸或形狀彼此不同。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該至少一孔洞包括複數個孔洞，且該些孔洞之尺寸或形狀彼此大抵相同。
  9. 如申請專利範圍第8項所述之晶片封裝體，其中該些孔洞大抵均勻分佈於該金屬遮光層之中。
  10. 如申請專利範圍第1項所述之晶片封裝體，更包括：一介電層，位於該第一表面與該絕緣層之間；一元件區，形成於該半導體基底之中；以及複數個導電墊，位於該介電層之中，其中該導線層電性連接其中一該些導電墊。
  11. 如申請專利範圍第10項所述之晶片封裝體，其中該金屬遮光層在該第一表面上之一投影位於該元件區在該第一表面上之一投影與該些導電墊在該第一表面上之投影之間。
  12. 如申請專利範圍第10項所述之晶片封裝體，其中該金屬遮光層電性連接該介電層中之一接地導電墊。
  13. 如申請專利範圍第1項所述之晶片封裝體，更包括一銲線，電性接觸該第二凹陷之該第二底部正上方之該導線層。
  14. 如申請專利範圍第1項所述之晶片封裝體，其中該導線層不電性接觸該金屬遮光層。
  15. 一種晶片封裝體，包括： 一半導體基底，具有一第一表面及一第二表面；一第一凹陷，自該第一表面朝該第二表面延伸；一第二凹陷，自該第一凹陷之一底部朝該第二表面延伸，其中該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面；一導線層，設置於該第一表面上，且延伸進入該第一凹陷及/或該第二凹陷；一絕緣層，位於該導線層與該半導體基底之間；以及一金屬遮光層，設置於該第一表面上，且具有至少一孔洞，其中該至少一孔洞之形狀為一三邊形、一五邊形、一六邊形、或一七邊形。
  16. 一種晶片封裝體的形成方法，包括：提供至少一半導體基底，具有一第一表面及一第二表面；自該第一表面移除部分的該半導體基底以於該半導體基底之中形成一第一凹陷及一第二凹陷，其中該第一凹陷朝該第二表面延伸，而該第二凹陷自該第一凹陷之一底部朝該第二表面延伸；於該第一表面上形成一絕緣層，該絕緣層延伸進入該第一凹陷及該第二凹陷；於該絕緣層上形成一導線層，該導線層延伸進入該第一凹陷及/或該第二凹陷；於該絕緣層上形成一金屬遮光層，該金屬遮光層具有至 少一孔洞，其中該至少一孔洞之形狀為一四邊形；以及沿著該半導體基底之至少一預定切割道進行一切割製程以形成至少一晶片封裝體，其中在該切割製程之後，該第一凹陷之一側壁及該底部與該第二凹陷之一第二側壁及一第二底部共同形成該半導體基底之一外側表面。
  17. 如申請專利範圍第16項所述之晶片封裝體的形成方法，其中該金屬遮光層與該導線層係同時形成。
  18. 如申請專利範圍第16項所述之晶片封裝體的形成方法，其中該金屬遮光層與該導線層之形成步驟包括：於該絕緣層上形成一金屬層；以及將該金屬層圖案化以形成出該金屬遮光層及該導線層。
  19. 如申請專利範圍第18項所述之晶片封裝體的形成方法，其中提供該至少一半導體基底之步驟包括提供複數個半導體基底，且將該金屬層圖案化以形成出該金屬遮光層及該導線層之步驟包括：提供一容器；於該容器中注入一蝕刻液；以及將該些半導體基底放置於該蝕刻液之中蝕刻移除部分的該金屬層以形成該金屬遮光層及該導線層。
  20. 如申請專利範圍第19項所述之晶片封裝體的形成方法，其中該金屬遮光層、該金屬遮光層之該至少一孔洞、及該導線層係同時形成。
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