WO2017036381A1 - 封装结构及封装方法 - Google Patents

封装结构及封装方法 Download PDF

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Publication number
WO2017036381A1
WO2017036381A1 PCT/CN2016/097359 CN2016097359W WO2017036381A1 WO 2017036381 A1 WO2017036381 A1 WO 2017036381A1 CN 2016097359 W CN2016097359 W CN 2016097359W WO 2017036381 A1 WO2017036381 A1 WO 2017036381A1
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WO
WIPO (PCT)
Prior art keywords
layer
light shielding
material layer
wafer
cutting
Prior art date
Application number
PCT/CN2016/097359
Other languages
English (en)
French (fr)
Inventor
王之奇
洪方圆
Original Assignee
苏州晶方半导体科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201510552404.6A external-priority patent/CN105070734A/zh
Priority claimed from CN201520673730.8U external-priority patent/CN204991711U/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Priority to KR1020187007195A priority Critical patent/KR102070665B1/ko
Priority to US15/755,933 priority patent/US20180337206A1/en
Publication of WO2017036381A1 publication Critical patent/WO2017036381A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a package structure and a package method.
  • connection between an IC chip and an external circuit is achieved by means of metal wire bonding.
  • wire bonding technology is no longer applicable.
  • Wafer Level Chip Size Packaging is a technology that performs a package test on a whole wafer and then cuts a single finished chip.
  • the packaged chip size is consistent with the die.
  • Wafer-level chip packaging technology has overturned the traditional packaging such as Ceramic Leadless Chip Carrier and Organic Leadless Chip Carrier, which is becoming lighter and smaller in the market. Short, thin and low-cost requirements. Chips packaged by wafer level chip packaging technology are highly miniaturized, and chip cost is significantly reduced as the chip is reduced and the wafer size is increased.
  • Wafer-level chip packaging technology is a technology that can integrate IC design, wafer fabrication, package testing, and integration. It is a hot spot and development trend in the current packaging field.
  • the image sensor chip is a chip that can convert an optical image into an electrical signal, and has a sensing area.
  • Image sensor chip is packaged using existing wafer level chip packaging technology
  • an upper cover substrate is usually formed at the sensing area. The upper cover substrate can be retained after the wafer level chip package is completed, and the sensing area is continuously protected from damage and contamination during use of the image sensor chip.
  • the problem solved by the present invention is that the image sensor formed by the prior art has poor performance.
  • an embodiment of the present invention provides a package structure.
  • the package structure includes: a chip unit, a first surface of the chip unit includes a sensing area; an upper cover, a first surface of the upper cover has a support structure, and the upper cover covers the chip unit a surface, the support structure is located between the upper cover and the chip unit, and the sensing area is located within a cavity surrounded by the support structure and the first surface of the chip unit; a layer, the light shielding layer covering a second surface of the upper cover opposite to the first surface, and exposing an intermediate portion of the second surface that coincides with the sensing area in a light transmitting direction.
  • an area of the upper portion of the upper cover exposed by the light shielding layer is greater than or equal to an area of the sensing area.
  • the light shielding layer further covers a portion of the sidewall of the upper cover.
  • the material of the light shielding layer is a black photosensitive organic material having a thickness of 10 ⁇ m to 50 ⁇ m.
  • the material of the light shielding layer is metal and has a thickness of 1 ⁇ m to 10 ⁇ m.
  • the material of the light shielding layer is aluminum.
  • the surface of the metal is blackened.
  • the chip unit further includes: a solder pad located outside the sensing area; a through hole extending from the chip surface of the chip unit opposite to the first surface, the through hole Exposing the pad; an insulating layer covering the second surface of the chip unit and the sidewall surface of the via; a metal layer on the surface of the insulating layer and electrically connected to the pad; located in the metal layer and a solder resist layer on a surface of the insulating layer, the solder resist layer having an opening exposing a portion of the metal layer; and an external bump filling the opening and exposed outside the surface of the solder resist layer.
  • an embodiment of the present invention further provides a package method, including: providing a wafer to be packaged, the first surface of the wafer to be packaged includes a plurality of chip units and a chip unit a dicing area between the chip unit including a sensing area; providing a capping substrate, forming a plurality of supporting structures on the first surface of the capping substrate, the supporting structure and the sensing on the wafer to be packaged
  • the first surface of the capping substrate is oppositely coupled to the first surface of the wafer to be packaged, so that the supporting structure and the first surface of the wafer to be packaged are surrounded by a cavity.
  • a sensing region is located in the cavity; forming a light shielding material layer on a second surface of the capping substrate opposite to the first surface, the light shielding material layer having an opening corresponding to the sensing region;
  • the dicing area cuts the wafer to be packaged, the cover substrate and the light shielding material layer to form a plurality of package structures, the package structure includes the chip unit, and the package is cut by An upper cover plate formed by the substrate and a light shielding layer formed by cutting the light shielding material layer, the light shielding layer covering the second surface of the upper cover plate and exposing to coincide with the sensing area in the light transmission direction The middle area.
  • cutting the wafer to be packaged, the cover substrate and the light shielding material layer along the scribe line region comprises: performing a first cutting process, including from the scribe line region Forming a second surface of the package wafer opposite the first surface to form a first cutting trench until reaching a first surface of the wafer to be packaged; and performing a second cutting process, including cutting the light shielding material layer and The capping substrate forms a second dicing trench penetrating the first dicing trench and simultaneously forms a plurality of package structures.
  • cutting the wafer to be packaged, the cover substrate and the light shielding material layer along the scribe line region further comprises: performing a third cutting process before the second cutting process, a third cutting process is cut along the cutting path region from the second surface of the capping substrate to a predetermined depth to form a third cutting groove; when a light shielding material layer is formed on the second surface of the capping substrate The light shielding material layer covers the third cutting trench sidewall; the second cutting process cuts the light shielding material layer and the second cutting trench formed by the capping substrate penetrates the first cutting trench And a third cutting trench having a width smaller than a width of the third cutting trench, the light shielding layer further covering a sidewall of the upper cover after forming a plurality of package structures Upper area.
  • the light shielding material layer is a black photosensitive organic material
  • forming a light shielding material layer on the second surface of the cover substrate comprises: a process of spin coating, spraying or pasting on the cover substrate Forming a black photosensitive organic material layer on the surface; exposing and developing the black photosensitive organic material layer, forming an opening corresponding to the sensing region in the black photosensitive organic material layer; and the black photosensitive organic material layer Bake hard film.
  • the light shielding material layer is a metal
  • forming a light shielding material layer on the second surface of the capping substrate comprises: forming a metal material layer on the second surface of the capping substrate by using a sputtering process; Forming a patterned photoresist layer on the metal material layer, the imaged photoresist layer exposing a region of the metal material layer to be formed with an opening; using the patterned photoresist layer as a mask Etching the metal material layer until the second surface of the capping substrate is exposed to form an opening corresponding to the sensing region; and removing the patterned photoresist layer.
  • the encapsulating method further comprises: blackening the surface of the metal material layer with an acid-base solution.
  • the chip unit further includes a solder pad, the solder pad is located outside the sensing area, and when the first surface of the capping substrate is combined with the first surface of the wafer to be packaged,
  • the packaging method further includes: thinning a second surface opposite to the first surface of the wafer to be packaged; etching the wafer to be packaged from the second surface of the wafer to be packaged to form a pass a hole exposing a pad of the chip unit; a second surface of the wafer to be packaged and a sidewall of the through hole Forming an insulating layer; forming a metal layer connecting the pads on the surface of the insulating layer; forming a solder resist layer having an opening on the surface of the metal layer and the surface of the insulating layer, the opening exposing a surface of a portion of the metal layer; An external protrusion is formed on the surface of the solder resist layer, and the external protrusion fills the opening.
  • the package structure of the embodiment of the present invention includes a chip unit, an upper cover, and a light shielding layer on the second surface of the upper cover, the light shielding layer covers a peripheral area of the second surface of the upper cover, and is exposed The opposite intermediate region of the sensing region.
  • the light shielding layer in the package structure of the embodiment of the present invention can block light incident from a peripheral region of the second surface of the upper cover, the light being easily in the upper cover
  • the sidewall is reflected into the sensing region of the chip unit to interfere with the imaging of the sensing region. Since the light shielding layer of the embodiment of the invention reduces the interference light, the imaging quality of the package structure as the image sensor is improved.
  • the light shielding layer may further cover a part of the sidewall of the upper cover, further reducing interference light incident from the sidewall of the upper cover, and improving the package The imaging quality of the structure.
  • the encapsulation method of the embodiment of the present invention is used to form the above package structure, and has the above advantages.
  • FIG. 1 is a cross-sectional structural view showing a prior art image sensor chip
  • FIG. 2 is a cross-sectional structural view showing a package structure according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional structural view showing a package structure according to another embodiment of the present invention.
  • FIG. 4 to FIG. 11 are schematic diagrams showing the structure of an intermediate structure formed in a packaging method according to an embodiment of the present invention.
  • the inventors of the present invention have studied the process of packaging the image sensor chip by using the wafer level chip packaging technology in the prior art, and found that the performance of the image sensor formed by the prior art is poor because the chip package process is formed.
  • the upper cover substrate above the sensing area interferes with light entering the sensing area, reducing image quality.
  • FIG. 1 is a cross-sectional structural diagram of an image sensor chip formed by the prior art.
  • the image sensor chip includes: a substrate 10; a sensing region 20 on a first surface of the substrate 10; a solder pad 21 on a first surface of the substrate 10, on both sides of the sensing region 20; A second surface of the substrate 10 opposite to the first surface extends through a through hole (not labeled) of the substrate 10, the through hole exposing the pad 21; and the sidewall of the through hole and the lining An insulating layer 11 of the second surface of the bottom 10; a wiring layer 12 covering the bonding pad 21 and a portion of the insulating layer 11 from the second surface; and a solder resist layer 13 covering the wiring layer 12 and the insulating layer 11,
  • the solder resist layer 13 has an opening; a solder ball 14 electrically connected to the pad 21 through the circuit layer 12 in the opening of the solder resist layer 13; and a sensing area 20 around the first surface of the substrate 10 a cavity wall 31
  • the upper cover substrate 30 forms a cavity with the cavity wall 31 and the first surface of the substrate 10, so that the inductor 20 is located in the cavity to prevent the sensing area 20 from being contaminated and damaged during packaging and use. .
  • the upper cover substrate 30 has a relatively large thickness, for example 400 microns.
  • the inventors of the present invention have found that during the use of the image sensor chip described above, the light I1 is incident on the upper cover substrate 30 of the image sensor, and part of the light I2 entering the upper cover substrate 30 is irradiated to the side wall 30s of the upper cover substrate 30, resulting in the generation of the light beam I1.
  • the incident angle of the light ray I2 satisfies a specific condition, for example, when the upper cover substrate 30 is glass, the outside of the glass is air, and the When the incident angle of the light ray I2 is greater than the critical angle from the glass to the air, the light ray I2 is totally reflected at the side wall 30s of the upper cover substrate 30, and the total reflected light I2 propagates in the upper cover substrate 30. Until the illumination area 20 is illuminated, the sensing area 20 is severely disturbed. In the imaging process of the specific image sensor, the interference is reflected in the virtual image in the opposite direction of the total reflection light I2, which reduces the imaging quality.
  • a specific condition for example, when the upper cover substrate 30 is glass, the outside of the glass is air, and the When the incident angle of the light ray I2 is greater than the critical angle from the glass to the air, the light ray I2 is totally reflected at the side wall 30s of the upper cover substrate 30, and the total reflected light I2 propagates in the upper cover substrate 30. Until
  • an embodiment of the present invention provides a package structure and a package method for forming the package structure.
  • the package structure includes a chip unit, an upper cover, and a light shielding layer on a surface of the upper cover, the light shielding layer covers a peripheral area of the surface of the upper cover, and exposes an intermediate area opposite to the sensing area
  • the light entering the upper cover from the peripheral region of the upper cover surface can be blocked, thereby reducing the interference light entering the sensing area of the chip unit, and improving the imaging quality of the sensing area.
  • the packaging method for forming the above package structure also has the above advantages.
  • the package structure includes a chip unit 210 having a first surface 210a and a second surface 210b opposite to the first surface 210a.
  • the first surface 210a includes a sensing area 211, an upper cover plate 330, and the upper cover plate 330 includes a first surface 330a and a second surface 330b opposite to the first surface 330a, the first surface 330a having Support structure 320, and the upper cover plate 330 covers the core a first surface 210a of the sheet unit 210, the support structure 320 is located between the upper cover plate 330 and the chip unit 210, and the sensing area 211 is located at the support structure 320 and the chip unit 210 a surface surrounded by a surface 210a; and a light shielding layer 511 covering the second surface 330b of the upper cover 330 and exposed to the sensing region 211 in the light transmission direction The intermediate region of the coincident second surface 330b.
  • a light shielding layer 511 covering the second surface 330b of the upper cover
  • the material of the light shielding layer 511 is a black photosensitive organic material or a blackened metal, and has the characteristics of being opaque or low light transmission.
  • the light shielding layer 511 may be black rubber; the light shielding layer 511 may also be blackened aluminum, so that the light does not form specular reflection on the surface thereof, and the light shielding performance is good.
  • the light shielding layer 511 cannot enter the upper cover 330.
  • the package structure shown in FIG. 2 is the same as the image sensor of the prior art shown in FIG. 1 , and the same incident light I1 is incident on the upper cover substrate 330 of the image sensor in FIG. 1 . And reflecting at the side wall 30s of the upper cover substrate 330, entering the sensing area 20, and interfering with the imaging of the sensing area 20; and referring to FIG. 2, in the package structure of the embodiment of the invention, the upper cover substrate 330 is The peripheral area of the two surfaces 330b is covered by the light shielding layer 511. Since the light shielding layer 511 is opaque, the light ray I1 does not enter the upper cover 330, and thus does not interfere with the sensing area 211.
  • the area of the intermediate portion of the second surface 330b of the upper cover plate 330 exposed by the light shielding layer 511 of the embodiment of the present invention is greater than or equal to the area of the sensing region 211, from the second surface of the upper cover plate 330.
  • the light incident from the intermediate portion of 330b can enter the sensing region 211 from the upper cover 330, which reduces the interference of the light shielding layer 511 on the imaging quality of the sensing region 211.
  • the light shielding layer 511 also covers a partial region of the sidewall 330s between the first surface 330a and the second surface 330b of the upper cover plate 330. Compared with the light shielding layer shown in FIG. 2, as shown in FIG. 3, the light shielding covering the upper portion of the side wall 330s The layer 511 can further reduce the interference light I3 incident from the side wall 330s, further improving the imaging quality of the sensing area 211.
  • the height of the upper region of the side wall 330s of the upper cover 330 covered by the light shielding layer 511 is 1/5 to 4/5 of the thickness of the upper cover 330.
  • the shielding effect of the interference light incident from the side wall 330s is not good, and, in addition, from the side wall
  • the interference light incident at the bottom of the 330s is usually not able to reach the sensing area 211, so the height of the upper area of the side wall 330s covered by the light shielding layer 511 need not be too large.
  • an embodiment of the present invention provides a packaging method for forming a package structure as shown in FIG. 2 .
  • FIG. 4 to FIG. 11 are schematic diagrams showing an intermediate structure formed in a packaging process of a packaging method according to an embodiment of the present invention.
  • FIG. 4 is a schematic top view of the wafer to be packaged 200
  • FIG. 5 is a cross-sectional view along line AA1 of FIG.
  • the wafer to be packaged 200 has a first surface 200a and a second surface 200b opposite to the first surface 200a.
  • the first surface 200a of the wafer to be packaged 200 has a plurality of chip units 210 and a scribe line region 220 between the chip units 210.
  • the plurality of chip units 210 on the wafer to be packaged 200 are arranged in an array, and the scribe line region 220 is located between adjacent chip units 210, and subsequently along the scribe line region 220. Referring to the packaged wafer 200 for cutting, a plurality of chip package structures including the chip unit 210 may be formed.
  • the chip unit 210 is an image sensor chip unit, and the chip unit 210 has a sensing area 211 and a pad 212 outside the sensing area 211.
  • the sensing region 211 is an optical sensing region, for example, may be formed by a plurality of photodiode arrays, and the photodiode may convert an optical signal irradiated to the sensing region 211 into an electrical signal.
  • the pad 212 serves as an input and output terminal for the device in the sensing region 211 to be connected to an external circuit.
  • the chip unit 210 is formed on a silicon substrate, and the chip unit 210 may further include other functional devices formed in the silicon substrate.
  • a cover substrate 300 is provided, the cover substrate 300 including a first surface 300a and a second surface 300b opposite to the first surface 300a, at a first surface 300a of the cover substrate 300 A plurality of support structures 320 are formed, and the groove structure of the support structure 320 and the first surface 300a of the cover substrate 300 corresponds to the sensing area 211 on the wafer to be packaged 200.
  • the capping substrate 300 covers the first surface 200a of the wafer to be packaged 200 in a subsequent process for protecting the sensing region 211 on the wafer to be packaged 200. Since light is required to pass through the cover substrate 300 to reach the sensing region 211, the cover substrate 300 has high light transmittance and is a light transmissive material. Both surfaces 300a and 300b of the cover substrate 300 are flat and smooth, and do not cause scattering, diffuse reflection or the like on incident light.
  • the material of the capping substrate 300 may be inorganic glass, plexiglass or other light transmissive materials having specific strength.
  • the cover substrate 300 has a thickness of 300 ⁇ m to 500 ⁇ m, and may be, for example, 400 ⁇ m. If the thickness of the capping substrate 300 is too large, the thickness of the finally formed chip package structure is too large, which cannot meet the requirement of thinning and lightening of the electronic product; if the thickness of the capping substrate 300 is too small, it may result in The cover substrate 300 has a small strength and is easily damaged, and cannot sufficiently protect the sensing area covered subsequently.
  • the support structure 320 is formed by etching after depositing a layer of support structure material on the first surface 300a of the capping substrate 300. Specifically, a support structural material layer (not shown) covering the first surface 300a of the capping substrate 300 is first formed, and then the support structure is The material layer is patterned to form the support structure 320 after removing a portion of the support structure material layer.
  • the sensing region 211 may be located in a recess surrounded by the support structure 320 and the first surface 300a of the cover substrate 300 after a subsequent bonding process.
  • the material of the support structure material layer is a wet film or a dry film photoresist, which is formed by a process such as spraying, spin coating or pasting, and the support structure material layer is exposed and developed for patterning.
  • the support structure 320 is then formed.
  • the support structure material layer may also be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc., formed by a deposition process, and then patterned by photolithography and etching processes to form the support. Structure 320.
  • the support structure 320 can also be formed by etching the capping substrate 300. Specifically, a patterned photoresist layer may be formed on the capping substrate 300, and then the capping substrate 300 is etched by using the patterned photoresist layer as a mask. The support structure 320 is formed in the substrate 300, and the support structure 320 is a convex portion on the first surface 300a of the cover substrate 300.
  • the first surface 300 a of the capping substrate 300 is opposite to and coupled to the first surface 200 a of the wafer 200 to be packaged, so that the supporting structure 320 and the wafer to be packaged 200 are
  • the first surface 200a encloses a cavity (not labeled), and the sensing region 211 is located within the cavity.
  • the capping substrate 300 and the wafer to be packaged 200 are bonded by an adhesive layer (not shown).
  • an adhesive layer for example, a process of spraying, spin coating or pasting on the top surface of the support structure 320 of the first surface 300a of the capping substrate 300, and/or the first surface 200a of the wafer 200 to be packaged
  • the adhesive layer is formed, and the first surface 300a of the capping substrate 300 is pressed against the first surface 200a of the wafer to be packaged 200, and bonded through the adhesive layer.
  • the adhesive layer can achieve both bonding and insulation and sealing.
  • the adhesive layer can It is considered to be a polymer bonding material such as a polymer material such as silica gel, epoxy resin or benzocyclobutene.
  • the support structure 320 and the first to be packaged wafer 200 are Surface 200a encloses a cavity.
  • the position of the cavity corresponds to the position of the sensing area 211, and the cavity area is slightly larger than the area of the sensing area 211, such that the sensing area 211 is located within the cavity.
  • the pad 212 on the wafer to be packaged 200 is covered by the supporting structure 320 on the capping substrate 300.
  • the capping substrate 300 can function to protect the wafer to be packaged 200 in a subsequent process.
  • the package to be packaged 200 is subjected to a packaging process.
  • the wafer to be packaged 200 is thinned from the second surface 200b of the wafer to be packaged 200 to facilitate etching of the subsequent via, and the thinning of the wafer to be packaged 200 is performed.
  • a mechanical polishing, a chemical mechanical polishing process, or the like may be employed; then, the wafer to be packaged 200 is etched from the second surface 200b of the wafer 200 to be packaged to form a via (not labeled), the through hole Exposing the pad 212 on the first surface 200a side of the wafer to be packaged 200; then, forming an insulating layer 213 on the second surface 200b of the wafer to be packaged 200 and the sidewall of the through hole, The insulating layer 213 exposes the pad 212 at the bottom of the via hole.
  • the insulating layer 213 may provide electrical insulation for the second surface 200b of the wafer to be packaged 200, and may also be exposed by the through hole.
  • the substrate of the wafer to be packaged 200 is electrically insulated, and the material of the insulating layer 213 may be silicon oxide, silicon nitride, silicon oxynitride or an insulating resin; then, a connection is formed on the surface of the insulating layer 213.
  • the metal layer 214 can be used as a rewiring layer Leading the pad 212 to the second surface 200b of the wafer to be packaged 200, and then connecting with an external circuit, the metal layer 214 is formed by metal film deposition and etching of the metal film; then, Forming a solder resist layer 215 having an opening (not labeled) on the surface of the metal layer 214 and the surface of the insulating layer 213, the opening exposing a portion of the surface of the metal layer 214, the solder resist layer 215 Material is oxidized An insulating dielectric material such as silicon or silicon nitride is used to protect the metal layer 214; then, an external protrusion 216 is formed on the surface of the solder resist layer 215, and the external protrusion 216 fills the opening.
  • the external protrusion 216 may be a connection structure such as a solder ball or a metal pillar, and the material may be a metal material such as copper, aluminum, gold, t
  • the chip package structure obtained by the subsequent cutting may be connected to the external circuit through the external protrusion 216.
  • the optical signal is converted into an electrical signal by the sensing region 211 of the chip unit, the electrical signal may be sequentially transmitted through the pad 212, the metal layer 214, and the external bump 216 to an external circuit for processing.
  • a light shielding material layer 510 having a plurality of openings 520 corresponding to the sensing regions 211 is formed on the second surface 300b of the capping substrate 300.
  • the area of the opening 520 is greater than or equal to the area of the sensing area 211, and is used to expose the sensing area 211 after the package structure is subsequently formed.
  • the light shielding material layer 510 is a black organic material that is opaque or low in light transmittance, such as black glue.
  • the black organic material is a photosensitive material, which can be patterned by a photolithography process.
  • the method of forming the light shielding material layer 510 includes: forming a black photosensitive organic material layer on the second surface 300b of the capping substrate 300 by spin coating, spraying or pasting; according to the black photosensitive organic Positive and negative development characteristics of the material, exposing the area of the black photosensitive organic material layer to be formed with the opening 520, or exposing a region other than the opening 520, and developing, forming in the black photosensitive organic material layer a plurality of openings 520 corresponding to the sensing regions; finally, baking the black photosensitive organic material layer to enhance mechanical strength of the black photosensitive organic material layer and adhesion to the capping substrate 300 Attached.
  • the black photosensitive organic material has a thickness of 10 ⁇ m to 50 ⁇ m, preferably 15
  • the light shielding material layer 510 is formed of black rubber, since the black rubber is an organic material, it is difficult to do It is completely opaque. A better shading effect can be achieved by appropriately increasing the thickness of the black rubber material layer. However, the greater the thickness of the black rubber material layer, the more difficult it is for the light to penetrate the black rubber material layer to the bottom during the exposure process. The bottom of the layer of vinyl material cannot be completely exposed, which increases the difficulty of development and affects the resolution of the formed pattern; in addition, as a organic substance, the black plastic material is easy to generate particles and contaminate the chip during exposure and development. Causes poor light transmission.
  • the light shielding material layer 510 may also be a metal, which may be blackened so that the light does not form a specular reflection on its surface.
  • the metal may be aluminum, an aluminum alloy or other suitable metallic material.
  • the method of forming the light shielding material layer 510 includes: forming a metal material layer on the second surface 300b of the capping substrate 300 by a sputtering process.
  • the metal material layer is an aluminum material layer.
  • the metal material layer is blackened by an acid-base syrup, for example, the aluminum material layer may be treated with a sulfur-containing alkali solution to form a black sulfide film layer on the aluminum material layer.
  • the blackened metal material layer has a thickness of from 1 ⁇ m to 10 ⁇ m, preferably, may be 5 ⁇ m, 6 ⁇ m, or the like.
  • forming the light shielding material layer 510 on the second surface 300b of the capping substrate 300 may also be before the capping substrate 300 is combined with the wafer to be packaged 200.
  • the invention may be omitted after the subsequent first cutting process, and may be selected according to specific process conditions.
  • the wafer to be packaged 200, the capping substrate 300, and the light shielding material layer 510 are along the dicing street region 220 of the wafer to be packaged 200 (see also FIG. 5).
  • the cutting is performed to form a plurality of package structures as shown in FIG.
  • the package structure includes a chip unit 210; an upper cover plate 330 formed by cutting the cover substrate 300 on the chip unit 210, and a light shielding layer 511 formed by cutting the light shielding material layer 510, the light shielding Layer 511 covers second surface 330b of upper cover plate 330 and exposes an intermediate region of second surface 330b opposite said sensing region 211.
  • the cutting of the wafer to be packaged 200, the capping substrate 300, and the light shielding material layer 510 includes a first cutting process and a second cutting process.
  • a first cutting process is performed, which starts cutting from the second surface 200b of the wafer to be packaged 200 along the dicing street region 220 as shown in FIG.
  • the first surface 200a of the wafer to be packaged 200 forms a first cutting trench 410.
  • the first cutting process may be performed by a slicing knife or a laser cutting, and the slicing knife cutting may be a metal knife or a resin knife.
  • a second cutting process is performed, starting from the light shielding material layer 510 along a region corresponding to the dicing street region 220 described in FIG. 5, for the light shielding material layer 510 and the The cover substrate 300 is cut until reaching the first surface 200a of the wafer to be packaged 200, forming a second cutting trench 420 penetrating the first cutting trench 410, and simultaneously forming a plurality of package structures, thereby completing the cutting Process.
  • the second cutting process may also use a slicing knife or a laser cutting.
  • the second cutting process may also cut the capping substrate 300 and the light shielding material layer 510 from the first surface 300a of the capping substrate 300 along the first cutting trench 410. The cutting is completed through the second cutting groove 420 of the capping substrate 300 and the light shielding material layer 510.
  • the first cutting process is performed before the second cutting process, and in some other embodiments, the first cutting process may also be performed after the second cutting process.
  • the invention is not limited thereto.
  • FIG. 12 to FIG. 15 are structural diagrams of a packaging process for forming the package structure shown in FIG. 3 according to another embodiment of the present invention.
  • a wafer 200 to be packaged is provided.
  • the first surface 200 a of the wafer to be packaged 200 includes a plurality of chip units 210 and is located at the chip unit 210 .
  • the chip unit includes a sensing region 211; a cover substrate 300 is provided, and a plurality of support structures 320 are formed on the first surface 300a of the cover substrate 300, the support structure 320 and the The sensing area 211 on the packaged wafer 200 corresponds to; the first surface 300a of the cover substrate 300 is oppositely coupled to the first surface 200a of the wafer to be packaged 200, such that the support structure 320 and the The first surface 200a of the wafer to be packaged 200 encloses a cavity, and the sensing region 211 is located within the cavity.
  • a first cutting process is performed.
  • the first cutting process is cut from the second surface 200b of the wafer to be packaged 200 along the dicing street region 220 as shown in FIG. 5 until the first surface 200a of the wafer to be packaged 200 reaches the first surface 200a.
  • the trench 410 is cut.
  • a third cutting process is performed, which is cut from the second surface 300b of the capping substrate 300 along the dicing street region 220 as shown in FIG. 5 to a predetermined depth to form a Three cutting grooves 430.
  • the third cutting trench 430 is located within the capping substrate 300.
  • the width of the third cutting trench 430 is greater than the width of the first dicing trench 410 and the subsequently formed second dicing trench so that a subsequent opaque material layer can be formed within the third trench 430.
  • the process of forming the third cutting groove 430 may be bit grinding, sheet cutting or laser cutting.
  • a light shielding material is formed on the second surface 300b of the capping substrate 300.
  • the layer 510 has a plurality of openings 520 corresponding to the sensing regions 211.
  • the light shielding material layer 510 also covers the sidewalls and the bottom surface of the third cutting trench 430, so that after the cutting is completed, the light shielding material layer 510 is further It can cover part of the side wall of the upper cover.
  • the material of the light shielding material layer 510 may be a black photosensitive organic material or a metal.
  • a second cutting process is performed, starting from the light shielding material layer 510 along a region corresponding to the dicing street region 220 described in FIG. 5, for the light shielding material layer 510 and the
  • the cover substrate 300 is cut until reaching the first surface 200a of the wafer to be packaged 200, forming a second cutting trench 420 penetrating the first cutting trench 410 and the third cutting trench 430, and forming a plurality of A package structure to complete the cutting process.
  • the width of the second cutting trench 420 is smaller than the width of the third cutting trench 430 to reduce damage to the light shielding material layer 510 on the sidewall surface of the third cutting trench 430.
  • the light shielding material layer 510 of the sidewall surface of the third cutting trench 430 is left in the formed package structure. Therefore, referring to FIG. 3, in the finally formed package structure, the light shielding layer 511 formed by cutting the light shielding material layer 510 also covers the upper region of the side wall of the upper cover plate 330. In some embodiments, the height of the upper region of the sidewall of the upper cover 330 covered by the light shielding layer 511 is 1/5 to 4/5 of the thickness of the upper cover 330.
  • the first cutting process is performed before the third cutting process and the second cutting process, and in other embodiments, the first cutting process may also be performed in the Executing after the third cutting process and the second cutting process may also be performed between the third cutting process and the second cutting process.

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Abstract

一种封装结构和封装方法，封装结构包括：芯片单元（210），芯片单元的第一表面（210a）包括感应区域（211）；上盖板（330），上盖板的第一表面（330a）具有支撑结构（320），上盖板覆盖芯片单元的第一表面，支撑结构位于上盖板和芯片单元之间，感应区域位于支撑结构和芯片单元的第一表面围成的空腔之内；遮光层，遮光层覆盖在上盖板的第一表面相对的第二表面（330b）上，并暴露出第二表面在透光方向与感应区域重合的中间区域。该封装结构和封装方法可以减少入射至感应区域的干扰光线。

Description

封装结构及封装方法
本申请要求于2015年9月2日提交中国专利局,申请号201510552404.6,发明名称为“封装结构及封装方法”的中国专利申请的优先权，以及于2015年9月2日提交中国专利局，申请号为201520673730.8，发明名称为“封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种封装结构和一种封装方法。
背景技术
传统技术上，IC芯片与外部电路的连接是通过金属引线键合(Wire Bonding)的方式实现。随着IC芯片特征尺寸的缩小和集成电路规模的扩大，引线键合技术不再适用。
晶圆级芯片封装(Wafer Level Chip size Packaging，WLCSP)技术是对整片晶圆进行封装测试后再切割得到单个成品芯片的技术，封装后的芯片尺寸与裸片一致。晶圆级芯片封装技术颠覆了传统封装如陶瓷无引线芯片载具(Ceramic Leadless Chip Carrier)、有机无引线芯片载具(Organic Leadless Chip Carrier)的模式，顺应了市场对微电子产品日益轻、小、短、薄化和低价化要求。经晶圆级芯片封装技术封装后的芯片达到了高度微型化，芯片成本随着芯片的减小和晶圆尺寸的增大而显著降低。晶圆级芯片封装技术是可以将IC设计、晶圆制造、封装测试、整合为一体的技术，是当前封装领域的热点和发展趋势。
影像传感器芯片作为一种可以将光学图像转换成电子信号的芯片，其具有感应区域。当利用现有的晶圆级芯片封装技术对影像传感器芯片进行封装 时，为了在封装过程中保护上述的感应区域不受损伤和污染，通常会在感应区域位置形成一个上盖基板。所述上盖基板在完成晶圆级芯片封装后，可以继续保留，在影像传感器芯片的使用过程中继续保护感应区域免受损伤和污染。
但是，采用上述晶圆级芯片封装技术形成的影像传感器性能不佳。
发明内容
本发明解决的问题是现有技术形成的影像传感器性能不佳。
为解决上述问题，本发明实施例提供了一种封装结构。所述封装结构包括：芯片单元，所述芯片单元的第一表面包括感应区域；上盖板，所述上盖板的第一表面具有支撑结构，所述上盖板覆盖所述芯片单元的第一表面，所述支撑结构位于所述上盖板和所述芯片单元之间，且所述感应区域位于所述支撑结构和所述芯片单元的第一表面围成的空腔之内；以及遮光层，所述遮光层覆盖在所述上盖板的与第一表面相对的第二表面上，并暴露出第二表面在透光方向上与所述感应区域重合的中间区域。
可选地，所述遮光层暴露出的所述上盖板中间区域的面积大于或者等于所述感应区域的面积。
可选地，所述遮光层还覆盖所述上盖板的部分侧壁。
可选地，所述遮光层的材料为黑色光敏有机材料，厚度为10μm～50μm。
可选地，所述遮光层的材料为金属，厚度为1μm～10μm。
可选地，所述遮光层的材料为铝。
可选地，所述金属的表面经过黑化处理。
可选地，所述芯片单元还包括：位于所述感应区域外的焊垫；从所述芯片单元的与第一表面相对的第二表面贯穿所述芯片单元的通孔，所述通孔暴 露出所述焊垫；覆盖所述芯片单元第二表面和所述通孔侧壁表面的绝缘层；位于所述绝缘层表面且与所述焊垫电连接的金属层；位于所述金属层和所述绝缘层表面的阻焊层，所述阻焊层具有暴露出部分所述金属层的开孔；填充所述开孔，并暴露在所述阻焊层表面之外的外接凸起。
对应于上述的封装结构，本发明实施例还提供了一种封装方法，所述封装方法包括：提供待封装晶圆，所述待封装晶圆的第一表面包括多个芯片单元和位于芯片单元之间的切割道区域，所述芯片单元包括感应区域；提供封盖基板，在所述封盖基板的第一表面形成多个支撑结构，所述支撑结构与所述待封装晶圆上的感应区域相对应；将所述封盖基板的第一表面与所述待封装晶圆的第一表面相对结合，使得所述支撑结构与所述待封装晶圆的第一表面围成空腔，所述感应区域位于所述空腔内；在所述封盖基板的与第一表面相对的第二表面上形成遮光材料层，所述遮光材料层具有与所述感应区域对应的开口；沿所述切割道区域对所述待封装晶圆、所述封盖基板和所述遮光材料层进行切割，形成多个封装结构，所述封装结构包括所述芯片单元、由切割所述封盖基板形成的上盖板和由切割所述遮光材料层形成的遮光层，所述遮光层覆盖在所述上盖板的第二表面上，并暴露出在透光方向上与所述感应区域重合的中间区域。
可选地，沿所述切割道区域对所述待封装晶圆、所述封盖基板和所述遮光材料层进行切割包括：执行第一切割工艺，包括沿所述切割道区域从所述待封装晶圆的与第一表面相对的第二表面开始切割，直至到达所述待封装晶圆的第一表面形成第一切割沟槽；以及执行第二切割工艺，包括切割所述遮光材料层和所述封盖基板，形成与所述第一切割沟槽贯通的第二切割沟槽，同时形成多个封装结构。
可选地，沿所述切割道区域对所述待封装晶圆、所述封盖基板和所述遮光材料层进行切割还包括：在所述第二切割工艺前执行第三切割工艺，所述 第三切割工艺沿所述切割道区域从所述封盖基板的第二表面开始切割到达预设深度，形成第三切割沟槽；在所述封盖基板的第二表面上形成遮光材料层时，所述遮光材料层覆盖所述第三切割沟槽侧壁；所述第二切割工艺切割所述遮光材料层和所述封盖基板形成的第二切割沟槽贯通所述第一切割沟槽和第三切割沟槽，所述第二切割沟槽的宽度小于所述第三切割沟槽的宽度，在形成多个封装结构后，所述遮光层还覆盖所述上盖板的侧壁的上部区域。
可选地，所述遮光材料层为黑色光敏有机材料，在所述封盖基板的第二表面上形成遮光材料层包括：采用旋涂、喷涂或者黏贴的工艺在所述封盖基板的第二表面上形成黑色光敏有机材料层；对所述黑色光敏有机材料层进行曝光和显影，在所述黑色光敏有机材料层内形成与所述感应区域对应的开口；对所述黑色光敏有机材料层进行烘烤坚膜。
可选地，所述遮光材料层为金属，在所述封盖基板的第二表面上形成遮光材料层包括：采用溅射工艺在所述封盖基板的第二表面上形成金属材料层；在所述金属材料层上形成图形化的光刻胶层，所述图像化的光刻胶层暴露出所述金属材料层待形成开口的区域；以所述图形化的光刻胶层为掩膜，刻蚀所述金属材料层，直至暴露出所述封盖基板的第二表面，形成与所述感应区域对应的开口；去除所述图形化的光刻胶层。
可选地，所述封装方法还包括：采用酸碱溶液对所述金属材料层的表面进行黑化处理。
可选地，所述芯片单元还包括焊垫，所述焊垫位于所述感应区域外，当将所述封盖基板的第一表面与所述待封装晶圆的第一表面相结合后，所述封装方法还包括：从所述待封装晶圆的与第一表面相对的第二表面进行减薄；从所述待封装晶圆的第二表面刻蚀所述待封装晶圆，形成通孔，所述通孔暴露出所述芯片单元的焊垫；在所述待封装晶圆的第二表面以及通孔的侧壁表 面形成绝缘层；在所述绝缘层表面形成连接焊垫的金属层；在所述金属层表面以及绝缘层表面形成具有开孔的阻焊层，所述开孔暴露出部分金属层表面；在所述阻焊层表面上形成外接凸起，所述外接凸起填充所述开孔。
与现有技术相比，本发明实施例的技术方案具有以下优点：
本发明实施例的封装结构包括芯片单元、上盖板和位于所述上盖板第二表面上的遮光层，所述遮光层覆盖所述上盖板第二表面的外围区域，并暴露出与所述感应区域相对的中间区域。与现有技术的封装结构相比，本发明实施例封装结构中的遮光层可以阻挡从所述上盖板第二表面的外围区域入射的光线，所述光线容易在在所述上盖板的侧壁发生反射进入芯片单元的感应区域，从而干扰所述感应区域的成像，由于本发明实施例的遮光层减少了上述的干扰光线，因此提高了作为影像传感器的封装结构的成像质量。
进一步地，本发明实施例的封装结构中，所述遮光层还可以覆盖所述上盖板的部分侧壁，进一步减少了从所述上盖板侧壁入射的干扰光线，提高了所述封装结构的成像质量。
对应地，本发明实施例的封装方法用于形成上述的封装结构，也具有上述的优点。
附图说明
图1示出了现有技术的影像传感器芯片的剖面结构示意图；
图2示出了本发明一实施例的封装结构的剖面结构示意图；
图3示出了本发明另一实施例的封装结构的剖面结构示意图；
图4至图11示出了本发明一实施例的封装方法中所形成的中间结构的结构示意图；
图12至图15示出了本发明另一实施例的封装方法中所形成的中间结构 的结构示意图。
具体实施方式
由背景技术可知，现有技术形成的影像传感器的性能不佳。
本发明的发明人对现有技术采用晶圆级芯片封装技术对影像传感器芯片进行封装的工艺进行了研究，发现现有技术形成的影像传感器的性能不佳的原因在于，在芯片封装过程中形成于感应区域之上的上盖基板会对进入感应区域的光线产生干扰，降低成像质量。
具体地，参考图1，图1示出了现有技术形成的影像传感器芯片的剖面结构示意图。所述影像传感器芯片包括：衬底10；位于所述衬底10第一表面的感应区域20；位于所述衬底10第一表面，所述感应区域20两侧的焊垫21；从所述衬底10的与所述第一表面相对的第二表面贯穿所述衬底10的通孔(未标示)，所述通孔暴露出所述焊垫21；位于所述通孔侧壁及衬底10第二表面的绝缘层11；从所述第二表面覆盖所述焊垫21及部分绝缘层11的线路层12；覆盖所述线路层12和绝缘层11的阻焊层13，所述阻焊层13具有开口；位于所述阻焊层13开口内通过所述线路层12与所述焊垫21电连接的焊球14；位于所述衬底10第一表面的感应区域20周围的空腔壁31；以及位于所述空腔壁上的上盖基板30。所述上盖基板30与空腔壁31以及衬底10的第一表面构成空腔，使得所述感应器20位于所述空腔内，避免感应区20在封装和使用过程中受到污染和损伤。通常所述上盖基板30的厚度较大，例如400微米。
本发明的发明人发现，在上述的影像传感器芯片的使用过程中，光线I1入射影像传感器的上盖基板30，进入上盖基板30的部分光线I2会照射至上盖基板30的侧壁30s，产生折射和反射现象，反射光线如果入射至所述感应区域20，就会对影像传感器的成像造成干扰。尤其是，如果光线I2的入射角度满足特定条件，例如，当所述上盖基板30为玻璃，玻璃外为空气，而所述 光线I2的入射角大于由玻璃到空气的临界角时，所述光线I2会在所述上盖基板30的侧壁30s处发生全反射，全反射光线I2在所述上盖基板30内传播，直至照射至所述感应区域20，会对所述感应区域20造成严重干扰。在具体影像传感器的成像过程中，所述干扰体现为在全反射光线I2光路的反方向上构成虚像，降低了成像质量。
此外，随着晶圆级芯片封装的微型化趋势，晶圆级芯片上集成的传感器芯片的封装体越多，单个成品芯片封装体的尺寸越小，上盖基板30的侧壁与感应区20边缘的距离也越来越近，上述的干扰现象也更为明显。
基于以上研究，本发明实施例提供了一种封装结构和形成所述封装结构的封装方法。所述封装结构包括芯片单元、上盖板和位于所述上盖板表面的遮光层，所述遮光层覆盖所述上盖板表面的外围区域，并暴露出与所述感应区域相对的中间区域，可以阻挡从所述上盖板表面的外围区域入射所述上盖板的光线，从而减少了进入芯片单元感应区域的干扰光线，提高了感应区域的成像质量。对应地，形成上述封装结构的封装方法也具有以上优点。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
需要说明的是，提供这些附图的目的是有助于理解本发明的实施例，而不应解释为对本发明的不当的限制。为了更清楚起见，图中所示尺寸并未按比例绘制，可能会做放大、缩小或其他改变。
首先，本发明实施例提供了一种封装结构，参考图2，所述封装结构包括芯片单元210，所述芯片单元210具有第一表面210a和与所述第一表面210a相对的第二表面210b，所述第一表面210a包括感应区域211；上盖板330，所述上盖板330包括第一表面330a和与所述第一表面330a相对的第二表面330b，所述第一表面330a具有支撑结构320，且所述上盖板330覆盖所述芯 片单元210的第一表面210a，所述支撑结构320位于所述上盖板330和所述芯片单元210之间，且所述感应区域211位于所述支撑结构320和所述芯片单元210的第一表面210a围成的空腔之内；以及遮光层511，所述遮光层511覆盖在所述上盖板330的第二表面330b上，并暴露出与所述感应区域211在透光方向上重合的第二表面330b中间区域。在一些实施例中，所述遮光层511暴露出的所述上盖板330第二表面330b中间区域的面积与所述感应区域211的面积相等或者大于所述感应区域211的面积。
本发明实施例中，所述遮光层511的材料为黑色光敏有机材料或者经过黑化处理的金属，具有不透光或者低透光的特性。例如，所述遮光层511可以为黑胶；所述遮光层511还可以为经过黑化处理的铝，使得光线在其表面不能形成镜面反射，遮光性能好。当光线入射至所述遮光层511表面时，不能穿过所述遮光层511进入所述上盖板330。
本发明实施例图2所示的封装结构与图1所示的现有技术的影像传感器相比，相同的入射光线I1，在图1中，会射入所述影像传感器的上盖基板330，并在上述上盖基板330的侧壁30s处发生反射，进入感应区域20，干扰感应区域20的成像；而参考图2，在本发明实施例的封装结构中，所述上盖基板330的第二表面330b的外围区域被所述遮光层511覆盖，由于所述遮光层511不透光，所述光线I1不会进入所述上盖板330，也就不会对感应区域211产生干扰。此外，本发明实施例的所述遮光层511暴露出的所述上盖板330第二表面330b中间区域的面积大于或等于所述感应区域211的面积，从所述上盖板330第二表面330b中间区域入射的光线可以从所述上盖板330进入感应区域211，减小了所述遮光层511对感应区域211成像质量的干扰。
进一步地，在其他一些实施例中，参考图3，所述遮光层511还覆盖了所述上盖板330的第一表面330a和第二表面330b之间的侧壁330s的部分区域。与图2所示的遮光层相比，如图3所示，覆盖所述侧壁330s上部区域的遮光 层511可以进一步减少从所述侧壁330s入射的干扰光线I3，进一步提高了所述感应区域211的成像质量。所述遮光层511覆盖的所述上盖板330侧壁330s的上部区域的高度为所述上盖板330厚度的1/5～4/5。若所述遮光层511覆盖所述上盖板330侧壁330s的上部区域的高度过小，则对从所述侧壁330s入射的干扰光线的遮挡效果不佳，另外，由于从所述侧壁330s的底部入射的干扰光线通常不能到达所述感应区域211，因此所述遮光层511覆盖所述侧壁330s的上部区域的高度也无需过大。
对应地，本发明实施例提供了一种封装方法，用于形成如图2所示的封装结构。请参考图4至图11，为本发明实施例的封装方法的封装过程中形成的中间结构示意图。
首先，参考图4和5，提供待封装晶圆200，其中，图4为所述待封装晶圆200的俯视结构示意图，图5为图4沿AA1的剖视图。
所述待封装晶圆200具有第一表面200a和与所述第一表面200a相对的第二表面200b。所述待封装晶圆200的第一表面200a上具有多个芯片单元210和位于所述芯片单元210之间的切割道区域220。
本实施例中，所述待封装晶圆200上的多个芯片单元210呈阵列排布，所述切割道区域220位于相邻的芯片单元210之间，后续沿所述切割道区域220对所述待封装晶圆200进行切割，可以形成多个包括所述芯片单元210的芯片封装结构。
本实施例中，所述芯片单元210为图像传感器芯片单元，所述芯片单元210具有感应区211和位于所述感应区域211之外的焊垫212。所述感应区域211为光学感应区，例如，可以由多个光电二极管阵列排布形成，所述光电二极管可以将照射至所述感应区域211的光学信号转化为电学信号。所述焊垫212作为所述感应区域211内器件与外部电路连接的输入和输出端。在一些实 施例中，所述芯片单元210形成于硅衬底上，所述芯片单元210还可以包括形成于硅衬底内的其他功能器件。
需要说明的是，在本发明实施例的封装方法的后续步骤中，为了简单明了起见，仅以图4所示的沿所述待封装晶圆200的AA1方向的截面图为例进行说明，在其他区域执行相似的工艺步骤。
接着，参考图6，提供封盖基板300，所述封盖基板300包括第一表面300a以及与所述第一表面300a相对的第二表面300b，在所述封盖基板300的第一表面300a形成多个支撑结构320，所述支撑结构320与所述封盖基板300的第一表面300a围成的凹槽结构与所述待封装晶圆200上的感应区域211相对应。
本实施例中，所述封盖基板300在后续工艺中覆盖所述待封装晶圆200的第一表面200a，用于对所述待封装晶圆200上的感应区域211进行保护。由于需要光线透过所述封盖基板300到达感应区域211，因此，所述封盖基板300具有较高的透光性，为透光材料。所述封盖基板300的两个表面300a和300b均平整、光滑，不会对入射光线产生散射、漫反射等。
具体地，所述封盖基板300的材料可以为无机玻璃、有机玻璃或者其他具有特定强度的透光材料。本实施例中，所述封盖基板300的厚度为300μm～500μm，例如，可以为400μm。如果所述封盖基板300的厚度过大，会导致最终形成的芯片封装结构的厚度过大，不能满足电子产品薄轻化的需求；如果所述封盖基板300的厚度过小，则会导致封盖基板300的强度较小，容易损伤，不能对后续所覆盖的感应区域起到足够的保护作用。
在一些实施例中，所述支撑结构320通过在所述封盖基板300的第一表面300a上沉积支撑结构材料层后刻蚀形成。具体地，首先形成覆盖所述封盖基板300第一表面300a的支撑结构材料层(未示出)，接着对所述支撑结构 材料层进行图形化，去除部分所述支撑结构材料层后，形成所述支撑结构320。所述支撑结构320与所述封盖基板300的第一表面300a围成的凹槽结构在所述封盖基板300上的位置与所述感应区域211在所述待封装晶圆200上位置相对应，从而使得在后续的结合工艺后，所述感应区域211可以位于所述支撑结构320与所述封盖基板300的第一表面300a围成的凹槽内。在一些实施例中，所述支撑结构材料层的材料为湿膜或干膜光刻胶，通过喷涂、旋涂或者黏贴等工艺形成，对所述支撑结构材料层进行曝光和显影进行图形化后形成所述支撑结构320。在一些实施例中，所述支撑结构材料层还可以为氧化硅、氮化硅、氮氧化硅等绝缘介质材料，通过沉积工艺形成，后续采用光刻和刻蚀工艺进行图形化形成所述支撑结构320。
在其他一些实施例中，所述支撑结构320还可以通过对所述封盖基板300进行刻蚀后形成。具体地，可以在所述封盖基板300上形成图形化的光刻胶层，然后再以所述图形化的光刻胶层为掩膜刻蚀所述封盖基板300，在所述封盖基板300内形成所述支撑结构320，所述支撑结构320即为所述封盖基板300第一表面300a上的凸起部分。
接着，参考图7，将所述封盖基板300的第一表面300a与所述待封装晶圆200的第一表面200a相对并结合，使得所述支撑结构320与所述待封装晶圆200的第一表面200a围成空腔(未标示)，所述感应区域211位于所述空腔内。
本实施例中，通过粘合层(未示出)将所述封盖基板300和所述待封装晶圆200相结合。例如，可以在所述封盖基板300第一表面300a的支撑结构320的顶表面上，和/或所述待封装晶圆200的第一表面200a上，通过喷涂、旋涂或者黏贴的工艺形成所述粘合层，再将所述封盖基板300的第一表面300a与所述待封装晶圆200的第一表面200a相对压合，通过所述粘合层结合。所述粘合层既可以实现粘接作用，又可以起到绝缘和密封作用。所述粘合层可 以为高分子粘接材料，例如硅胶、环氧树脂、苯并环丁烯等聚合物材料。
本实施例中，将所述封盖基板300的第一表面300a与所述待封装晶圆200的第一表面200a相对结合后，所述支撑结构320与所述待封装晶圆200的第一表面200a围成空腔。所述空腔的位置与所述感应区域211的位置相对应，且所述空腔面积略大于所述感应区域211的面积，可以使得所述感应区域211位于所述空腔内。本实施例中，将所述封盖基板300和所述待封装晶圆200相结合后，所述待封装晶圆200上的焊垫212被所述封盖基板300上的支撑结构320覆盖。所述封盖基板300可以在后续工艺中，起到保护所述待封装晶圆200的作用。
接着，参考图8，对所述待封装晶圆200进行封装处理。
具体地，首先，从所述待封装晶圆200的第二表面200b对所述待封装晶圆200进行减薄，以便于后续通孔的刻蚀，对所述待封装晶圆200的减薄可以采用机械研磨、化学机械研磨工艺等；接着，从所述待封装晶圆200的第二表面200b对所述待封装晶圆200进行刻蚀，形成通孔(未标示)，所述通孔暴露出所述待封装晶圆200第一表面200a一侧的焊垫212；接着，在所述待封装晶圆200的第二表面200b上以及所述通孔的侧壁上形成绝缘层213，所述绝缘层213暴露出所述通孔底部的焊垫212，所述绝缘层213可以为所述待封装晶圆200的第二表面200b提供电绝缘，还可以为所述通孔暴露出的所述待封装晶圆200的衬底提供电绝缘，所述绝缘层213的材料可以为氧化硅、氮化硅、氮氧化硅或者绝缘树脂；接着，在所述绝缘层213表面形成连接所述焊垫212的金属层214，所述金属层214可以作为再布线层，将所述焊垫212引至所述待封装晶圆200的第二表面200b上，再与外部电路连接，所述金属层214经过金属薄膜沉积和对金属薄膜的刻蚀后形成；接着，在所述金属层214表面及所述绝缘层213表面形成具有开孔(未标示)的阻焊层215，所述开孔暴露出部分所述金属层214的表面，所述阻焊层215的材料为氧化 硅、氮化硅等绝缘介质材料，用于保护所述金属层214；再接着，在所述阻焊层215的表面上形成外接凸起216，所述外接凸起216填充所述开孔，所述外接凸起216可以为焊球、金属柱等连接结构，材料可以为铜、铝、金、锡或铅等金属材料。
对所述待封装晶圆200进行封装处理后，可以使得后续切割获得的芯片封装结构通过所述外接凸起216与外部电路连接。所述芯片单元的感应区域211在将光信号转换为电信号后，所述电信号可以依次通过所述焊垫212、金属层214和外接凸起216，传输至外部电路进行处理。
接着，参考图9，在所述封盖基板300的第二表面300b上形成遮光材料层510，所述遮光材料层510具有与所述感应区域211对应的多个开口520。所述开口520的面积大于或等于所述感应区域211的面积，在后续形成封装结构后，用于暴露所述感应区域211。
在一些实施例中，所述遮光材料层510为不透光或者低透光的黑色有机材料，例如黑胶。所述黑色有机材料为光敏材料，通过光刻工艺可以对其进行图形化。具体地，形成所述遮光材料层510的方法包括：通过旋涂、喷涂或者黏贴的方法在所述封盖基板300的第二表面300b上形成黑色光敏有机材料层；根据所述黑色光敏有机材料的正负显影特性，对所述黑色光敏有机材料层待形成开口520的区域进行曝光，或者对待形成开口520之外的区域进行曝光，进行显影后，在所述黑色光敏有机材料层内形成与所述感应区域相对应的多个开口520；最后，对所述黑色光敏有机材料层进行烘烤坚膜，增强所述黑色光敏有机材料层的机械强度及与所述封盖基板300的粘附性。在一些实施例中，所述黑色光敏有机材料的厚度为10μm～50μm，优选地，可以为15μm，20μm等。
如果所述遮光材料层510采用黑胶形成，由于黑胶为有机材料，难以做 到完全不透光。通过适当的增加黑胶材料层的厚度，可以达到较佳的遮光效果，但是，黑胶材料层的厚度越大，在曝光过程中，光线越难以穿透所述黑胶材料层到达底部，即所述黑胶材料层的底部不能完全曝光，增大了显影难度，影响所形成图形的分辨率；此外，黑胶材料作为有机物，在曝光显影过程中还容易产生颗粒物(particle)，污染芯片，导致透光率不佳。
因此，在另外一些实施例中，所述遮光材料层510还可以为金属，所述金属可以经过黑化处理，使得光线在其表面不能形成镜面反射。所述金属可以为铝、铝合金或者其他适宜的金属材料。具体地，形成所述遮光材料层510的方法包括：通过溅射的工艺在所述封盖基板300的第二表面300b形成金属材料层，本实施例中，所述金属材料层为铝材料层；接着，再通过酸碱药水对所述金属材料层进行黑化，例如，可以采用含硫的碱溶液对所述铝材料层进行处理，在所述铝材料层上形成黑色的硫化物膜层，提高所述铝材料层的遮光效果；接着，在经过黑化的金属材料层上形成图像化的光刻胶层，所述图形化的光刻胶层暴露出待形成开口520的区域，再以所述图形化的光刻胶层为掩膜对所述经过黑化的金属材料层进行刻蚀直至到达所述封盖基板300的第二表面300b，去除所述图形化的光刻胶层，形成具有多个开口520的遮光材料层510。经过黑化处理的金属材料，不仅遮光效果好，而且厚度较薄，有利于最终形成的封装结构的轻薄化。在一些实施例中，所述经过黑化处理的金属材料层的厚度为1μm～10μm，优选地，可以为5μm，6μm等。
需要说明的是，在其他实施例中，在所述封盖基板300的第二表面300b上形成遮光材料层510还可以在所述封盖基板300与所述待封装晶圆200结合之前，还可以在后续的第一切割工艺之后，本发明对此不作限定，可以根据具体的工艺条件进行选择。
接着，参考图10和图11，沿所述待封装晶圆200的切割道区域220(同时参考图5)对所述待封装晶圆200、所述封盖基板300和所述遮光材料层510 进行切割，形成多个如图2所示的封装结构。所述封装结构包括芯片单元210；位于所述芯片单元210上的由切割所述封盖基板300形成的上盖板330，以及由切割所述遮光材料层510形成的遮光层511，所述遮光层511覆盖所述上盖板330的第二表面330b，并暴露出与所述感应区域211相对的第二表面330b的中间区域。
本实施例中，对所述待封装晶圆200、所述封盖基板300和所述遮光材料层510的切割包括了第一切割工艺和第二切割工艺。具体地，参考图10，首先，执行第一切割工艺，所述第一切割工艺沿如图5所示的切割道区域220从所述待封装晶圆200的第二表面200b开始切割，直至到达所述待封装晶圆200的第一表面200a形成第一切割沟槽410。所述第一切割工艺可以采用切片刀切割或者激光切割，所述切片刀切割可以采用金属刀或者树脂刀。
接着，参考图11，执行第二切割工艺，所述第二切割工艺沿与图5所述的切割道区域220对应的区域从所述遮光材料层510开始，对所述遮光材料层510和所述封盖基板300切割，直至到达所述待封装晶圆200的第一表面200a，形成贯通所述第一切割沟槽410的第二切割沟槽420，同时形成多个封装结构，从而完成切割工艺。所述第二切割工艺也可以采用切片刀切割或者激光切割。
在其他一些实施例中，所述第二切割工艺也可以沿所述第一切割沟槽410从所述封盖基板300的第一表面300a切割所述封盖基板300和遮光材料层510，形成贯穿所述封盖基板300和遮光材料层510的第二切割沟槽420，完成切割。
需要说明的是，本实施例中，所述第一切割工艺在所述第二切割工艺之前执行，在其他一些实施例中，所述第一切割工艺也可以在所述第二切割工艺之后执行，本发明对此不作限定。
此外，本发明的另一实施例中，还提供了一种形成如图3所示的封装结构的封装方法。请参考图12至图15，为本发明另一实施例的形成图3所示的封装结构的封装过程的结构示意图。
在本实施例中，与前一实施例类似，参考图4至图8，提供待封装晶圆200，所述待封装晶圆200的第一表面200a包括多个芯片单元210和位于芯片单元210之间的切割道区域220，所述芯片单元包括感应区域211；提供封盖基板300，在所述封盖基板300的第一表面300a形成多个支撑结构320，所述支撑结构320与所述待封装晶圆200上的感应区域211相对应；将所述封盖基板300的第一表面300a与所述待封装晶圆200的第一表面200a相对结合，使得所述支撑结构320与所述待封装晶圆200的第一表面200a围成空腔，所述感应区域211位于所述空腔内。具体可参考前一实施例，在此不再赘述，以下仅对与前一实施例不同之处详述。
在将所述封盖基板300和所述待封装晶圆200结合之后，参考图12，执行第一切割工艺。所述第一切割工艺沿如图5所示的切割道区域220从所述待封装晶圆200的第二表面200b开始切割，直至到达所述待封装晶圆200的第一表面200a形成第一切割沟槽410。
接着，参考图13，执行第三切割工艺，所述第三切割工艺沿如图5所示的切割道区域220从所述封盖基板300的第二表面300b开始切割，到达预定深度，形成第三切割沟槽430。所述第三切割沟槽430位于所述封盖基板300内。所述第三切割沟槽430的宽度大于所述第一切割沟槽410和后续形成的第二切割沟槽的宽度，以便后续的遮光材料层可以形成于所述第三沟槽430内。形成所述第三切割沟槽430工艺可以为钻头研磨、片刀切割或者激光切割。
接着，参考图14，在所述封盖基板300的第二表面300b上形成遮光材料 层510，所述遮光材料层510具有与所述感应区域211对应的多个开口520。与前一实施例相比，本实施例中，所述遮光材料层510还覆盖了所述第三切割沟槽430的侧壁和底部表面，使得后续完成切割后，所述遮光材料层510还可以覆盖上盖板的部分侧壁。所述遮光材料层510的材料可以为黑色光敏有机材料或者金属。
接着，参考图15，执行第二切割工艺，所述第二切割工艺沿与图5所述的切割道区域220对应的区域从所述遮光材料层510开始，对所述遮光材料层510和所述封盖基板300切割，直至到达所述待封装晶圆200的第一表面200a，形成贯通所述第一切割沟槽410和第三切割沟槽430的第二切割沟槽420，同时形成多个封装结构，从而完成切割工艺。本实施例中，所述第二切割沟槽420的宽度小于所述第三切割沟槽430的宽度，以减小对所述第三切割沟槽430侧壁表面的遮光材料层510的损伤，使得所述第三切割沟槽430侧壁表面的遮光材料层510保留在所形成的封装结构中。因此，参考图3，在最终形成的封装结构中，由切割所述遮光材料层510形成的遮光层511还覆盖了所述上盖板330的侧壁的上部区域。在一些实施例中，所述遮光层511覆盖的所述上盖板330的侧壁的上部区域的高度为所述上盖板330厚度的1/5～4/5。
需要说明的是，本实施例中，所述第一切割工艺在所述第三切割工艺和所述第二切割工艺之前执行，在其他一些实施例中，所述第一切割工艺也可以在所述第三切割工艺和所述第二切割工艺之后执行，还可以在所述第三切割工艺和第二切割工艺之间执行。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (15)

  1. 一种封装结构，其特征在于，包括：
    芯片单元，所述芯片单元的第一表面包括感应区域；
    上盖板，所述上盖板的第一表面具有支撑结构，所述上盖板覆盖所述芯片单元的第一表面，所述支撑结构位于所述上盖板和所述芯片单元之间，且所述感应区域位于所述支撑结构和所述芯片单元的第一表面围成的空腔之内；以及
    遮光层，所述遮光层覆盖在所述上盖板的与第一表面相对的第二表面上，并暴露出第二表面在透光方向上与所述感应区域重合的中间区域。
  2. 如权利要求1所述的封装结构，其特征在于，所述遮光层暴露出的所述上盖板中间区域的面积大于或者等于所述感应区域的面积。
  3. 如权利要求1所述的封装结构，其特征在于，所述遮光层还覆盖所述上盖板的部分侧壁。
  4. 如权利要求1所述的封装结构，其特征在于，所述遮光层的材料为黑色光敏有机材料，厚度为10μm～50μm。
  5. 如权利要求1所述的封装结构，其特征在于，所述遮光层的材料为金属，厚度为1μm～10μm。
  6. 如权利要求5所述的封装结构，其特征在于，所述遮光层的材料为铝。
  7. 如权利要求5所述的封装结构，其特征在于，所述金属的表面经过黑化处理。
  8. 如权利要求1所述的封装结构，其特征在于，所述芯片单元还包括：
    位于所述感应区域外的焊垫；
    从所述芯片单元的与第一表面相对的第二表面贯穿所述芯片单元的通孔，所述通孔暴露出所述焊垫；
    覆盖所述芯片单元第二表面和所述通孔侧壁表面的绝缘层；
    位于所述绝缘层表面且与所述焊垫电连接的金属层；
    位于所述金属层和所述绝缘层表面的阻焊层，所述阻焊层具有暴露出部分所述金属层的开孔；以及
    填充所述开孔，并暴露在所述阻焊层表面之外的外接凸起。
  9. 一种形成如权利要求1-8中任一项所述的封装结构的封装方法，其特征在于，包括：
    提供待封装晶圆，所述待封装晶圆的第一表面包括多个芯片单元和位于芯片单元之间的切割道区域，所述芯片单元包括感应区域；
    提供封盖基板，在所述封盖基板的第一表面形成多个支撑结构，所述支撑结构与所述待封装晶圆上的感应区域相对应；
    将所述封盖基板的第一表面与所述待封装晶圆的第一表面相对结合，使得所述支撑结构与所述待封装晶圆的第一表面围成空腔，所述感应区域位于所述空腔内；
    在所述封盖基板的与第一表面相对的第二表面上形成遮光材料层，所述遮光材料层具有与所述感应区域对应的开口；以及
    沿所述切割道区域对所述待封装晶圆、所述封盖基板和所述遮光材料层进行切割，形成多个封装结构，所述封装结构包括所述芯片单元、由切割所述封盖基板形成的上盖板和由切割所述遮光材料层形成的遮光层，所述遮光层覆盖在所述上盖板的第二表面上，并暴露出在透光方向上与所述感应区域重合的中间区域。
  10. 如权利要求9所述的封装方法，其特征在于，沿所述切割道区域对所述待封装晶圆、所述封盖基板和所述遮光材料层进行切割包括：
    执行第一切割工艺，包括沿所述切割道区域从所述待封装晶圆的与第一表面相对的第二表面开始切割，直至到达所述待封装晶圆的第一表面形成第一切割沟槽；以及
    执行第二切割工艺，包括切割所述遮光材料层和所述封盖基板，形成与所述第一切割沟槽贯通的第二切割沟槽，同时形成多个封装结构。
  11. 如权利要求10所述的封装方法，其特征在于，沿所述切割道区域对所述待封装晶圆、所述封盖基板和所述遮光材料层进行切割还包括：
    在所述第二切割工艺前执行第三切割工艺，所述第三切割工艺沿所述切割道区域从所述封盖基板的第二表面开始切割到达预设深度，形成第三切割沟槽；
    在所述封盖基板的第二表面上形成遮光材料层时，所述遮光材料层覆盖所述第三切割沟槽侧壁；以及
    所述第二切割工艺切割所述遮光材料层和所述封盖基板形成的第二切割沟槽贯通所述第一切割沟槽和第三切割沟槽，所述第二切割沟槽的宽度小于所述第三切割沟槽的宽度，在形成多个封装结构后，所述遮光层还覆盖所述上盖板的侧壁的上部区域。
  12. 如权利要求9所述的封装方法，其特征在于，所述遮光材料层为黑色光敏有机材料，在所述封盖基板的第二表面上形成遮光材料层包括：
    采用旋涂、喷涂或者黏贴的工艺在所述封盖基板的第二表面上形成黑色光敏有机材料层；
    对所述黑色光敏有机材料层进行曝光和显影，在所述黑色光敏有机材料层内形成与所述感应区域对应的开口；以及
    对所述黑色光敏有机材料层进行烘烤坚膜。
  13. 如权利要求9所述的封装方法，其特征在于，所述遮光材料层为金属，在所述封盖基板的第二表面上形成遮光材料层包括：
    采用溅射工艺在所述封盖基板的第二表面上形成金属材料层；
    在所述金属材料层上形成图形化的光刻胶层，所述图像化的光刻胶层暴露出所述金属材料层待形成开口的区域；
    以所述图形化的光刻胶层为掩膜，刻蚀所述金属材料层，直至暴露出所述封盖基板的第二表面，形成与所述感应区域对应的开口；以及
    去除所述图形化的光刻胶层。
  14. 如权利要求13所述的封装方法，其特征在于，还包括：采用酸碱溶液对所述金属材料层的表面进行黑化处理。
  15. 如权利要求9所述的封装方法，其特征在于，所述芯片单元还包括焊垫，所述焊垫位于所述感应区域外，当将所述封盖基板的第一表面与所述待封装晶圆的第一表面相结合后，所述封装方法还包括：
    从所述待封装晶圆的与第一表面相对的第二表面进行减薄；
    从所述待封装晶圆的第二表面刻蚀所述待封装晶圆，形成通孔，所述通孔暴露出所述芯片单元的焊垫；
    在所述待封装晶圆的第二表面以及通孔的侧壁表面形成绝缘层；
    在所述绝缘层表面形成连接焊垫的金属层；
    在所述金属层表面以及绝缘层表面形成具有开孔的阻焊层，所述开孔暴露出部分金属层表面；以及
    在所述阻焊层表面上形成外接凸起，所述外接凸起填充所述开孔。
PCT/CN2016/097359 2015-09-02 2016-08-30 封装结构及封装方法 WO2017036381A1 (zh)

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725185A (zh) * 2019-03-04 2020-09-29 苏州多感科技有限公司 图像传感器及其制备方法、图像识别方法、电子设备
CN110649055A (zh) * 2019-09-27 2020-01-03 华天科技（昆山）电子有限公司 改善cis芯片炫光问题的晶圆级封装方法以及封装结构
CN113690261A (zh) * 2021-08-23 2021-11-23 锐芯微电子股份有限公司 Cmos图像传感器的形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101226949A (zh) * 2007-01-15 2008-07-23 采钰科技股份有限公司 图像感测装置与其封装方法
CN102782862A (zh) * 2010-02-26 2012-11-14 精材科技股份有限公司 芯片封装体及其制造方法
CN104347644A (zh) * 2013-07-25 2015-02-11 意法半导体研发(深圳)有限公司 具有透镜组件的图像检测器及相关方法
CN105070734A (zh) * 2015-09-02 2015-11-18 苏州晶方半导体科技股份有限公司 封装结构及封装方法
CN204991711U (zh) * 2015-09-02 2016-01-20 苏州晶方半导体科技股份有限公司 封装结构

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7180149B2 (en) * 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
CN101784917B (zh) * 2007-07-25 2014-04-02 株式会社日本触媒 光屏蔽膜
KR100982270B1 (ko) * 2008-08-08 2010-09-15 삼성전기주식회사 카메라 모듈 및 이의 제조 방법
TWI437700B (zh) * 2010-05-31 2014-05-11 Kingpak Tech Inc 晶圓級影像感測器構裝結構之製造方法
TWI546921B (zh) * 2013-03-14 2016-08-21 精材科技股份有限公司 晶片封裝體及其形成方法
CN104201116B (zh) * 2014-09-12 2018-04-20 苏州晶方半导体科技股份有限公司 指纹识别芯片封装方法和封装结构
JP2018533217A (ja) * 2015-10-29 2018-11-08 チャイナ ウェイファー レベル シーエスピー カンパニー リミテッド 感光性チップパッケージ化構造及びそのパッケージ化方法
US20180090524A1 (en) * 2016-09-26 2018-03-29 China Water Level CSP Co., Ltd. Image sensor package and method of packaging the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101226949A (zh) * 2007-01-15 2008-07-23 采钰科技股份有限公司 图像感测装置与其封装方法
CN102782862A (zh) * 2010-02-26 2012-11-14 精材科技股份有限公司 芯片封装体及其制造方法
CN104347644A (zh) * 2013-07-25 2015-02-11 意法半导体研发(深圳)有限公司 具有透镜组件的图像检测器及相关方法
CN105070734A (zh) * 2015-09-02 2015-11-18 苏州晶方半导体科技股份有限公司 封装结构及封装方法
CN204991711U (zh) * 2015-09-02 2016-01-20 苏州晶方半导体科技股份有限公司 封装结构

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