CN104051359A - 晶片封装体及其形成方法 - Google Patents

晶片封装体及其形成方法 Download PDF

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Publication number
CN104051359A
CN104051359A CN201410080425.8A CN201410080425A CN104051359A CN 104051359 A CN104051359 A CN 104051359A CN 201410080425 A CN201410080425 A CN 201410080425A CN 104051359 A CN104051359 A CN 104051359A
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China
Prior art keywords
depression
light shield
wafer encapsulation
metal light
shield layer
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CN201410080425.8A
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CN104051359B (zh
Inventor
林义闵
张义民
张恕铭
何彦仕
刘沧宇
郑家明
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体及其形成方法，该晶片封装体包括：一半导体基底，具有一第一表面及一第二表面；一第一凹陷，自该第一表面朝该第二表面延伸；一第二凹陷，自该第一凹陷的一底部朝该第二表面延伸，其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面；一导线层，设置于该第一表面上，且延伸进入该第一凹陷及/或该第二凹陷；一绝缘层，位于该导线层与该半导体基底之间；以及一金属遮光层，设置于该第一表面上，且具有至少一孔洞，其中该至少一孔洞的形状为一四边形。本发明有助于晶片封装体的缩小化，且可使晶片封装体的可靠度提升。

Description

晶片封装体及其形成方法
技术领域
本发明是有关于晶片封装体，且特别是有关于采用晶圆级封装制程制作的晶片封装体。
背景技术
晶片封装制程是形成电子产品过程中的一重要步骤。晶片封装体除了将晶片保护于其中，使免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
由于电子产品缩小化的需求仍持续，如何于有限空间中设置更多的导电线路成为重要课题。此外，亦有避免外界光线影响晶片封装体的运作的需求。
发明内容
本发明提供一种晶片封装体，包括：一半导体基底，具有一第一表面及一第二表面；一第一凹陷，自该第一表面朝该第二表面延伸；一第二凹陷，自该第一凹陷的一底部朝该第二表面延伸，其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面；一导线层，设置于该第一表面上，且延伸进入该第一凹陷及/或该第二凹陷；一绝缘层，位于该导线层与该半导体基底之间；以及一金属遮光层，设置于该第一表面上，且具有至少一孔洞，其中该至少一孔洞的形状为一四边形。
本发明提供一种晶片封装体，包括：一半导体基底，具有一第一表面及一第二表面；一第一凹陷，自该第一表面朝该第二表面延伸；一第二凹陷，自该第一凹陷的一底部朝该第二表面延伸，其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面；一导线层，设置于该第一表面上，且延伸进入该第一凹陷及/或该第二凹陷；一绝缘层，位于该导线层与该半导体基底之间；以及一金属遮光层，设置于该第一表面上，且具有至少一孔洞，其中该至少一孔洞的形状为一三边形、一五边形、一六边形或一七边形。
本发明提供一种晶片封装体的形成方法，包括：提供至少一半导体基底，具有一第一表面及一第二表面；自该第一表面移除部分的该半导体基底以于该半导体基底之中形成一第一凹陷及一第二凹陷，其中该第一凹陷朝该第二表面延伸，而该第二凹陷自该第一凹陷的一底部朝该第二表面延伸；于该第一表面上形成一绝缘层，该绝缘层延伸进入该第一凹陷及该第二凹陷；于该绝缘层上形成一导线层，该导线层延伸进入该第一凹陷及/或该第二凹陷；于该绝缘层上形成一金属遮光层，该具有至少一孔洞，其中该至少一孔洞的形状为一四边形；以及沿着该半导体基底的至少一预定切割道进行一切割制程以形成至少一晶片封装体，其中在该切割制程之后，该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面。
本发明有助于晶片封装体的缩小化，且可使晶片封装体的可靠度提升。
附图说明
图1A-1D显示根据本发明一实施例的晶片封装体的制程剖面图。
图2显示根据本发明一实施例的晶片封装体的俯视图。
图3显示根据本发明一实施例的晶片封装体的制程剖面图。
图4A及4B分别显示根据本发明实施例的晶片封装体的局部俯视图。
附图中符号的简单说明如下：
100～基底；100a、100b～表面；101～介电层；102～元件区；104a、104G～导电垫；116～绝缘层；117～金属层；118～导线层；130a、130b～凹陷；204～焊线；260a、260b～金属遮光层；262～孔洞；302～容器；304～蚀刻液；306～放置台；SC～预定切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，本发明可能于许多实施例重复使用标号及/或文字。此重复仅为了简化与清楚化，不代表所讨论的不同实施例之间必然有关联。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。为了简单与清楚化，许多结构可能会绘成不同的尺寸。
本发明一实施例的晶片封装体可用以封装影像感测器晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital oranalog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro MechanicalSystem;MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package;WSP)制程对影像感测元件、发光二极管(light-emitting diodes;LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)喷墨头(ink printer heads)、或功率金属氧化物半导体场效电晶体模组(powerMOSFET modules)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。在一实施中，上述切割后的封装体为一晶片尺寸封装体(CSP;chipscale package)。晶片尺寸封装体(CSP)的尺寸可仅略大于所封装的晶片。例如，晶片尺寸封装体的尺寸不大于所封装晶片的尺寸的120%。
图1A-1D显示根据本发明一实施例的晶片封装体的制程剖面图。如图1A所示，提供半导体基底100，其具有表面100a及表面100b。半导体基底100例如包括硅基底、硅锗基底、砷化镓基底、其他适合的半导体基底、或前述的组合。在一实施例中，半导体基底100为一半导体晶圆(例如，硅晶圆)。因此，可进行晶圆级封装制程以节省制作成本与制作时间。半导体基底100可定义有至少一预定切割道SC。在后续制程中，可沿着预定切割道SC切割半导体基底100以形成多个彼此分离的晶片封装体。
半导体基底100中可形成有元件区102。元件区102中可形成有有源元件或无源元件、数字电路或模拟电路等集成电路的电子元件，例如是有关于光电元件、微机电系统、微流体系统、或利用热、光线及压力等物理量变化来测量的物理感测器。在一实施例中，元件区102中形成有影像感测元件。或者，元件区102中可形成有发光二极管、太阳能电池、射频元件、加速计、陀螺仪、微制动器、表面声波元件、压力感测器、喷墨头、或功率金属氧化物半导体场效电晶体模组。
半导体基底100的表面100a上可形成有介电层101。介电层101的材质可包括(但不限于)氧化硅、氮化硅、氮氧化硅、或前述的组合。介电层101中可形成有多个导电垫104a。每一导电垫104a可包括多个导电层的叠层。导电垫104a可通过介电层101中的内连线结构(未显示)而与元件区102中的对应的元件电性连接。换言之，导电垫104a电性连接元件区102，可用于输入及/或输出电性信号。在一实施例中，可移除部分的介电层101而使导电垫104a露出。
如图1B所示，在一实施例中，可通过图案化制程及/或切割制程移除部分的半导体基底100以形成多个凹陷。这些凹陷可自表面100a朝表面100b延伸，并彼此相连通。此外，在后续沿着预定切割道SC进行的切割制程之后，这些凹陷的侧壁与底部可共同形成半导体基底100的外侧表面。即，在切割制程之后，半导体基底100的部分的外侧表面由这些凹陷的侧壁与底部所共同形成。在图1B的实施例中，以两个凹陷130b及130a为例做说明。然应注意的是，在其他实施例中，半导体基底100可具有三个或三个以上的相连通凹陷，且在切割制程之后，这些凹陷的底部及侧边可共同形成半导体基底100的外侧表面。
如图1B所示，凹陷130b可自半导体基底100的表面100a朝表面100b延伸。凹陷130a可自凹陷130b的底部朝表面100b延伸。在后续沿着预定切割道SC进行切割制程之后，凹陷130b的侧壁及底部与凹陷130a的侧壁及底部可共同形成半导体基底100的外侧表面。
接着，如图1C所示，可于半导体基底100的表面100a上形成绝缘层116。绝缘层116可延伸进入凹陷130b及凹陷130a。在一实施例中，绝缘层116可顺应性形成于凹陷130b及凹陷130a的侧壁及底部上。在一实施例中，可采用化学气相沉积制程、旋转涂布制程、喷涂制程、热氧化制程、氮化制程、其他适合制程、或前述的组合以形成绝缘层116。绝缘层116的材质可包括(但不限于)氧化硅、氮化硅、氮氧化硅、高分子材料、或前述的组合。绝缘层116可具有露出导电垫104a的开口。
接着，可于半导体基底100的表面100a上的绝缘层116上形成金属层117。金属层117的材质可包括(但不限于)铜、铝、金、铂、镍、锡、钛、或前述的组合。在一实施例中，金属层117可包括铝铜层(其可例如具有1.2μm的厚度)及晶种层。晶种层例如为钛层或钛钨(TiW)层。金属层117可延伸进入凹陷130b及/或凹陷130a。例如，在一实施例中，金属层117可延伸于凹陷130b的侧壁与底部上，且更进一步延伸于凹陷130a的侧壁与底部上，如图1C所示。
接着，如图1D所示，将金属层117图案化以形成至少一导线层118。在一实施例中，导线层118可电性连接导电垫104a，且延伸于凹陷130b及/或凹陷130a之中。在一实施例中，多个导线层118可分别电性连接对应的导电垫104a，并延伸于凹陷130a的底部上。
图2显示根据本发明一实施例的晶片封装体的俯视图，其中相同或相似的标号用以标示相同或相似的元件。图1D可相应于图2中的切线a-b处的剖面图。如图2及图1D所示，导线层118可通过绝缘层116及介电层101的开口而电性接触所露出的导电垫104a。虽然图2仅显示出一导线层118，然更多的导线层118可形成于绝缘层116之上，且可分别电性连接对应的导电垫104a，并延伸于凹陷130a的底部上。在另一实施例中，半导体基底100可形成有其他不与凹陷130b及130a连通的其他凹陷，其中部分的导线层118亦可延伸进入其他凹陷之中。换言之，在其他实施例中，不同的导线层可能延伸进入不同的凹陷。
如图2及图1D所示，在一实施例中，可于半导体基底100的表面100a上的绝缘层116上形成金属遮光层260a及/或金属遮光层260b。或者，在其他实施例中，可形成更多的金属遮光层。金属遮光层260a及/或金属遮光层260b可不电性接触导线层118。在一实施例中，金属遮光层260a及/或金属遮光层260b的位于表面100a上的投影可位于元件区102在表面100a上的投影与导电垫104a在表面100a上的投影之间。金属遮光层260a及/或金属遮光层260b可用以阻挡部分的外界光线照射元件区102，以避免影响元件区102的运作。在一实施例中，金属遮光层260a及/或金属遮光层260b可选择性通过绝缘层116及介电层101的开口而电性接触介电层101中的接地导电垫104G。
如图2所示，金属遮光层260a或金属遮光层260b的宽度通常较宽，因此容易具有较高的内应力而可能导致缺陷。在一实施例中，为了减轻金属遮光层260a或金属遮光层260b中的内应力，可于金属遮光层260a或金属遮光层260b中形成应力释放图案(stress release pattern)，其可例如为形成于金属遮光层中的孔洞。
如图2及图1D所示，金属遮光层260a或金属遮光层260b可具有至少一孔洞262。在一实施例中，可通过图案化制程移除部分的金属遮光层260a或金属遮光层260b以形成孔洞262。孔洞262例如可贯穿金属遮光层260a。然本发明实施例不限于此。在其他实施例中，孔洞262未完全贯穿金属遮光层260a。
在一实施例中，金属遮光层260a可于形成导线层118之后，另以其他沉积制程及图案化制程而形成于绝缘层116之上。或者，在其他实施例中，金属遮光层260a可与导线层118同时形成。例如，在一实施例中，金属遮光层260a及导线层118可皆由图案化金属层117而形成。在此情形下，金属遮光层260a的材质可相同于导线层118的材质。在一实施例中，金属遮光层260a的厚度可相同于导线层118的厚度。在一实施例中，金属遮光层260a、金属遮光层260a中的孔洞262及导线层118是同时形成。
图3显示根据本发明一实施例的晶片封装体的制程剖面图，其中相同或相似的标号用以标示相同或相似的元件。如图3所示，可提供容器302，并于其中注入蚀刻液304。接着，可提供多个类似于图1C所示的半导体基底100，并可于半导体基底100的表面形成具有所需图案的光阻层。接着，可于平台306设置多个半导体基底100，并浸泡于蚀刻液304之中以将金属层107图案化为多个导线层118及具有至少一孔洞262的至少一金属遮光层260a。如此，可同时定义出多个半导体基底(或晶圆)上的导线层与金属遮光层，可减少制程时间与成本。在一实施例中，可反复升起平台306与放下平台306。即，可对半导体基底100进行反复地蚀刻液浸泡以完成金属层117的图案化。
在一实施例中，金属遮光层260a的孔洞262的形状是设计为四边形。因此，可较轻易地移除蚀刻液或蚀刻剂蚀刻金属层117时所产生的气泡，使金属层117的图案化可顺利进行。在一实施例中，金属遮光层260a中可形成有多个孔洞262，且孔洞262的尺寸或形状可彼此不同，如图2所示。然应注意的是，本发明实施例不限于此。在其他实施例中，金属遮光层260a的孔洞262的尺寸或形状可大抵彼此相同。
例如，图4A及4B分别显示根据本发明实施例的晶片封装体的局部俯视图，其中相同或相似的标号用以标示相同或相似的元件。如图4A及4B所示，金属遮光层260a的孔洞262的尺寸或形状可大抵彼此相同，其可例如为长方形或具有至少一圆角的长方形。在其他实施例中，孔洞262的形状可为其他四边形，例如正方形、菱形、梯形、平行四边形或其他四边形，且可(但不限于)皆分别具有至少一圆角。在一实施例中，金属遮光层260a的孔洞262可大抵均匀分布于金属遮光层260a之中。应注意的是，本发明实施例不限于此。在其他实施例中，金属遮光层260a的孔洞262的形状可为三边形、五边形、六边形或七边形。在一实施例中，金属遮光层260a的孔洞262的形状为非圆形且为边数少于八边的形状。如此，可避免蚀刻金属层117以形成孔洞262的过程中，蚀刻金属层117所产生的气泡附着于孔洞262而不易移除，影响孔洞262的形成。
接着，回到图1D，在一实施例中，可选择性形成焊线204。焊线204可电性接触延伸进入凹陷130b及/或凹陷130a中的导线层118。在一实施例中，焊线204可直接接触这些凹陷中的最接近表面100b的最低凹陷(例如，凹陷130a)的底部正上方的导线层118。最低凹陷(例如，凹陷130a)的底部可大抵平行于表面100b。焊线204可用于使其他电子构件(例如，印刷电路板)的电性信号通过导线层118而传递至晶片封装体。接着，可沿着半导体基底100的预定切割道SC进行切割制程以形成至少一晶片封装体。或者，在其他实施例中，可于形成焊线204之前，进行半导体基底100的切割制程。
在本发明实施例中，通过堆叠晶片与将导线层导引至凹陷之中，可于有限空间之中，设置更多的导电线路，有助于晶片封装体的缩小化。由于导线线路的传递距离减小，信号传递速度可获提升。此外，由于焊线形成于凹陷之中，可受到凹陷的保护而使晶片封装体的可靠度提升。由于焊线形成于凹陷之中，可使晶片封装体的整体体积缩小。本发明实施例所形成的凹陷包括多个相连通的凹陷，可使导线层于更为缓和的轮廓上沉积，可提升导线层的可靠度。本发明实施例所形成的金属遮光层可避免光线影响元件区的运作，可提升效能。金属遮光层的孔洞有助于释放金属遮光层中的应力以增进晶片封装体的可靠度。通过金属遮光层的孔洞的形状设计，可使晶片封装体的制作时间与制作成本显著降低。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一半导体基底，具有一第一表面及一第二表面；
一第一凹陷，自该第一表面朝该第二表面延伸；
一第二凹陷，自该第一凹陷的一底部朝该第二表面延伸，其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面；
一导线层，设置于该第一表面上，且延伸进入该第一凹陷及/或该第二凹陷；
一绝缘层，位于该导线层与该半导体基底之间；以及
一金属遮光层，设置于该第一表面上，且具有至少一孔洞，其中该至少一孔洞的形状为一四边形。
2.根据权利要求1所述的晶片封装体，其特征在于，该四边形具有至少一圆角。
3.根据权利要求1所述的晶片封装体，其特征在于，该四边形为一长方形。
4.根据权利要求1所述的晶片封装体，其特征在于，该至少一孔洞贯穿该金属遮光层。
5.根据权利要求1所述的晶片封装体，其特征在于，该金属遮光层的材质相同于该导线层的材质。
6.根据权利要求1所述的晶片封装体，其特征在于，该金属遮光层的厚度相同于该导线层的厚度。
7.根据权利要求1所述的晶片封装体，其特征在于，该至少一孔洞包括多个孔洞，且所述孔洞的尺寸或形状彼此不同。
8.根据权利要求1所述的晶片封装体，其特征在于，该至少一孔洞包括多个孔洞，且所述孔洞的尺寸或形状彼此大抵相同。
9.根据权利要求8所述的晶片封装体，其特征在于，所述孔洞大抵均匀分布于该金属遮光层之中。
10.根据权利要求1所述的晶片封装体，其特征在于，还包括：
一介电层，位于该第一表面与该绝缘层之间；
一元件区，形成于该半导体基底之中；以及
多个导电垫，位于该介电层之中，其中该导线层电性连接其中一所述导电垫。
11.根据权利要求10所述的晶片封装体，其特征在于，该金属遮光层在该第一表面上的一投影位于该元件区在该第一表面上的一投影与所述导电垫在该第一表面上的投影之间。
12.根据权利要求10所述的晶片封装体，其特征在于，该金属遮光层电性连接该介电层中的一接地导电垫。
13.根据权利要求1所述的晶片封装体，其特征在于，还包括一焊线，该焊线电性接触该第二凹陷的该第二底部正上方的该导线层。
14.根据权利要求1所述的晶片封装体，其特征在于，该导线层不电性接触该金属遮光层。
15.一种晶片封装体，其特征在于，包括：
一半导体基底，具有一第一表面及一第二表面；
一第一凹陷，自该第一表面朝该第二表面延伸；
一第二凹陷，自该第一凹陷的一底部朝该第二表面延伸，其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面；
一导线层，设置于该第一表面上，且延伸进入该第一凹陷及/或该第二凹陷；
一绝缘层，位于该导线层与该半导体基底之间；以及
一金属遮光层，设置于该第一表面上，且具有至少一孔洞，其中该至少一孔洞的形状为一三边形、一五边形、一六边形或一七边形。
16.一种晶片封装体的形成方法，其特征在于，包括：
提供至少一半导体基底，该半导体基底具有一第一表面及一第二表面；
自该第一表面移除部分的该半导体基底以于该半导体基底之中形成一第一凹陷及一第二凹陷，其中该第一凹陷朝该第二表面延伸，而该第二凹陷自该第一凹陷的一底部朝该第二表面延伸；
于该第一表面上形成一绝缘层，该绝缘层延伸进入该第一凹陷及该第二凹陷；
于该绝缘层上形成一导线层，该导线层延伸进入该第一凹陷及/或该第二凹陷；
于该绝缘层上形成一金属遮光层，该金属遮光层具有至少一孔洞，其中该至少一孔洞的形状为一四边形；以及
沿着该半导体基底的至少一预定切割道进行一切割制程以形成至少一晶片封装体，其中在该切割制程之后，该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面。
17.根据权利要求16所述的晶片封装体的形成方法，其特征在于，该金属遮光层与该导线层是同时形成。
18.根据权利要求16所述的晶片封装体的形成方法，其特征在于，该金属遮光层与该导线层的形成步骤包括：
于该绝缘层上形成一金属层；以及
将该金属层图案化以形成出该金属遮光层及该导线层。
19.根据权利要求18所述的晶片封装体的形成方法，其特征在于，提供该至少一半导体基底的步骤包括提供多个半导体基底，且将该金属层图案化以形成出该金属遮光层及该导线层的步骤包括：
提供一容器；
于该容器中注入一蚀刻液；以及
将所述半导体基底放置于该蚀刻液之中蚀刻移除部分的该金属层以形成该金属遮光层及该导线层。
20.根据权利要求19所述的晶片封装体的形成方法，其特征在于，该金属遮光层、该金属遮光层的该至少一孔洞及该导线层是同时形成。
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