WO2006013731A1 - 集合基板、半導体素子搭載部材、半導体装置、撮像装置、発光ダイオード構成部材、および発光ダイオード - Google Patents
集合基板、半導体素子搭載部材、半導体装置、撮像装置、発光ダイオード構成部材、および発光ダイオード Download PDFInfo
- Publication number
- WO2006013731A1 WO2006013731A1 PCT/JP2005/013402 JP2005013402W WO2006013731A1 WO 2006013731 A1 WO2006013731 A1 WO 2006013731A1 JP 2005013402 W JP2005013402 W JP 2005013402W WO 2006013731 A1 WO2006013731 A1 WO 2006013731A1
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- WIPO (PCT)
- Prior art keywords
- semiconductor element
- light emitting
- hole
- insulating member
- main surface
- Prior art date
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Classifications
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09181—Notches in edge pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
Definitions
- the present invention relates to a ceramic aggregate substrate formed integrally with a plurality of plate-like insulation members arranged in the same plane, and the insulation member obtained by cutting out the aggregate substrate for each region. Formed using the semiconductor element mounting member, a semiconductor device such as an imaging device or a light emitting diode component formed using the semiconductor element mounting member, and the light emitting diode component. Light emitting diodes.
- the semiconductor element mounting member includes, for example, one surface of the insulating member as a main surface for mounting a semiconductor element, and the opposite surface as an external connection surface for connection with another member, and a semiconductor surface on the main surface.
- Multiple electrode layers for element mounting, multiple electrode layers for connection to other members are formed on the external connection surface, and each electrode layer on both sides is formed in multiple through holes that penetrate the insulating member It is formed in a structure that is individually connected through the conductive layer and via conductor.
- the semiconductor element mounting member is conventionally a ceramic green as a precursor of an insulating member.
- the sheet is generally manufactured by a so-called cofire method (for example,
- Patent Documents 1 and 2 That is, the ceramic green sheet is formed into a planar shape corresponding to the outer shape of the insulating member, and after forming a through hole at the predetermined position, in the case of a via conductor, the ceramic green sheet that is the basis thereof is formed.
- a semiconductor element mounting member is manufactured by simultaneously firing the ceramic liner sheet and the conductive paste while filling the through hole with the conductive paste that is fired simultaneously with the firing of the conductive paste.
- a conductive paste is applied to the surface of the ceramic green sheet formed in a predetermined planar shape to serve as the main surface and the external connection surface of the insulating member.
- a plating metal layer is laminated on the base metal layer, whereby the main surface, And the electrode layer of the external connection surface is formed.
- Patent Document 1 Japanese Patent Laid-Open No. 11-135906
- Patent Document 2 JP 2002-232017
- a ceramic aggregate substrate integrally formed in a shape in which a plurality of plate-like insulating members are arranged on the same plane by the cofire method individual regions of the aggregate substrate are formed. It has been studied to produce a plurality of insulating members at once by cutting them out by dicing or the like.
- a ceramic green sheet having a large area including a plurality of regions to be insulating members has a large amount of shrinkage at the time of firing, and the whole does not shrink uniformly and shrinks unevenly. It was. For example, a rectangular ceramic green sheet shrinks so that the vicinity of the center of each side is larger than the corner of the rectangle and enters inward.
- a large ceramic green sheet including a plurality of regions to be insulating members is pre-fired to form a single aggregate substrate, and a plurality of insulating green members are formed on the aggregate substrate.
- an insulating member is manufactured by setting a region and forming a through hole for each region by laser processing or the like and then cutting out each region.
- the through-holes formed are formed simultaneously with or before and after the step of forming the electrode layer by chemical plating, electric plating, or the like on the main surface side and the external connection surface side of the insulating member, respectively.
- a conductive layer connecting both electrode layers is formed.
- the through hole formed by laser processing is formed in a tapered shape in which the diameter gradually decreases from the laser incident side to the output side.
- the surface and the inner surface of the through hole intersect at an acute angle, and the portion of the corner that intersects at an acute angle has poor adhesion to the metallization formed by physical vapor deposition, printing, plating, etc., and the film thickness is not uniform. Therefore, when the electrode layer and the conductive layer are formed on the insulating member, there is a problem that connection failure between the electrode layer and the conductive layer is likely to occur.
- An object of the present invention is to manufacture a ceramic green sheet through a step of forming a through hole and then to form a conductive layer formed in the through hole and an electrode formed on a main surface or an external connection surface.
- An object of the present invention is to provide an assembly board that can be reliably connected to a layer without causing poor connection.
- Another object of the present invention is to provide a semiconductor element mounting member formed using an insulating member cut out for each region of the aggregate substrate, and an imaging device formed using the semiconductor element mounting member,
- An object of the present invention is to provide a semiconductor device such as a light emitting diode constituent member and a light emitting diode formed using the light emitting diode constituent member.
- a collective substrate of the present invention is a board in which one side is a main surface for mounting a semiconductor element and the opposite side is an external connection surface for connection to another member.
- a through hole penetrating in the thickness direction of the insulating member is formed in at least one of the positions straddling the line, and an inner surface forming each through hole is formed on the main surface side and the outer connection surface side. From the opening to the smallest hole provided in one place in the thickness direction of the insulating member
- the aggregate substrate of the present invention is preferably manufactured by firing a plate-like precursor as a base material and then forming through holes.
- the collective substrate of the present invention is used for connecting an electrode layer for mounting a semiconductor element formed on the main surface side of a region to be an insulating member and another member formed on the external connection surface side. It is preferable to provide an electrode layer and a conductive layer formed in the through hole and connecting the electrode layer on the main surface side and the electrode layer on the external connection surface side.
- the semiconductor element mounting member of the present invention is manufactured by cutting out the aggregate substrate of the present invention including the electrode layer and the conductive layer for each region.
- the semiconductor element mounting member of the present invention includes an insulating member in which a region for mounting a semiconductor element is set on a main surface, and a frame laminated on the main surface so as to surround the region. It is preferable that the thermal expansion coefficient of the insulating member and the frame body is 10 X 10-6 Z ° C or less, and the thermal expansion coefficient of the frame body and the thermal expansion coefficient of the insulating member are difference is preferably not more than 3 X 10- 6 Z ° C for.
- the semiconductor element mounting member of the present invention includes at least 80% of the area of the region for mounting the semiconductor element surrounded by the frame on the main surface of the insulating member, and includes at least an electrode layer for mounting the semiconductor element It is preferably covered with a metal layer.
- the imaging device of the present invention includes the semiconductor element mounting member of the present invention and the semiconductor element mounting.
- An image sensor as a semiconductor element mounted in a region surrounded by a frame on the main surface of the insulating member of the mounting member, and joined to the upper surface of the frame to seal the inside of the frame; And a lid that also serves as a translucent plate material.
- a semiconductor device of the present invention includes the semiconductor element mounting member of the present invention and a semiconductor element mounted on a main surface of an insulating member among the semiconductor element mounting members. Element force It is sealed with a sealing material.
- the semiconductor device of the present invention includes the electrode layer and the conductive layer, and the minimum hole portion of the through hole is filled with a conductive material forming the conductive layer, and the through hole is closed in the thickness direction.
- a semiconductor element is mounted on the main surface of each region of the collective substrate that is to be an insulating member, and then the entire surface of the collective substrate on the main surface side on which the semiconductor element is mounted is sealed with a sealing material.
- the collective substrate is manufactured by cutting out each region together with the sealing material, and at least a part of the through hole after cutting is formed on a side surface intersecting the main surface and the external connection surface of the insulating member.
- the semiconductor device of the present invention is characterized in that the semiconductor element is a light emitting element and the sealing material is at least one of a phosphor and a protective resin. It is what.
- the light emitting diode component of the present invention it is preferable that at least a part of the outermost surface of the electrode layer on the main surface of the insulating member is formed of Ag, A, or A1 alloy.
- the light-emitting diode of the present invention includes a package having a recess, the light-emitting diode component of the present invention mounted on the bottom surface of the recess of the package, and a seal for sealing the recess in the opening of the recess.
- V is provided with a sealing cap or a lens which has a material power capable of transmitting light of the light-emitting diode constituent member which is bonded.
- the inner surface forming the through hole has a minimum hole provided at one location in the thickness direction of the insulating member from the opening on the main surface side of the insulating member and the external connection surface side. Since each of the main surfaces, the external connection surface, and the inner surface of the through hole has an obtuse angle, the opening size is tapered so as to gradually decrease. Will be crossed. Therefore, according to the collective substrate of the present invention, physical vapor deposition, When forming electrode layers and conductive layers by printing, plating, etc., metallized peeling at the corners and uneven film thickness are greatly reduced, resulting in poor connection between the electrode layer and the conductive layer. Thus, the semiconductor device can be reliably connected and the reliability of the semiconductor device can be improved more than before.
- the thermal conductivity of the collective substrate of the present invention is lOWZmK or more, it is possible to increase the heat dissipation of the semiconductor element mounting member and cope with the higher output of the semiconductor element. Further, the thermal expansion coefficient of the collective substrate, 10 the X 10- 6 Z ° C below that, inflated by Netsu ⁇ history or the like of driving the device, subjected to any excessive stress to the semiconductor element when deflated, the device is It is possible to reliably prevent breakage or disconnection from the electrode layer to cause poor bonding.
- the aggregate substrate of the present invention is manufactured by firing a plate-like precursor such as a ceramic green sheet and then forming a through hole, the precursor is uneven.
- the uneven displacement of the through hole due to the contraction is eliminated.
- the electrode layer is formed on the main surface of the insulating member and the external connection surface of the collective substrate of the present invention, and the conductive layer is formed on the inner surface of the through hole, the electrode layer and the conductive layer are It is possible to connect securely without causing poor connection. Therefore, according to the semiconductor element mounting member of the present invention manufactured by cutting out the assembly board of the present invention for each region, the semiconductor element mounted on the main surface is divided between the two electrode layers and the conductive layer. It is possible to reliably connect to other members without causing poor connection or the like.
- the electrode layer is formed by a conventionally known method such as solder bonding or wire bonding. By various connection methods, it is possible to more securely and electrically connect to the electrode layer provided on the other member.
- a region for mounting a semiconductor element is set on the main surface of the insulating member, and a frame is formed on the main surface of the insulating member so as to surround the region. product
- the mounted semiconductor element can be sealed by bonding a lid on the frame body.
- the semiconductor element is an image sensor
- the image sensor is sealed in such a manner that the image sensor can be exposed through the lid by using a lid that also has a light-transmitting material force. can do.
- the coefficient of thermal expansion of the insulating member and the frame of the semiconductor element mounting member of the present invention is 10
- At least 80% of the area of the semiconductor element mounting member of the present invention for mounting the semiconductor element surrounded by the frame on the main surface of the insulating member is at least for mounting the semiconductor element.
- the semiconductor layer is covered with a metal layer including an electrode layer, for example, when the semiconductor element is an image pickup element, the metal layer functions as a light shielding layer, and light incident from behind the image pickup element through the insulating member is used.
- the sensitivity of the image sensor can be improved.
- the semiconductor element is a light emitting element, the light emitting efficiency of the light emitting diode can be improved by causing the metal layer to function as a reflective layer.
- the image pickup device of the present invention after mounting an image pickup device as a semiconductor element in a region surrounded by a frame on the main surface of the insulating member of the semiconductor element mounting member including the frame, Since it is configured by joining a lid that also serves as a translucent plate material on the frame, the image sensor can be sealed in a state where exposure through the lid is possible. it can.
- the semiconductor device of the present invention has a structure in which a semiconductor element is mounted on a main surface of a semiconductor element mounting member manufactured by cutting an aggregate substrate into each region and sealed with a sealing material. Therefore, it can be handled in the same way as a conventional chip of a semiconductor element, and can be mounted on a mounting portion of another member such as a wiring board. It is also possible to inspect for defects before mounting on the mounting part. Moreover, since it is not necessary to directly touch the semiconductor element during mounting work, it is possible to suppress the occurrence of damage to the element due to static electricity as much as possible.
- the semiconductor device of the present invention is mounted on the main surface of the semiconductor substrate using a collective substrate in which the minimum hole portion of the through hole is filled with a conductive material and closed in the thickness direction, and a sealing material Sealed
- the sealing material can be prevented from leaking to the opposite surface side through the through hole during the sealing. . Therefore, for example, a specific region on one side of the collective substrate on which one side of the semiconductor element is mounted can be omitted, and the entire surface can be protected with a sealing material. It becomes possible to promote further downsizing.
- the conductive layer formed on the inner surface of the exposed through hole is formed on the solder fillet. It can function as a formation part. For this reason, when the semiconductor device is mounted on the mounting portion of the other member by soldering, the formed solder fillet assists the external connection electrode layer, thereby improving the mounting reliability.
- the light-emitting diode component of the present invention uses a light-emitting element as a semiconductor element in the semiconductor device of the present invention, and at least one of a phosphor and a protective resin as a sealing material. Therefore, it is handled in the same way as a conventional light emitting element chip, and a mounting portion of a light emitting diode knock-out or a substrate of a surface light emitting body configured by arranging a large number of light emitting elements in a planar shape. It can be mounted on a mounting portion or the like. In addition, it is possible to determine whether the light emitting element is good or to check the color of light emission before mounting on these mounting portions. Furthermore, since it is not necessary to directly touch the light emitting element during the mounting operation or the like, the occurrence of damage to the element due to static electricity or the like can be suppressed as much as possible.
- the light-emitting diode constituent members of the present invention when at least a part of the outermost surface of the electrode layer on the main surface of the insulating member is formed of Ag, A, or A1 alloy, light from the light-emitting element is emitted.
- light having a wavelength of 600 nm or less which is suitable for emitting white light in combination with a phosphor, can be reflected to the front side of the light emitting diode component as efficiently as possible to improve the light emission efficiency.
- the light emitting diode of the present invention uses the light emitting diode component of the present invention, it can be efficiently manufactured without wasting the expensive light emitting diode.
- FIG. 1 is an enlarged plan view of a part of an aggregate substrate serving as an insulating member for mounting an image pickup device as an example of an embodiment of the aggregate substrate of the present invention.
- FIG. 2 is an enlarged cross-sectional view of a through hole portion in the collective substrate.
- FIG. 3 is an enlarged cross-sectional view of a through hole portion in an insulating member cut out from a collective substrate.
- FIG. 4 is a plan view showing the main surface side of the insulating member.
- FIG. 5 is a plan view showing a semiconductor element mounting member formed by joining a frame body on the main surface.
- FIG. 6 is a bottom view showing the external connection surface side of the insulating member.
- FIG. 7 shows a semiconductor element mounting member in which an image sensor as a semiconductor element is mounted on an element mounting region on the main surface of an insulating member, and a light-transmitting lid is mounted on the frame. It is sectional drawing of the imaging device formed by joining.
- FIG. 8 is an enlarged plan view of a part of the collective substrate serving as an insulating member for mounting a light-emitting element as another example of the collective substrate of the present invention.
- FIG. 9 is an enlarged cross-sectional view of a through hole portion in the collective substrate.
- FIG. 10 is an enlarged cross-sectional view of a through hole portion in an insulating member obtained by cutting out the collective substrate.
- FIG. 11 is a plan view showing the main surface side of the insulating member.
- FIG. 12 is a bottom view showing the external connection surface side of the insulating member.
- FIG. 13 shows a light-emitting diode constituent member in which a light-emitting element as a semiconductor element is mounted on the main surface of an insulating member of a semiconductor element mounting member and sealed with phosphor and Z or protective resin. It is sectional drawing.
- FIG. 14 is a cross-sectional view showing a light emitting diode in which a light emitting diode component is mounted on a package.
- FIG. 15 is a side view of the semiconductor element mounting member of the present invention as viewed from the direction of the arrow V in FIG. 17 in which the through hole portion is enlarged in another example of the embodiment.
- FIG. 16 is a side view showing a state of the same through hole before forming a conductive layer on the inner surface of the through hole.
- FIG. 17 is a plan view showing the main surface side of the semiconductor element mounting member of the above example.
- FIG. 18 is a bottom view showing the external connection surface side.
- FIG. 19 is an enlarged plan view of the through-hole portion before the insulating member that is the basis of the semiconductor element mounting member of the above example is cut out by the collective substrate.
- FIG. 20 is a cross-sectional view taken along line BB in FIG.
- FIG. 21 is an enlarged plan view of a deformed portion of a through hole.
- FIG. 22 is a cross-sectional view taken along line BB in FIG.
- FIG. 1 is an enlarged plan view of a part of the collective substrate 1 as an example of an embodiment of the collective substrate 1 according to the present invention, which is an insulating member 2 for mounting an image pickup device.
- . 2 is an enlarged cross-sectional view of a portion of the through hole 11 in the collective substrate 1
- FIG. 3 is an enlarged cross-sectional view of the portion of the through hole 11 in the insulating member 2 cut out of the collective substrate 1.
- is there. 4 is a plan view showing the main surface 21 side of the insulating member 2
- FIG. 5 is a plan view showing a semiconductor element mounting member BL formed by joining the frame body 4 on the main surface 21.
- 6 is a bottom view showing the external connection surface 22 side of the insulating member 2.
- FIG. 7 shows that the imaging element PE1 as a semiconductor element is mounted on the element mounting region 21a on the main surface 21 of the insulating member 2 of the semiconductor element mounting member BL, and a light-transmitting lid is provided on the frame body 4.
- 3 is a cross-sectional view of an imaging device PE2 formed by joining a body FL.
- the collective substrate 1 of this example is entirely formed in a flat plate shape by ceramic, and forms a predetermined planar shape (rectangular shape in the figure) to be a plate-like insulating member 2. ) And a constant width region lb for removal by dicing provided in a vertical and horizontal matrix between each region la so as to partition the plurality of regions la. Is included.
- a one-dot chain line in the figure is a boundary line L for partitioning the regions la and lb. Further, a plurality of (eight in the figure) through-holes 11 are formed across the boundary line L at positions corresponding to the two long sides parallel to each other in each region la! The
- the aggregate substrate 1 is manufactured by firing a ceramic precursor (ceramic green sheet or the like) as a base and forming it into a flat plate shape, and then forming through holes 11 by post-processing. I like it.
- a ceramic precursor ceramic green sheet or the like
- the through hole 11 can be formed with high positional accuracy, which is difficult to form with the conventional cofire method.
- each through hole 11 has two first and second surfaces, respectively.
- the taper surface is composed of l lb and 11c.
- the first tapered surface l ib is the smallest hole portion 11a having a circular planar shape provided at one position in the thickness direction of the insulating member 2 from the main surface 21 side (the upper surface side in the figure) of the insulating member 2.
- it is formed in a conical taper shape so that the opening diameter gradually decreases, and the main surface 21 opens in a circular shape.
- the second taper surface 11c is formed in a conical taper shape so that the opening diameter gradually decreases from the external connection surface 22 side (the lower surface side in the figure) of the insulating member 2 to the minimum hole portion 11a.
- the external connection surface 22 has a circular opening.
- Various methods can be considered as a method of forming the through-hole 11 having the shape shown in the figure on the assembled substrate 1 that has been previously baked and formed into a flat plate shape by post-processing. It is preferable to form by a method using a method. That is, with reference to FIGS. 1 and 2, the circular region corresponding to the opening of the through hole 11 on the external connection surface 22 side of the collective substrate 1 is exposed, and the other regions are protected with a resist film. Then, the exposed region of the aggregate substrate 1 is selectively perforated in the thickness direction by the sandblast method to form the second taper surface 11c.
- the circular region corresponding to the opening of the through hole 11 is exposed, and the other region is protected with a resist film, and the aggregate substrate 1 is formed by the sandblast method.
- the exposed area is selectively drilled in the thickness direction to form a 1 lb first tapered surface.
- the opening size becomes smaller as drilling progresses, so both tapered surfaces l lb and 11c are formed in a conical taper shape, and both tapered surfaces l
- the connecting portion of lb and 11c is the minimum hole portion 11a, and the through hole 11 is formed.
- the opening diameter of the minimum hole 11a and the thickness direction of the insulating member 2 of the minimum hole 11a are adjusted.
- the formation position can be arbitrarily controlled.
- the first tapered surface l ib and the main surface 21 continuous therewith intersect at an obtuse angle ⁇ , and the second tapered surface 11c and
- the corners of the first tapered surface l ib and the main surface 21 and the first 2 themes Separation of metallization and non-uniform film thickness at the corners of the par surface l ie and the external connection surface 22 can be greatly reduced, resulting in poor connection between the electrode layers 31 and 32 and the conductive layer 33. It becomes possible to make a reliable connection immediately. Therefore, it is possible to improve the reliability of the imaging device PE2.
- both tapered surfaces l lb and 11c intersect each other at an acute angle in the through hole 11, the adhesion of the metallization at the portion of the minimum hole 11a which is the corner of the both decreases, and the conductive layer 33 Force There is a risk of discontinuity at the minimum hole 11a or uneven metallization.
- both tapered surfaces l lb and 11c are also obtuse at an angle ⁇ .
- the aggregate substrate 1 preferably has a thermal conductivity of lOWZmK or more. If the thermal conductivity is 10W ZmK or more, it is possible to increase the heat dissipation of the semiconductor element mounting member BL and cope with higher output of the image sensor PE1. Furthermore, the collective substrate 1, the thermal expansion coefficient is preferably not less 10 X 10- 6 Z ° C. If the thermal expansion coefficient of less 10 X 10- 6 Z ° C, expansion due to heat history of when the device driving dynamic, excessive stress on the imaging element PE1 upon contraction Te Kuwawatsu, the element PE1 is broken Or disconnection can be prevented.
- Materials for forming the aggregate substrate 1 satisfying these conditions include A1N, Al 2 O, SiC, S
- the thermal conductivity of the collective substrate 1 is 80 WZmK or more, particularly 150 WZmK or more, even within the above range, in order to achieve a high thermal conductivity, A1N or SiC preferable. In view of reducing the difference in thermal expansion coefficient from the image sensor PE1, A1N or Al 2 O is preferable.
- the aggregate substrate 1 is preferably formed by 2 3. However, considering the balance between the mechanical strength and other physical properties of the collective substrate 1 or the manufacturing cost, the collective substrate 1
- the thermal conductivity in the range of the, in particular, preferred instrument thermal expansion coefficient not more than 300WZmK also within the scope of the, in particular, 4 X 10- 6 ⁇ 7 X 10- 6 Z ° C
- 4 X 10- 6 ⁇ 7 X 10- 6 Z ° C Preferably
- the main surface 21 of the collective substrate 1 has an electrode layer 31 for mounting a semiconductor element
- the external connection surface 22 has an electrode layer 32 for connection to other members
- the inner surface of the through hole 11 has both A conductive layer 33 that connects the electrode layers 31 and 32 is formed (FIGS. 1 to 6).
- each electrode layer 31 on the main surface 21 side is formed independently corresponding to each through hole 11. Further, in the example shown in the figure, each electrode layer 31 has another one from the through hole 11 formed at a position corresponding to one of the two long sides of the rectangular parallel to each other in the region la to be the insulating member 2. It is formed in a rectangular shape extending in the direction of the long side of the side.
- the electrode layer 32 on the external connection surface 22 side is also formed independently corresponding to each through hole 11 with a plurality of forces, and each electrode layer 32 is mutually connected in the region la that becomes the insulating member 2.
- the conductive layer 33 is formed so as to cover the entire inner surface of the through hole 11 and to be connected to the electrode layer 31 on the main surface 21 side of the collective substrate 1 and the electrode layer 32 on the external connection surface 22 side. .
- the metal layer 5 is formed on the main surface 21 in a state where a gap g is provided so as not to contact each electrode layer 31.
- the metal layer 5 together with the electrode layer 31 functions as a light-shielding layer that covers the region 21a for mounting the semiconductor element surrounded by the frame body 4 in the main surface 21. That is, the metal layer 5 is used to improve the sensitivity of the image sensor PE1 by blocking light incident from behind the image sensor PE1 mounted in the region 21a through the insulating member 2.
- the electrode layer 31 and the metal layer 5 are preferably formed so as to cover 80% or more of the area of the region 21a. Thereby, the electrode layer 31 and the metal layer 5 can sufficiently function as a light shielding layer.
- the plurality of electrode layers 31 need to be separated from each other, and the metal layer 5 needs to be separated from each electrode layer 31. Therefore, a gap g is always required between the electrode layer 31 and the metal layer 5, and 100% of the area of the region 21 a, that is, the entire surface of the region 21 cannot be covered with the electrode layer 31 or the metal layer 5. In consideration of securing a sufficient gap g between the electrode layer 31 and the metal layer 5 to prevent a short circuit between the plurality of electrode layers 31.
- the pole layer 31 and the metal layer 5 are preferably formed so as to cover 95% or less of the area of the region 21a.
- Each electrode layer 31 may be formed to be large so as to cover 80 to 95% of the area of the region 21a, and the metal layer 5 may be omitted.
- the electrode layers 31, 32 and the conductive layer 33 can all be formed of various conventionally known metal materials having excellent conductivity. Each layer is formed into a single layer structure or a multilayer structure of two or more layers using various metallization methods such as a wet plating method or a physical vapor deposition method such as a vacuum deposition method or a sputtering method. be able to. In the wet plating method, since a metal film having a sufficient thickness can be formed by a single treatment, the electrode layers 31, 32 and the conductive layer 33 may be formed in a single layer structure. A multilayer structure in which a surface layer with a thickness of 0.1-: LO / zm is laminated on one or two underlayers of Cu or M, which also has excellent metallic power such as Ag and Au. It may be formed.
- the electrode layers 31, 32 and the conductive layer 33 are formed in a multilayer structure in which a plurality of functionally separated layers are stacked. In order from the closest side to the collective board 1,
- the thickness of the adhesion layer is preferably about 0.01 to 1. O / zm, the thickness of the diffusion prevention layer is about 0.01-1 and the thickness of the surface layer is preferably about 0.1 to about LO / zm.
- the electrode layers 31 and 32 and the conductive layer 33 may be formed in a multilayer structure by combining physical vapor deposition and wet plating.
- an underlayer that also contains Cu and N is formed by wet plating, and further, Ag, It is possible to form a surface layer made of Al, Au or the like having excellent conductivity.
- the surface of the electrode layer 31 on the main surface 21 side is, for example, connected to each terminal of the mounted image sensor PE1.
- bonding pads such as Au may be provided.
- the surface of the electrode layer 32 on the external connection surface 22 side is, for example, soldered between the electrode layer provided on the substrate of a digital camera or the like to improve the reliability when surface mounting. It is also possible to provide an anti-solder joint layer that also has Au force.
- the electrode layers 31 and 32 having a single-layer structure are formed or arranged on the outermost layer of the electrode layers 31 and 32 having a multilayer structure. If present, the bonding pad and the solder joint layer may be omitted.
- the metal layer 5 since the metal layer 5 is formed on the same surface as the electrode layer 31, it may be formed so as to have the same layer configuration at the same time as the electrode layer 31 is formed. However, since the metal layer 5 only needs to function as a light shielding layer, for example, even when the electrode layer 31 is formed in a multilayer structure as described above, the metal layer 5 has a sufficient thickness. It may be formed in a single layer structure having only one layer.
- a metal mask or a mask formed by photolithography is used to expose the uncovered aggregate without being covered with the mask.
- the surface of the substrate 1 may be selectively metallized by the wet plating method or physical vapor deposition method. Further, in order to make the electrode layers 31 and 32 have a multilayer structure, metallization with different metals may be repeated on the exposed surface of the insulating member 1.
- the conductive layer 33 is formed when the electrode layer 31 or the metal layer 5 is formed on the main surface 21, or when the electrode layer 32 is formed on the external connection surface 22, or when both the operations are performed. By leaving the opening of the through hole 11 exposed without being covered with a mask, it is possible to form both the electrode layers 31 and 32 and the electrode layers 31 and 32 at the same time.
- a semiconductor element mounting member BL for mounting the imaging element PE1 as a semiconductor element is manufactured.
- the region lb defined by the boundary line L in the collective substrate 1 is removed by dicing or the like.
- the remaining region la is separated apart, and a plurality of insulating members 2 are formed.
- the frame body 4 is bonded onto the main surface 21 of each formed insulating member 2 via a bonding layer B1 made of, for example, a low-melting glass or the like, a frame on the main surface 21 is formed.
- the region 21a exposed through the through-hole 41 of the body 4 is taken as a semiconductor element.
- a semiconductor element mounting member BL, which is an element mounting portion for mounting the image element PE1, is manufactured (FIGS. 4 to 7).
- a collective substrate that includes a plurality of regions to be the frame 4 in which a plurality of through holes 41 are arranged in accordance with the formation interval of the region la of the collective substrate is prepared.
- 32, the conductive layer 33, and the metal layer 5 are joined to the main surface 21 side of the collective substrate 1 through the joining layer B1, and then the region lb of the collective substrate 1 and the assembly to be the frame 4 Even if the region of the substrate overlapping the region lb is removed by dicing or the like, a plurality of semiconductor element mounting members BL in which the insulating member 2 and the frame body 4 are laminated can be manufactured.
- the frame body 4 has a thermal expansion coefficient in consideration of preventing the occurrence of deformation such as warpage in the state of being laminated with the insulating member 2, and reducing the difference in thermal expansion coefficient from the semiconductor element.
- the frame body 4 is formed of the same material as the insulating member 2 so that the difference in thermal expansion coefficient is completely eliminated.
- the frame 4 is also preferably made of A1N.
- the body 4 is also preferably made of Al 2 O.
- the frame 4 has a semiconductor element as an imaging element.
- the light shielding material in order to block unnecessary light incident through the frame 4, it is preferable to form the light shielding material.
- an imaging device PE2 of the present invention has an imaging element PE1 mounted in a region 21a of the semiconductor element mounting member BL, and a terminal (not shown) of the imaging element PE1.
- a terminal (not shown) of the imaging element PE1.
- the tip of the electrode layer 31 exposed in the region 21a is connected via the wire bonding WB, it is formed on the frame body 4 via a bonding layer B2 made of a resin such as low-melting glass.
- the lid FL made of a translucent material is joined.
- the imaging element PE1 can be sealed in a state where the imaging element PE1 can be exposed through the lid FL.
- Each terminal of the image sensor PE1 is connected to an electrode layer or the like provided on a substrate of a digital camera or the like via a wire bonding WB, an electrode layer 31, a conductive layer 33, and an electrode layer 32.
- FIG. 8 shows a light emitting device mounting example as another example of the embodiment of the collective substrate 1 of the present invention.
- 3 is an enlarged plan view of a part of the collective substrate 1 that is the basis of the insulating member 2.
- FIG. FIG. 9 is an enlarged cross-sectional view of the through-hole 11 portion of the collective substrate 1.
- FIG. 10 is an enlarged cross-sectional view of the through-hole 11 portion of the insulating member 2 cut out of the collective substrate 1.
- FIG. 11 is a plan view showing the main surface 21 side of the insulating member 2
- FIG. 12 is a bottom view showing the external connection surface 22 side. Further, FIG.
- FIG. 13 shows a case where the light emitting element LE1 as a semiconductor element is mounted on the main surface 21 of the insulating member 2 of the semiconductor element mounting member BL, and the phosphor and Z or protective resin FR as a sealing material.
- FIG. 14 is a cross-sectional view showing a light-emitting diode LE3 in which the light-emitting diode constituent member LE2 is mounted on the package 7.
- the collective substrate 1 of this example is still formed in a flat plate shape by ceramic, and has a predetermined planar shape (rectangular in the figure) that becomes a plate-like insulating member 2.
- a one-dot chain line in the figure is a boundary line L for partitioning the regions la and lb.
- a plurality of (three in the figure) through-holes 11 are formed at positions corresponding to two sides in the vertical direction in the figure, which are parallel to each other, in each region la. It is formed in the vicinity of
- the aggregate substrate 1 is formed by firing a ceramic precursor (ceramic green sheet or the like) to form a flat plate, and then forming the through holes 11 by post-processing. Preferably, it is formed. As a result, the through hole 11 can be formed with high positional accuracy, which is difficult to form with the conventional cofire method.
- the electrode layers 31 and 32 and the conductive layer 33 are also preferably formed on the surface of the aggregate substrate 1 after firing. In this case, an A1 layer, which has excellent light reflectivity but was difficult to form on the underlayer made of Mo, W, or the like formed by the cofire method by the plating method, is used for the electrode layer 31. Etc. can also be formed.
- each through hole 11 is composed of first and second tapered surfaces l lb and 11c, respectively.
- the first taper surface l ib extends from the main surface 21 side of the insulating member 2 (upper surface side in the figure) to one location in the thickness direction of the insulating member 2.
- the provided planar shape is formed in a conical taper shape so that the opening diameter gradually decreases toward the circular hole 11a having a circular shape, and the main surface 21 opens in a circular shape.
- the second taper surface 11c is formed in a conical taper shape so that the opening diameter gradually decreases from the external connection surface 22 side (the lower surface side in the figure) of the insulating member 2 to the minimum hole portion 11a.
- the external connection surface 22 has a circular opening.
- the electrode layers 31 and 32 and the conductive layer 33 When the electrode layers 31 and 32 and the conductive layer 33 are formed, the corners of the first tapered surface l ib and the main surface 21 and the corners of the first tapered surface 11c and the external connection surface 22 are formed. Metallization separation and film thickness non-uniformity can be greatly reduced. Therefore, the electrode layers 31 and 32 and the conductive layer 33 can be securely connected without causing poor connection, and the reliability of the light emitting diode component LE2 and the light emitting diode LE3 can be improved. It becomes.
- the partial force of the minimum hole portion 11a is filled by the deposition of the conductive material 33a that forms the conductive layer 33.
- the assembly substrate 1 is closed in the thickness direction.
- the light emitting element LE1 mounted on the main surface 21 of each insulating member 2 of the collective substrate 1 is replaced with the phosphor and Z or protective resin FR as a sealing material.
- the phosphor and Z or the protective resin FR can be prevented from leaking to the back surface of the collective substrate 1 through the through holes 11.
- both the taper surfaces l lb and 11c also intersect at an obtuse angle of 0. Both tapers
- the second tapered surface 11c includes a region la of the aggregate substrate 1 that becomes the insulating member 2, and a region lb between the regions la. Is formed at a position across the boundary line L. Then, when the region lb is removed by dicing or the like and each region la is cut out, the second taper is formed on the side surface 23 of the insulating member 2 constituting the semiconductor element mounting member BL as shown in FIGS. The conductive layer 33 force formed on the inner surface of the surface 11c is exposed through the opening l id.
- the exposed conductive layer 33 is caused to function as a solder fillet forming portion, and the light emitting diode component LE2 is mounted on another member, for example, the package 7 of the light emitting diode LE3 shown in FIG. 14 by soldering.
- the formed solder fillet assists the electrode layer 32 for external connection, and the mounting reliability can be improved.
- the formation by the sand blast method described above is used as a method of forming the through-hole 11 having a strong shape by post-processing on the aggregate substrate 1 that has been baked and formed into a flat plate shape.
- the method is preferably employed.
- the opening diameter of the minimum hole 11a and the formation position of the minimum hole 11a in the thickness direction of the insulating member 1 are determined. It can be controlled arbitrarily.
- the formation position in the thickness direction of insulating member 2 of minimum hole portion 11a controlled as described above is represented by a distance h from main surface 21 to minimum hole portion 11a.
- the thickness exceeds 0 times the thickness t of the insulating member 2 and is 2/3 times or less.
- taper surfaces l lb and 11c are secured above and below the minimum hole portion 11a, and the first taper surface l ib and the main surface 21 are crossed at an obtuse angle ⁇ , and the second taper surface 11c Outside
- the connecting surface 22 can intersect at an obtuse angle ⁇ and formed on it.
- the electrode layers 31, 32 and the conductive layer 33 can be reliably connected.
- the exposed area of the conductive layer 33 on the second tapered surface 11c which is continuous with the electrode layer 32 on the side of the external connection surface 22 from the minimum hole portion 11a, is secured, and is sufficient as a solder fillet formation portion. It can also be made to function.
- the through hole 11 may be deformed by connecting the first and second tapered surfaces l lb and 11c formed from both sides of the collective substrate 1 by the formation method using the sandblast method. It can also be formed reliably.
- the conductive layer 33 functioning as a solder fillet forming portion on the second tapered surface 11c.
- the distance h is the thickness t of the insulating member 2.
- the force is less than 1Z2 times 0. Further, in order to reliably form the through hole 11 by the above forming method, the distance h is more preferable than a force of about 5 m to 50 m.
- the opening diameter d of the minimum hole portion 11a is preferably 10 ⁇ m or more.
- the minimum hole portion 11a having an opening diameter d of 10 / z m or more can be formed with relatively high accuracy when the through hole 11 is formed by a normal processing method such as the sandblast method. It is also possible to form each through hole 11 with the opening diameter d of the minimum hole portion 11a aligned, and no separate processing steps are required to form the minimum hole portion 11a. Therefore, the productivity of the semiconductor element mounting member BL can be improved and the cost can be reduced.
- the opening diameter d of the minimum hole portion 11a is preferably 200 m or less. If the opening diameter d is 200 m or less, when the conductive layer 33 is formed on the inner surface of the through hole 11, the minimum hole portion 11a can be filled with the conductive material 33a more efficiently. And Z or protective grease FR can be prevented more reliably.
- the opening diameter d of the above-mentioned / J hole ⁇ lla is 50 to 150 111. 75-125 / ⁇ ⁇ is even more preferable.
- the collective substrate 1 preferably has a thermal conductivity of lOWZmK or more. It is preferably 80 WZmK or more, particularly 150 WZmK or more. In consideration of the balance with other physical properties such as mechanical strength and the manufacturing cost, the thermal conductivity of the aggregate substrate 1 is preferably 300 WZmK or less.
- the thermal expansion coefficient of the collective substrate 1 is a 4 X 10- 6 ⁇ 7 X 10- 6 / ° C Is preferred.
- Materials for forming the aggregate substrate 1 satisfying these conditions include A1N, Al 2 O, SiC, S
- Insulating ceramics such as iN, BeO, and BN. Above all, especially high heat
- A1N and Al 2 O are preferable in order to reduce the difference in thermal expansion coefficient from the light-emitting element LE1 in which A1N and SiC are preferred. Furthermore, if cost is the top priority
- the main surface 21 of the collective substrate 1 has an electrode layer 31 for mounting a semiconductor element, and the external connection surface 22 has an electrode layer 32 for connection with another member, penetrating therethrough.
- a conductive layer 33 that connects the electrode layers 31 and 32 is formed.
- the minimum hole portion 11a of the through hole 11 is filled by depositing the conductive material 33a forming the conductive layer 33, and the through hole 11 before cutting out the insulating member 2 is formed in the collective substrate 1.
- the state is closed in the thickness direction.
- the thickness t in the thickness direction of the collective substrate 1 filled with the conductive material 33a in the minimum hole portion 11a is preferably 1Z50 to 1Z2 times the thickness t of the collective substrate 1. Thickness t 1S set
- the thickness t of the substrate 1 is 1Z50 or more, it was closed due to its weight during sealing.
- the exposed area of the conductive layer 33 functioning as a solder fillet forming portion is further increased, and at the time of sealing, the closed through-hole 11 is removed due to its weight and the like, and the phosphor and Z or protection Even more reliably, the oil FR leaks to the external connection surface 22 side.
- the thickness t in the thickness direction of the aggregate substrate 1 filled with the conductive material 33a in the minimum hole portion 11a is 1Z20 to 1Z5 times the thickness t of the aggregate substrate 1.
- the thickness t of the conductive layer 33 formed on the inner surface of the through hole 11 is 0 of the opening diameter d of the minimum hole portion 11a.
- Thickness t force Opening diameter If it is more than 0.2 times d, it penetrates
- the minimum hole portion 11a can be filled with the conductive material 33a more efficiently, so that leakage of phosphor and Z or protective resin FR can be more reliably performed. It becomes possible to prevent.
- the thickness t is 1.0 times or less of the opening diameter d.
- the thickness t of the conductive layer 33 is 0.3 to 0.5 times the opening diameter d of the minimum hole 11a, considering that the minimum hole 11a is filled with the conductive material 33a more efficiently.
- the electrode layers 31 for mounting semiconductor elements are formed on the side of the main surface 21 of the region la to be the individual insulating members 2 of the collective substrate 1, two by two in the plane direction. It is provided in an isolated state. Further, the electrode layer 32 for external connection is formed on the external connection surface 22 side of the region la to be the individual insulating members 2 of the collective substrate 1, and two electrode layers 32 are separated from each other in the surface direction. By doing so, it is provided in an insulated state.
- the two electrode layers 31 on the main surface 21 side and the two electrode layers 32 on the external connection surface 22 side correspond to each other on both the front and back surfaces of the collective substrate 1. 32 are connected via the conductive layer 33 on the inner surface of the through hole 11 formed at three locations on the outer peripheral edge side of the region la to be the insulating member 2.
- the electrode layer 31 whose planar shape is formed in a substantially rectangular shape, and the main surface 21 of the through-hole 11 extended from the one side 31a of the electrode layer 31 in the direction of the through-hole 11
- the extended electrode layer 3 lb reaching the periphery of the opening on the side and the conductive layer 33 on the inner surface of the through hole 11 are integrally formed and connected to each other.
- the electrode layer 32 having a substantially rectangular planar shape and partially overlapping with the opening of the through hole 11 on the external connection surface 22 side, and the inner surface of the through hole 11
- the conductive layer 33 is integrally formed and connected to each other.
- the ratio of the total area of the electrode layer 32 provided on the external connection surface 22 to the area of the external connection surface 22 is preferably 30% or more.
- the light-emitting diode component LE2 is placed between the electrode layer 32 on the external connection surface 22 side of the semiconductor element mounting member BL and the electrode layer provided on the substrate 7 of the light-emitting diode LE3 or the surface light emitter.
- surface-mounting by soldering it is possible to secure a sufficient heat dissipation path between the semiconductor element mounting member BL and the package 7 or substrate, so that it is possible to increase the output of the light emitting diode LE3. Become.
- the ratio of the total area of electrode layer 32 to the area of external connection surface 22 is preferably 50% or more. More preferably, it is 70% or more. However, in consideration of ensuring sufficient insulation between the electrode layers 32 when the two or more electrode layers 32 are formed apart from each other in the plane direction as described above, the electrode layers 32 The ratio of the total area to the area of the external connection surface 22 is preferably 90% or less.
- the electrode layers 31 and 32 and the conductive layer 33 can be formed in a single layer structure or a multilayer structure of two or more layers using a metal material having excellent conductivity, as described above. .
- a metal material having excellent conductivity as described above.
- the surface of the electrode layer 31 is made of Ag, A or A1 alloy, etc., for reflecting light from the light emitting element LE1, particularly light with a short wavelength of 6 OOnm or less with high reflectance. You can provide a reflective layer! ⁇ .
- A1 is particularly excellent in the reflectance of light having a short wavelength of 450 nm or less, and is preferable in terms of improving the light emission efficiency of the light emitting element LE1 having a short wavelength, which is used for emitting white light in combination with a phosphor. .
- a reflective layer May be omitted.
- the above-described anti-solder bonding layer having the same Au force may be formed on the surface of the electrode layer 32, or the electrode layer 32 having a single-layer structure is formed using Au as a conductive material.
- the solder bonding layer may be omitted by arranging it on the outermost layer of the electrode layer 32 having a multilayer structure.
- a semiconductor element mounting member BL for mounting a light emitting element LE1 as a semiconductor element is manufactured using the aggregate substrate 1, and a light emitting diode component LE2 is manufactured on the aggregate substrate 1 in order to manufacture the light emitting diode component LE2.
- the light emitting element LE1 is mounted on the electrode layer 31 in each included region la, and the entire surface of the collective substrate 1 is sealed with a phosphor and / or a protective resin FR as a sealing material. Thereafter, the region lb of the collective substrate 1 is removed by dicing or the like. As a result, the remaining region la is separated into pieces to form the semiconductor element mounting member BL, and at the same time, the light emitting diode component LE2 shown in FIG. 13 is obtained.
- the light emitting element LE1 is mounted by soldering the electrode layer 31 of the semiconductor element mounting member BL and the electrode layer (not shown) of the light emitting element LE1 through the solder layer SL.
- a solder used for mounting the light emitting element LE1 in consideration of mounting the light emitting diode component LE2 on the cage 7 or the substrate in a later process, a relatively high melting point Au— It is preferable to use Sn-based, Au-Ge-based, Au-Si-based solder or the like.
- the light emitting element LE1 may be mounted on the semiconductor element mounting member BL using an Au bump that is soldered.
- the light emitting element LE1 and the electrode layer 31 may be connected by wire bonding.
- the protective resin for sealing the light emitting element LE various conventionally known protective resins such as epoxy and silicone can be used.
- a silicone-based resin is preferable.
- the phosphor include various conventionally known phosphors that can emit white light in combination with the light emitting element LE1 that emits light having a wavelength of 600 nm or less, particularly 450 nm or less.
- the light emitting element LE1 mounted on the electrode layer 31 is first sealed with the phosphor and then sealed with the protective resin so as to cover the phosphor. . It can also be sealed with a mixture of phosphor and protective resin.
- the area of the semiconductor element mounting member BL ie, in this example, the area of the main surface 21 and the external connection surface 22 of the insulating member 2 is the area of the light emitting element LE1 mounted on the main surface 21 (main surface 21
- the projected area is preferably 1.1 to 4 times. If the area of the semiconductor element mounting member BL exceeds four times the area of the light emitting element LE1, its outer shape should be made as small as possible to save space.
- the light-emitting diode component BL2 formed by mounting the light-emitting element LE1 on the main surface 21 side of the semiconductor element mounting member BL is replaced with a conventional light-emitting element chip 1 While being handled as one member, there is a risk that it will not be possible to embed it in the light emitting diode LE3 knock 7 or mount it on the substrate of the surface light emitter.
- the waste of material generated when the semiconductor element mounting member BL becomes too large and the light emitting element LE1 is defective may be almost the same as in the case of the conventional knocker.
- the insulating member 2 having high heat conductivity and high material strength described above is expensive, it is preferable to reduce the area as much as possible even within the above range. That is, the area of the semiconductor element mounting member BL is preferably 3.5 times or less of the area of the light emitting element LE1, even within the above range, in consideration of eliminating waste of materials. 3. More preferably, it is 0 times or less.
- the area of the semiconductor element mounting member BL is less than 1.1 times the area of the light emitting element LE1, the mounting operation of the light emitting element LE1 may be difficult. In particular, there is a possibility that sealing with a protective grease or the like on the side surface of the light emitting element LE1 is insufficient. In consideration of improving the mounting workability and sealing the light emitting element LE1 more securely with protective grease, the area of the semiconductor element mounting member BL is within the above range. In particular, the area of the light emitting element LE1 is preferably 1.3 times or more, and more preferably 1.5 times or more.
- the thickness of the insulating member 2 is preferably 0.1 to lmm in consideration of making the volume of the semiconductor element mounting member BL as small as possible while ensuring sufficient strength. More preferably, it is 0.5 mm.
- a surface light emitter can be constituted.
- the light emitting diode component LE2 can also be used as the final form of the light emitting diode device. For example, it may be soldered to a desired position on a circuit board such as a printed circuit board or a backlight constituent member of a liquid crystal by a method such as reflow to function as a light emitting diode.
- the light-emitting diode component LE2 has a recess 7a. Mounted on the two electrode layers 72 provided on the bottom surface of the recess 7a of the receptacle 7, and the opening 7b of the recess 7a is made of a material that can transmit light from the light emitting diode component LE2. Light-emitting diode LE3 can be obtained by sealing with cap or lens LS
- the light emitting diode component LE2 is mounted by soldering the electrode layer 32 of the semiconductor element mounting member BL and the electrode layer 72 of the socket 7 via the solder layer SL1. At that time, a part of the melted solder is formed on the inner surface of the second tapered surface 11c in the through hole 11 and wraps around the conductive layer 33 exposed on the side surface 23 of the insulating member 2, so that the solder fillet SL2 is formed. Since it is formed, the mounting reliability is improved.
- the substrate / cage 7 has a substrate 70 on which an electrode layer 72 is formed on the upper surface side, and a reflecting member 71 having a through-hole that is laminated on the substrate 70 and serves as a recess 7a.
- the through hole of the reflecting member 71 is formed in a mortar shape extending outward from the bottom surface side toward the opening 7b side, and its inner surface is a reflecting surface 71a. Then, the light from the light emitting diode component LE2 can be reflected in the direction of the opening 7b by the surface of the reflecting surface 71a, and can be radiated more efficiently to the outside of the knock 7 through the lens LS.
- the substrate 70 an insulating and heat-resistant substrate such as a ceramic substrate or a glass epoxy substrate is used. Further, as the reflecting member 71, in order to efficiently reflect the light from the light emitting diode constituting member LE2, the whole or at least the reflecting surface 71a is made of metal.
- the through hole 11 shown in FIG. 9 may be formed at a position where the entirety of the through hole 11 enters the region la of the collective substrate 1.
- the conductive layer 33 formed on the tapered surface 11c does not need to function as a solder fillet forming portion. Therefore, the through hole 11 may be completely filled with the conductive material 33a.
- FIG. 15 is an enlarged side view of the through hole 11 in another example of the semiconductor element mounting member BL of the present invention, as viewed from the direction of the arrow V in FIG. 17, and FIG. 3 is a side view showing a state of the same through hole 11 before forming a conductive layer 33 on the inner surface of the through hole 11.
- FIG. Fig. 17 is a plan view showing the main surface 21 side of the semiconductor element mounting member BL of the above example
- Fig. 18 is an external view. It is a bottom view showing the connection surface 22 side.
- FIG. 19 is a plan view in which the portion of the through hole 11 is enlarged before the insulating member 2 that is the basis of the semiconductor element mounting member BL of the above example is cut out from the collective substrate 1, and FIG. FIG.
- semiconductor element mounting member BL of this example is configured in substantially the same manner as the examples of FIGS. 8 to 14 except for the shape of through hole 11. That is, referring to FIG. 17 and FIG. 18, the semiconductor element mounting member BL of this example has one side of the main surface 21 for mounting the light emitting element, and the opposite side the external connection surface for connection to other members. 2 for mounting light-emitting elements provided in an insulated state by being formed on the main surface 21 of the rectangular flat plate-shaped insulating member 2 and the main surface 21 of the insulating member 2 that are spaced apart from each other in the surface direction.
- Two electrode layers 31 and two electrode layers 32 for connection to other members provided in an insulated state by being formed on the external connection surface 22 so as to be spaced apart from each other in the surface direction. .
- the two electrode layers 31 on the main surface 21 side and the two electrode layers 32 on the external connection surface 22 side correspond to each other on both the front and back surfaces of the insulating member 2.
- the electrode layer 31 that covers the entire surface of the main surface 21 and the inner surface of the through-hole 11 except that the planar shape is substantially rectangular and there is a gap having a constant width between the two electrode layers 31.
- the conductive layer 33 is integrally formed and connected to each other.
- the planar shape of the electrode layer 32 is formed in a substantially rectangular shape, and the electrode layer 32 extends from one side 32a of the electrode layer 32 in the direction of the through hole 11 so that the through hole 11 on the external connection surface 22 side.
- the extended electrode layer 32b reaching the periphery of the opening and the conductive layer 33 on the inner surface of the through hole 11 are integrally formed and connected to each other.
- a collective substrate 1 having a size including a plurality of insulating members 2 is prepared, and the collective substrate 1 is divided into a plurality of regions la that become insulating members 2 by boundary lines L.
- the through hole 11 is formed at a predetermined position, the electrode layer 31 is formed on one side, the electrode layer 32 is formed on the opposite side, the conductive layer 33 is formed on the inner surface of the through hole 11, and the light emitting element LE1 is further formed on the electrode layer 31.
- each through hole 11 is the first and second tapered surfaces l lb, 11c, respectively. It is configured.
- the first tapered surface l ib opens from the main surface 21 side of the insulating member 2 (upper surface side in the drawing) from the other part of the through hole 11 provided at one location in the thickness direction of the insulating member 2. It is formed in a tapered shape so that the opening width gradually decreases toward the smallest hole portion 11a having a small width d and a flat surface shape having an oval shape, and the main surface 21 is opened in an oval shape.
- the second taper surface 11c is formed in a taper shape so that the opening width gradually decreases from the external connection surface 22 side (the lower surface side in the figure) of the insulating member 2 to the minimum hole portion 11a. At the same time, the external connection surface 22 is opened in an oval shape.
- the through hole 11 includes two regions la to be the semiconductor element mounting members BL defined by the boundary line L on the collective substrate 1, and a region lb to be removed between them by dicing or the like. It is formed across. Then, when the conductive layer 33 is formed on the inner surface of the through hole 11, the portion of the minimum hole portion 11a is filled by the deposition of the conductive material 33a forming the conductive layer 33, and the through hole 11 is formed as shown in FIG. In the state before cutting shown in FIG. 20, the assembled substrate 1 is closed in the thickness direction.
- the side surface 23 of the insulating member 2 constituting the semiconductor element mounting member BL is shown in FIGS.
- the conductive layer 33 formed on the inner surface of the second tapered surface 11c is exposed through the opening l id. Therefore, when the exposed conductive layer 33 is made to function as a solder fillet forming portion, the light emitting diode component LE2 is mounted on another member, for example, the package 7 of the light emitting diode LE3 by soldering. By the formed solder fillet, outside It is possible to improve the mounting reliability by assisting the electrode layer 32 for connection of parts.
- the through hole 11 having the shape shown in the figure is preferably formed by the sandblast method.
- the shape of the region exposed without being protected by the resist film corresponding to the opening of the through hole 11 is made into an oval shape, and the assembly is performed by the sand plast method.
- the exposed region of the substrate 1 is selectively perforated in the thickness direction to form the second tapered surface 11c, and similarly on the opposite surface side, which is the main surface 21, to the opening of the through hole 11.
- the exposed area of the aggregate substrate 1 is selectively perforated in the thickness direction by the sandblasting method using the oval shape of the area exposed without being protected by the resist film, and the first tapered surface.
- the feature of the drilling by the sandblast method is that the opening size becomes smaller as the drilling progresses, so that the through hole 11 having the shape shown in FIGS. 19 and 20 is formed.
- each part of the through hole 11 are preferably set in the same range for the same reason as in the previous example. That is, referring to FIGS. 15 and 16, the formation position of the minimum hole portion 11a in the thickness direction of the insulating member 2 is represented by the distance h from the main surface 21 to the minimum hole portion 11a, and The thickness t of the insulating member 1 is preferably in the range of more than 0 times the thickness t and 2Z3 times or less.
- the opening width d of the minimum hole portion 11a is preferably 10 to 200 m, more preferably 50 to 150 ⁇ m, and even more preferably 75 to 125 ⁇ m. Yes.
- the opening width d referred to here is an oblong shape corresponding to a shape in which a semicircle is connected to both ends of a rectangular central portion, in a direction perpendicular to the center line connecting the centers of the semicircles on both ends. It refers to the width.
- the thickness t in the thickness direction of the insulating member 2 filled with the conductive material 33a in the minimum hole portion 11a is preferably 1Z50 to 1Z2 times the thickness t of the insulating member 1 1Z20 ⁇ : LZ5
- the thickness t of the conductive layer 33 formed on the inner surface of the through hole 11 is preferably 0.2 to 1.0 times the opening width d of the smallest hole portion 11a. Double
- each part other than the through hole 11 are preferably set in the same range for the same reason as in the previous example. That is, the area of the main surface 21 and the external connection surface 22 of the insulating member 2 is the same as the main surface 21.
- the area of the light emitting element LEI to be mounted (projected area on the main surface 21) is preferably 1.1 to 4 times, 1.
- the force is 3 to 3.5 times S, more preferably 1. It is even more preferable than the force S of 5 to 3.0 times.
- the thickness of the insulating member 2 is preferably 0.1 to lmm, and more preferably 0.2 to 0.5 mm.
- the ratio of the total area of the electrode layers 32 provided on the external connection surface 22 to the area of the external connection surface 22 is preferably 30% or more, and more preferably 50% or more. More preferably, it is 70% or more. Further, the ratio is preferably 90% or less.
- the electrode layers 31 and 32 and the conductive layer 33 are each made of various known metal materials having excellent conductivity, such as a wet plating method, or a physical vapor deposition method such as a vacuum vapor deposition method or a sputtering method. Various metallization methods can be used to form a single layer structure or a multilayer structure of two or more layers.
- the electrode layer 31 preferably has at least its surface formed of Ag, A or A1 alloy, etc.
- the electrode layer 32 preferably has at least its surface formed of Au.
- insulating member 2 has a thermal conductivity of more than LOWZmK, thermal expansion coefficient of 10 X 10- 6 Z ° half of this example includes a preferred instrument ceramic insulating member 2 to form the C following ceramic
- the conductive element mounting member BL is formed by firing a ceramic precursor (ceramic Darin sheet or the like) that forms the insulating member 2 to form a plate-like aggregate substrate 1 and then post-processing the aggregate substrate 1.
- a ceramic precursor ceramic Darin sheet or the like
- the light-emitting diode component LE2 divides the collective substrate 1 having a size including the plurality of insulating members 2 into a plurality of regions la, and forms through holes 11 at predetermined positions.
- the electrode layer 31 is formed on one side
- the electrode layer 32 is formed on the opposite side
- the conductive layer 33 is formed on the inner surface of the through hole 11, and the minimum hole portion 11a of the through hole 11 is filled with the volume of the conductive material 33a.
- each region la is cut out individually to form the semiconductor element mounting member BL. Manufactured at the same time.
- a surface light emitter is obtained.
- the light emitting diode component LE2 can also be used as the final form of the light emitting diode device. For example, it can be soldered to a desired position on a circuit board such as a printed circuit board or a liquid crystal backlight constituent member by a reflow method to function as a light emitting diode.
- the light-emitting diode component LE2 is mounted on the two electrode layers 72 provided on the bottom surface of the recess 7a of the package 7 of Fig. 14 by soldering via the solder layer SL1,
- the opening 7b of the recess 7a is sealed with a sealing cap or lens LS made of a material that can transmit light from the light emitting diode component LE2
- the light emitting diode LE3 can be obtained.
- a part of the melted solder is formed on the inner surface of the second tapered surface 11c in the through hole 11 and wraps around the conductive layer 33 exposed on the side surface 23 of the insulating member 2 to form the solder fillet SL2 Therefore, the mounting reliability is improved.
- the inner surface of the through hole 11 may be formed in a combination of the conical tapered shape of FIGS. 9 and 10 and the tapered shape of FIGS. 19 and 20. . That is, the inner surface of the through-hole 11 in the figure includes two first tapered surfaces l ib provided in two adjacent regions la serving as the semiconductor light emitting element mounting member BL, and the two regions la, respectively. 1 is provided across the region lb between the two first tapered surfaces l ib and the two minimum holes 11a provided in the two regions la. And a second tapered surface 11c.
- the two first tapered surfaces l ib each have an opening diameter from the main surface 21a side (the upper side in the figure) of the insulating member 2 to the two smallest holes 11a having a circular planar shape. Is formed in a conical taper shape so as to be gradually reduced, and is opened circularly at the main surface 21 in each region la.
- the second tapered surface 11c extends from the external connection surface 22 side (lower side in the figure) of the insulating member 2 to the two minimum hole portions 11a so that the planar shape thereof is at both ends of the rectangular central portion.
- Each of the two minimum holes 11a is formed in an oval shape connecting concentric semicircles, and is formed in a tapered shape so that the opening width of the oval defined above is gradually reduced.
- the external connection surface 22 is opened in an oval shape in a state of straddling two adjacent regions la and a region lb between them.
- the through hole 11 is also formed by a sandblast method.
- a sandblast method By using the sandblasting method, the shape of the region exposed on the one side of the collective substrate 1 corresponding to the opening of the through-hole 11 on the one surface side that becomes the external connection surface 22 without being protected by the resist film is made oval.
- the exposed region of the collective substrate 1 is selectively perforated in the thickness direction to form an oval second tapered surface 11c, and on the opposite side to the main surface 21, an opening of the through hole 11 is formed.
- the shape of the region exposed without being protected by the resist film is made circular, and the exposed region of the collective substrate 1 is selectively perforated in the thickness direction by the sandblasting method to form the second taper.
- the conductive layer 33 is formed on the inner surface of the through hole 11, the portion of the minimum hole 11a is filled by the deposition of the conductive material 33a forming the conductive layer 33, and the assembled substrate before cutting out
- the phosphor and Z or the protective resin FR can be prevented from leaking to the opposite side through the through hole 11.
- the region lb between the adjacent regions la is removed by dicing or the like and the region la is cut out as an individual insulating member, the inner surface of the second tapered surface 11c in the through hole 11 is removed.
- the conductive layer 33 formed is exposed at the side surface 23 of the insulating member 2, the conductive layer 33 can function as a solder fillet forming portion. It should be noted that the dimensions of each part of the through hole 11 and the dimensions of the other parts are preferably in the same range for the same reason as in the previous two examples.
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Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05766358A EP1775766A4 (en) | 2004-08-06 | 2005-07-21 | COLLECTIVE SUBSTRATE, MOUNTING MEMBER FOR A SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, ILLUMINATING DEVICE, ILLUMINATED DIODE COMPONENT AND LED LUMINAIRE |
JP2006531379A JP4012936B2 (ja) | 2004-08-06 | 2005-07-21 | 集合基板 |
US10/589,747 US7649270B2 (en) | 2004-08-06 | 2005-07-21 | Collective substrate, semiconductor element mount, semiconductor device, imaging device, light emitting diode component and light emitting diode |
CN200580008032.5A CN1930680B (zh) | 2004-08-06 | 2005-07-21 | 集合基板 |
CA2552908A CA2552908C (en) | 2004-08-06 | 2005-07-21 | Collective substrate, semiconductor element mount, semiconductor device, imaging device, light emitting diode component and light emitting diode |
US11/987,170 US7737562B2 (en) | 2004-08-06 | 2007-11-28 | Semiconductor element mount, semiconductor device, imaging device, light emitting diode component and light emitting diode |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2004231085 | 2004-08-06 | ||
JP2004-231085 | 2004-08-06 | ||
JP2005-047481 | 2005-02-23 | ||
JP2005047481 | 2005-02-23 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/987,170 Continuation US7737562B2 (en) | 2004-08-06 | 2007-11-28 | Semiconductor element mount, semiconductor device, imaging device, light emitting diode component and light emitting diode |
Publications (1)
Publication Number | Publication Date |
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WO2006013731A1 true WO2006013731A1 (ja) | 2006-02-09 |
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PCT/JP2005/013402 WO2006013731A1 (ja) | 2004-08-06 | 2005-07-21 | 集合基板、半導体素子搭載部材、半導体装置、撮像装置、発光ダイオード構成部材、および発光ダイオード |
Country Status (6)
Country | Link |
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US (2) | US7649270B2 (ja) |
EP (1) | EP1775766A4 (ja) |
JP (1) | JP4012936B2 (ja) |
KR (1) | KR100765945B1 (ja) |
CA (1) | CA2552908C (ja) |
WO (1) | WO2006013731A1 (ja) |
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JP2011071373A (ja) * | 2009-09-28 | 2011-04-07 | Kyocera Corp | 配線基板 |
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US20110278627A1 (en) * | 2006-12-21 | 2011-11-17 | Geun-Ho Kim | Light emitting device package and method for manufacturing the same |
US11264542B2 (en) | 2017-04-28 | 2022-03-01 | Nichia Corporation | Light-emitting device |
JP7521565B2 (ja) | 2022-09-30 | 2024-07-24 | Toppanホールディングス株式会社 | ガラス基板、多層配線基板、およびガラス基板の製造方法 |
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JP5279488B2 (ja) * | 2005-05-30 | 2013-09-04 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | ケーシング本体およびケーシング本体の製造方法 |
JP2007324417A (ja) * | 2006-06-01 | 2007-12-13 | Sharp Corp | 半導体発光装置とその製造方法 |
US20080035942A1 (en) * | 2006-08-08 | 2008-02-14 | Lg Electronics Inc. | Light emitting device package and method for manufacturing the same |
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US8742588B2 (en) * | 2008-10-15 | 2014-06-03 | ÅAC Microtec AB | Method for making via interconnection |
TW201114003A (en) * | 2008-12-11 | 2011-04-16 | Xintec Inc | Chip package structure and method for fabricating the same |
US8309973B2 (en) * | 2009-02-12 | 2012-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-based sub-mount for an opto-electronic device |
US20100237379A1 (en) * | 2009-03-19 | 2010-09-23 | Wu-Cheng Kuo | Light emitting device |
FR2943848B1 (fr) * | 2009-03-27 | 2012-02-03 | Jean Pierre Medina | Procede et machine de fabrication d'un semi-conducteur, du type cellule photovoltaique ou composant electronique similaire |
US8925192B2 (en) * | 2009-06-09 | 2015-01-06 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
US8187887B2 (en) | 2009-10-06 | 2012-05-29 | Massachusetts Institute Of Technology | Method and apparatus for determining radiation |
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KR20110094996A (ko) * | 2010-02-18 | 2011-08-24 | 엘지이노텍 주식회사 | 발광소자 패키지, 그 제조방법 및 조명시스템 |
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EP2637484B1 (en) * | 2010-11-02 | 2018-09-12 | Kyocera Corporation | Multi-part wired substrate, wired substrate, and electronic device |
CN102054914B (zh) * | 2010-11-09 | 2013-09-04 | 映瑞光电科技(上海)有限公司 | 发光二极管及其制造方法、发光装置 |
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CN102969432A (zh) * | 2012-10-25 | 2013-03-13 | 日月光半导体制造股份有限公司 | 发光二极管封装构造及其制造方法 |
EP3113586B1 (en) | 2014-02-26 | 2018-11-28 | NGK Insulators, Ltd. | Insulating substrate having through-holes |
JP6712050B2 (ja) * | 2016-06-21 | 2020-06-17 | 富士通株式会社 | 樹脂基板及びその製造方法、並びに回路基板及びその製造方法 |
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TWI610403B (zh) | 2017-03-03 | 2018-01-01 | 矽品精密工業股份有限公司 | 基板結構及其製法與電子封裝件 |
KR102019794B1 (ko) | 2017-06-29 | 2019-09-09 | 주식회사 디아이티 | 프로브 핀의 내구성 강화를 위한 스페이스 트랜스포머 및 그의 제조 방법 |
JP6629391B2 (ja) | 2018-06-27 | 2020-01-15 | 株式会社アドマップ | SiCコート |
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WO2020246812A1 (ko) * | 2019-06-04 | 2020-12-10 | 엘지이노텍 주식회사 | 인쇄회로기판 |
US11848243B2 (en) | 2021-03-05 | 2023-12-19 | Infineon Technologies Austria Ag | Molded semiconductor package having a substrate with bevelled edge |
CN118158926B (zh) * | 2024-05-11 | 2024-07-05 | 江苏普诺威电子股份有限公司 | 封装基板及其加工方法、半盲孔管脚单体及其加工方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07235621A (ja) * | 1994-02-22 | 1995-09-05 | Ibiden Co Ltd | リードレスチップキャリア及びその製造方法 |
JPH11238830A (ja) * | 1998-02-23 | 1999-08-31 | Hitachi Cable Ltd | 半導体パッケージ及びその製造方法 |
US20020050586A1 (en) | 2000-09-07 | 2002-05-02 | Murata Manufacturing Co., Ltd. | Electroconductive paste and method for manufacturing a multilayer ceramic electronic part using the same |
US20020056913A1 (en) | 1997-03-27 | 2002-05-16 | Takahisa Eimori | Semiconductor device and method of fabricating the same |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5875859A (ja) * | 1981-10-30 | 1983-05-07 | Fujitsu Ltd | 半導体装置 |
JP2922682B2 (ja) | 1991-09-27 | 1999-07-26 | 京セラ株式会社 | 固体撮像素子収納用パッケージ |
JP3127195B2 (ja) | 1994-12-06 | 2001-01-22 | シャープ株式会社 | 発光デバイスおよびその製造方法 |
CN1139117C (zh) * | 1995-03-20 | 2004-02-18 | 株式会社东芝 | 氮化硅电路板 |
JP3158018B2 (ja) | 1995-07-17 | 2001-04-23 | シャープ株式会社 | 横発光型ledおよびその製造方法 |
WO1998013862A1 (fr) * | 1996-09-24 | 1998-04-02 | Mitsubishi Denki Kabushiki Kaisha | Dispositif a semi-conducteur et son procede de fabrication |
JPH1174410A (ja) | 1997-08-28 | 1999-03-16 | Citizen Electron Co Ltd | 表面実装型チップ部品及びその製造方法 |
JP3518841B2 (ja) * | 1997-10-29 | 2004-04-12 | 株式会社トクヤマ | 基板およびその製造方法 |
CA2252113A1 (en) | 1997-10-29 | 1999-04-29 | Yoshihiko Numata | Substrate and process for producing the same |
US6114240A (en) * | 1997-12-18 | 2000-09-05 | Micron Technology, Inc. | Method for fabricating semiconductor components using focused laser beam |
JP3810204B2 (ja) * | 1998-03-19 | 2006-08-16 | 三菱電機株式会社 | 半導体装置の製造方法および半導体装置 |
US7205181B1 (en) * | 1998-03-20 | 2007-04-17 | Mcsp, Llc | Method of forming hermetic wafer scale integrated circuit structure |
JP3860336B2 (ja) * | 1998-04-28 | 2006-12-20 | 日本特殊陶業株式会社 | ガラスセラミック複合体 |
JP3501959B2 (ja) * | 1998-09-29 | 2004-03-02 | 三菱電機株式会社 | レーザー溶断方式半導体装置の製造方法および半導体装置 |
JP3769997B2 (ja) | 1999-09-22 | 2006-04-26 | セイコーエプソン株式会社 | マルチチップパッケージの製造方法 |
CN100392835C (zh) * | 1999-09-28 | 2008-06-04 | 松下电器产业株式会社 | 电子部件及其制造方法 |
US6452278B1 (en) * | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
JP4384339B2 (ja) | 2000-06-30 | 2009-12-16 | 日本特殊陶業株式会社 | 連結セラミック配線基板の製造方法、および配線基板の製造方法。 |
JP4737842B2 (ja) | 2001-01-30 | 2011-08-03 | 京セラ株式会社 | 発光素子収納用パッケージの製造方法 |
CN1200465C (zh) | 2001-10-24 | 2005-05-04 | 翰立光电股份有限公司 | 显示元件的封装结构及其形成方法 |
JP3769514B2 (ja) | 2002-03-20 | 2006-04-26 | 京セラ株式会社 | 配線基板 |
JP4038616B2 (ja) | 2002-12-26 | 2008-01-30 | 株式会社村田製作所 | 多層セラミック基板の製造方法 |
JP3876259B2 (ja) | 2004-08-04 | 2007-01-31 | 日本特殊陶業株式会社 | セラミック基板の製造方法 |
-
2005
- 2005-07-21 US US10/589,747 patent/US7649270B2/en active Active
- 2005-07-21 KR KR1020067015806A patent/KR100765945B1/ko not_active IP Right Cessation
- 2005-07-21 CA CA2552908A patent/CA2552908C/en not_active Expired - Fee Related
- 2005-07-21 EP EP05766358A patent/EP1775766A4/en not_active Withdrawn
- 2005-07-21 JP JP2006531379A patent/JP4012936B2/ja active Active
- 2005-07-21 WO PCT/JP2005/013402 patent/WO2006013731A1/ja active Application Filing
-
2007
- 2007-11-28 US US11/987,170 patent/US7737562B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07235621A (ja) * | 1994-02-22 | 1995-09-05 | Ibiden Co Ltd | リードレスチップキャリア及びその製造方法 |
US20020056913A1 (en) | 1997-03-27 | 2002-05-16 | Takahisa Eimori | Semiconductor device and method of fabricating the same |
JPH11238830A (ja) * | 1998-02-23 | 1999-08-31 | Hitachi Cable Ltd | 半導体パッケージ及びその製造方法 |
US20020050586A1 (en) | 2000-09-07 | 2002-05-02 | Murata Manufacturing Co., Ltd. | Electroconductive paste and method for manufacturing a multilayer ceramic electronic part using the same |
Non-Patent Citations (1)
Title |
---|
See also references of EP1775766A4 * |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007258514A (ja) * | 2006-03-24 | 2007-10-04 | Electroplating Eng Of Japan Co | Ledの製造方法 |
US20110278627A1 (en) * | 2006-12-21 | 2011-11-17 | Geun-Ho Kim | Light emitting device package and method for manufacturing the same |
US8546838B2 (en) * | 2006-12-21 | 2013-10-01 | Lg Electronics Inc. | Light emitting device package and method for manufacturing the same |
JP2011523502A (ja) * | 2008-04-29 | 2011-08-11 | ショット アクチエンゲゼルシャフト | 高出力led用のハウジング |
US8796709B2 (en) | 2008-04-29 | 2014-08-05 | Schott Ag | Housing for high-power LEDs |
JP2011071373A (ja) * | 2009-09-28 | 2011-04-07 | Kyocera Corp | 配線基板 |
US11264542B2 (en) | 2017-04-28 | 2022-03-01 | Nichia Corporation | Light-emitting device |
US11411144B2 (en) | 2017-04-28 | 2022-08-09 | Nichia Corporation | Light-emitting device |
US11652192B2 (en) | 2017-04-28 | 2023-05-16 | Nichia Corporation | Light-emitting device |
JP7521565B2 (ja) | 2022-09-30 | 2024-07-24 | Toppanホールディングス株式会社 | ガラス基板、多層配線基板、およびガラス基板の製造方法 |
Also Published As
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US20090001396A1 (en) | 2009-01-01 |
CA2552908A1 (en) | 2006-02-09 |
US20080203420A1 (en) | 2008-08-28 |
EP1775766A4 (en) | 2010-06-09 |
CA2552908C (en) | 2010-07-20 |
US7737562B2 (en) | 2010-06-15 |
EP1775766A1 (en) | 2007-04-18 |
KR100765945B1 (ko) | 2007-10-10 |
JPWO2006013731A1 (ja) | 2008-05-01 |
KR20060132684A (ko) | 2006-12-21 |
JP4012936B2 (ja) | 2007-11-28 |
US7649270B2 (en) | 2010-01-19 |
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