CN105684140B - 包括与过孔结合的精细间距背面金属再分布线的互连结构 - Google Patents

包括与过孔结合的精细间距背面金属再分布线的互连结构 Download PDF

Info

Publication number
CN105684140B
CN105684140B CN201380077033.XA CN201380077033A CN105684140B CN 105684140 B CN105684140 B CN 105684140B CN 201380077033 A CN201380077033 A CN 201380077033A CN 105684140 B CN105684140 B CN 105684140B
Authority
CN
China
Prior art keywords
rdl
via hole
layer
passivation layer
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201380077033.XA
Other languages
English (en)
Other versions
CN105684140A (zh
Inventor
K·J·李
J·Y·郑
H-K·张
J·缪尔海德
A·特朗
P·普瑞
J·姜
N·M·帕特尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN105684140A publication Critical patent/CN105684140A/zh
Application granted granted Critical
Publication of CN105684140B publication Critical patent/CN105684140B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0341—Manufacturing methods by blanket deposition of the material of the bonding area in liquid form
    • H01L2224/03424—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03823—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11823—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13583—Three-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13616—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13657—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本文描述了3D互连结构及其制造方法，其中，金属再分布层(RDL)与穿硅过孔(TSV)一起被集成，并采用了“穿过抗蚀剂镀覆”型工艺流程。氮化硅或碳化硅钝化层可被供于减薄器件晶片背面和RDL之间，从而在工艺流程期间提供密封阻隔和抛光停止层。

Description

包括与过孔结合的精细间距背面金属再分布线的互连结构
技术领域
本发明涉及三维(3D)封装，更具体而言，涉及将穿硅过孔(TSV)集成至3D封装之中。
背景
3D封装涉及片上系统(SOC)和系统级封装(SIP)配置。TSV 3D封装可包含两个或多个垂直堆叠的芯片，具有替代边缘引线的穿硅基板过孔，以在每个芯片上的电路元件之间创建电气连接。
诸如电子器件工程联合委员会(JEDEC)的JEDEC“外观设计注册，微型支柱格栅阵列(MPGA)”，DR-4.26A，2011年12月，11.2-845(R)项的标准为逻辑至存储器接口定义了芯片至芯片的焊盘接口。通常，TSV的物理位置直接位于芯片上焊盘位置的下方，这会占据大量的管芯面积。这就意味着所有其他电路都被安排在TSV位置的周围。
在TSV过程期间，TSV阵列通过减薄器件晶片来形成。传统的TSV结构在减薄器件晶片的背面上采用二氧化硅或聚合物作为绝缘材料。这些材料不是密闭的，且并不在减薄器件晶片的背面上提供耐用的钝化层。
附图说明
本发明实施例的特征和优点会从所附的权利要求、随后的一个或多个示例实施例的详细描述、及对应的附图开始变得明显，其中：
图1-17是根据发明实施例的采用“穿过抗蚀剂镀覆(plate through resist)”工艺来制造3D互连结构的方法的侧面剖视图示例。
图18是根据发明实施例实现TSV的3D封装的侧视图示例。
图19展示了根据发明实施例的系统。
详细说明
在不同的实施例中，描述了3D互连结构和制造3D互连结构的方法。然而，某些实施例可无需这些具体细节中的一个或多个项，或者与其他已知方法及材料相结合，而被实施。在随后的描述中，公开了许多具体细节，诸如具体材料和工艺等，以提供本发明的透彻理解。在另一个实例中，众所周知的封装过程和制造技术未被特别详细地描述，以免不必要地模糊本发明。纵观本说明书中所涉及的“实施例”或“一个实施例”是指包括于本技术的至少一个实施例中关于实施例所描述特定的特征、结构、材料或特性。这样，短语“在一个实施例中”或“在一实施例中”在贯穿本说明书中不同位置的出现不一定是指相同的发明实施例。另外，特定的特征、结构、材料或特性可以任何合适的方式被结合于一个或多个实施例中。
发明实施例描述了3D互连结构和工艺，其将TSV与非常精细间距的“穿过抗蚀剂镀覆”类型(在下文进行讨论)背面金属再分布层(RDL)进行结合。通过采用RDL(有时在本文中被称为RDL迹线)，该组合允许TSV的物理位置从芯片至芯片的焊盘位置脱离，这样提供了更多的电路布局灵活性。在这个方式下，多个迹线能够在相邻的焊盘行或列之间行进。例如，多个迹线可在以10μm-500μm间隔的相邻焊盘行或列之间行进。
本发明实施例允许了密封的3D互连结构和精细间距的RDL架构，并允许使用金属铜(与生产铝RDL迹线的削减刻蚀工艺相对)。
本发明实施例描述了氮化硅或碳化硅钝化层，这将背面RDL与减薄器件晶片的块状半导体(例如，硅)分离。氮化硅或碳化硅钝化层可提供密封阻隔，这在TSV和RDL工艺期间保护减薄器件晶片的背面免受迹线金属和水汽的污染。
另外，诸如氮化硅或碳化硅之类的背面钝化层材料可具有比诸如钽(Ta)、钛(Ti)、氮化钽(TaN)或氮化钛(TiN)之类的TSV阻隔层材料显著更低的移除率，从而使得钝化层允许大量的过抛光被纳入TSV阻隔层化学机械抛光(CMP)步骤，也不会导致非常大量的钝化层被移除。设计用于去除阻隔材料，诸如Ta、Ti、TaN、TiN的常见市售阻隔层CMP浆料也被设计用以去除氧化物，诸如二氧化硅。这样，在一些实施例中，在移除TSV之间的TSV阻隔层时，由氮化硅或碳化硅形成的钝化层可被用作抛光停止层，从而保护TSV结构的完整性。
实施例描述了与TSV结构一起集成穿过抗蚀剂镀覆RDL工艺的方式，其中，穿过抗蚀剂镀覆工艺可允许形成非常精细间距的背面RDL和更大的电路布局灵活性，而将密封阻隔钝化层集成至工艺序列之中，这可在TSV阻隔层从TSV之间移除期间充当CMP停止层，并提供更高的器件可靠性性能。采用穿过抗蚀剂镀覆工艺形成RDL，而非采用单或双镶嵌工艺，可减少或消除形成RDL所需CMP工艺的量。换言之，关于RDL的形成，特别是采用穿过抗蚀剂镀覆工艺形成RDL，可减少昂贵的Cu和阻隔层CMP工艺。例如，采用穿过抗蚀剂镀覆工艺形成RDL的顶面可无需采用用以形成RDL的CMP来完成。
虽然实施例参照硅器件晶片的TSV工艺进行描述，实施例也适用于除硅晶片以外的基板，诸如化合物III-V晶片或II-VI晶片。另外，需要理解的是，虽然描述并详细说明了“后过孔(via last)”TSV工艺(过孔制造于金属化结构之后)，本发明实施例并不被如此限制，并且本发明实施例也可兼容“过孔第一”TSV工艺(过孔制造于形成微电子器件之前)和“过孔中间”TSV工艺(过孔制造于形成微电子器件和金属化结构之间)。例如，穿过抗蚀剂镀覆RDL工艺也可被集成至过孔第一和过孔中间TSV工艺序列之中。
参照图17，在一实施例中，3D互连结构160包括具有正面102和背面104的半导体基板100、在正面102和背面104之间穿过半导体基板100的过孔(例如，TSV)142、以及形成于背面104之上的穿过抗蚀剂镀覆RDL 144。钝化层120可被置于背表面104和RDL 144之间，以防止水汽和迹线金属污染物进入半导体基板100。合适的钝化层材料可以是，例如碳化硅和氮化硅。
在一些实施例中，半导体基板100可以是包括多个所描述的3D互连结构的TSV处理器件晶片。另外，TSV处理器件晶片被单片化以形成多个半导体基板，其可被或可不被进一步处理以形成多个芯片，其可随后被集成至3D封装结构中。这样，在一实施例中，3D互连结构160是芯片。
在一实施例中，3D互连结构160包括以一系列行和列的方式布置于背表面104上的焊盘阵列。例如，阵列中的行和列可具有10μm至500μm的间距。诸如TSV 142之类的TSV阵列可被排布于背表面104下方，从而使得TSV阵列不被排布成与焊盘阵列相同的图案。在一实施例中，TSV阵列不直接在焊盘阵列的底下。在这样的实施例中，多个RDL，诸如RDL 144(本文中有时也被成为“RDL迹线”)，可在所述两行焊盘之间，在TSV阵列中将这两行之一连接至对应数量的TSV。例如，焊盘的两行可由10μm至500μm的间距隔开。以这样的方式，RDL允许了TSV和电路布局的物理位置中的灵活性。
参照图18，在一实施例中，3D封装包括基底基板170，诸如印刷电路板或层压基板。芯片堆叠被形成于基底基板上，其中，芯片堆叠包括形成的具有3D互连结构的芯片160。在一实施例中，芯片160是逻辑芯片，而一个或多个存储器芯片180被堆叠至逻辑芯片160上，其中逻辑芯片的焊盘阵列(在导电凸块阵列154底下)与存储器芯片180的对应焊盘阵列182耦合，尽管实施例并不被限制于此，且可包括各种芯片至芯片配置。
在一实施例中，过孔(例如，TSV)以后过孔工艺序列来形成。在这样的实施例中，在形成过孔之前，包含碳化硅或氮化硅的钝化层可被形成于器件晶片的背表面上。然后，过孔开口被形成于器件晶片之中，在器件晶片的背面和正面之间。绝缘衬垫层被形成于过孔开口的侧壁上。阻隔层被形成于过孔开口中，且在钝化层之上，然后，过孔的总容积可被填充以导电金属，诸如电镀的铜。举例而言，随后通过CMP从钝化层上方去除过孔开口之间的导电金属覆盖层和阻隔层。以此方式，钝化层不仅能作用以防止水汽和迹线金属污染物进入器件晶片，而且能用作抛光停止层，允许大量过抛光被纳入TSV阻隔层CMP步骤，而不会使极其大量的钝化层也被去除。
现参考图1-17，参照附图描述制造3D互连结构的方法。结合图1-17，还参照了图19的工艺1900。
倒转的器件晶片100被示于图1中，这可包括正面102和背面104。器件晶片100可具有各种构造。例如，器件晶片可以是块状半导体，包括覆盖于块状半导体的外延层，或包括绝缘体上半导体(SOI)结构，但也可采用其他结构。在特定的实施例中所示，器件晶片100包括SOI结构，该SOI结构包括覆盖于绝缘层114上的半导体层116，以及块状基板118。器件晶片100还可包括掺杂区域或其他掺杂特征以形成各种微电子器件，诸如金属-绝缘体-半导体场效应晶体管(MOSFET)、电容器、电感器、电阻器、二极管、微机电系统(MEMS)、其他适合的有源或无源器件，及其组合。
金属化结构112可被形成于器件晶片100的正面102之上。如所示，金属化结构112包括由导电金属(诸如铜、铝等)和层间介电材料(诸如二氧化硅、碳掺杂氧化物、氮化硅等)形成的多个互连层。钝化层113可被形成于金属化结构112的上层部分之上，以提供物理和化学保护。一个或多个导电焊盘108(例如，铜、铝等，可或可不形成为凸块)可设置在钝化层113中的开口之上。器件晶片100采用市售临时粘接剂208和设备被键合至临时载体晶片200(见方框1902)。随后可通过研磨、化学机械抛光(CMP)、等离子刻蚀和/或湿法刻蚀背面104以对器件晶片100进行背面减薄(见方框1904)。例如，在一实施例中，器件晶片100可被减薄背面至大约20-200μm(而其他实施例可包括20、50、100、150、200μm厚度等)。图1示出了减薄后的晶片100。
在减薄器件晶片100之后，钝化层120可被形成于背面104之上，以提供密封阻隔，如图2中所示(见方框1906)。适合的钝化层120材料包括，举例而言，碳化硅和氮化硅，因为这些材料可提供密封阻隔，这保护了减薄器件晶片100的背侧104免受迹线金属和水汽污染。在随后从TSV之间的钝化层120上CMP去除阻隔层材料的过程中，碳化硅和氮化硅还可具有比随后沉积的TSV阻隔层材料(诸如Ta或Ti)明显更低的去除率，如关于图8所描述的。可通过诸如化学气相沉积(CVD)之类的合适的方法来沉积钝化层120。钝化层120可替代地包括多个层，诸如氮化硅/氧化硅叠层或碳化硅/氧化硅叠层，其中氧化硅被形成于氮化硅或碳化硅之上，且可在下行过孔开口刻蚀过程中被用作硬掩模。
在图3中，光致抗蚀剂层被涂覆至减薄器件晶片上，曝光并显影(见方框1908，这称为“TSV”抗蚀剂，因为该抗蚀剂会被用以形成TSV)。在显影之后，在图案化光致抗蚀剂层122中需要过孔(例如TSV)的位置会存在开口。
在图4中，采用适合的方法，诸如等离子刻蚀，对过孔开口130(例如,TSV开口)进行刻蚀，穿过钝化层120，并穿过器件晶片100在背面104和正面102之间，停止于金属化结构112中的铜焊盘上。图案化的光致抗蚀剂层122随后被去除，而任何剩余的刻蚀聚合物或残留可被清除(见方框1910)。
在图5中，绝缘衬垫层136随后被沉积，以为过孔开口130的底部和侧壁以及钝化层120上过孔开口之间的区域提供衬垫(见方框1912)。绝缘衬垫层136适合的材料包括，但不仅限于，二氧化硅、氮化硅、碳化硅、及各种聚合物。这些材料可通过例如CVD、原子层沉积(ALD)、以及旋涂方法进行沉积。各向异性的等离子刻蚀工艺随后可被用以从过孔开口130的底部表面以及从钝化层120上过孔开口之间的区域去除绝缘衬垫层136，而保留过孔开口130的侧表面上绝缘衬垫层136的实际厚度(见方框1914)。在这样的实施例中，绝缘衬垫层136可被直接形成于由块状硅基板118界定的过孔开口130侧壁上。这样，绝缘衬垫层136在最终的3D互连结构中用以将TSV与周围的硅基板材料隔离。
在图6中，阻隔层和籽晶层138随后可被沉积至器件晶片表面上(见方框1916)。为简化说明，阻隔和籽晶层被示作一层，但实际上可通过首先形成阻隔层、随后在阻隔层上形成籽晶层而被形成。阻隔层138可包括，例如，钽、钛、或钴。籽晶层可以是，例如，铜(由被用于镀覆过孔的材料决定)。
在图7中，铜层140随后被电镀至器件晶片表面上，用铜完全填满TSV开口130(见方框1918)。随后通过CMP去除钝化层120之上的铜覆盖层和阻隔层，如图8中所示(见方框1920)。因此而产生的结构包括TSV 142，其穿过器件晶片100，在正面102和背面104之间延伸。在这样的配置中，单一金属填充140占据了TSV 142的总容积，可用阻隔层和籽晶层138(例如，为了电镀最终的RDL)以及绝缘衬垫层136进行衬垫。
在一实施例中，在第一CMP操作中用第一浆料去除铜140覆盖层，随后在第二CMP操作中用不同于第一浆料的第二浆料从钝化层120上去除阻隔层138。市售去除阻隔层138的CMP浆料被设计以刻蚀阻隔材料，诸如Ta、Ti、TaN和TiN，且通常也被设计以刻蚀氧化物。根据本发明的实施例，钝化层120可在去除阻隔层138期间用作抛光停止，这允许了阻隔层138CMP操作以包含大量过抛光，而不致使非常大量的钝化层120被去除。
在图9中，阻隔层171和籽晶层170随后可被沉积至器件晶片表面上(见方框1922，这称为“RDL”阻隔/籽晶，因为这些层会被用以形成RDL)。例如，阻隔层171可包括Ta、Ti、TaN、TiN。籽晶层170可以是，例如，铜。
在图10中，光致抗蚀剂材料被涂覆于籽晶层170上，然后被曝光和显影(见方框1924)。在显影抗蚀剂后，在抗蚀剂涂层中需要精细间距金属RDL线的地方存在开口(例如，开口134)，如图10中所示。
在图11中，铜层144随后被电镀至籽晶层170上，用铜填充开口134(见方框1926)并形成所需的精细间距金属RDL线。这样，抗蚀剂125中的开口124供于“穿过抗蚀剂镀覆”操作而非单或双镶嵌工艺。
在图12中，再分布光致抗蚀剂层被去除，而从晶片表面清除剩余的残留物(见方框1928)。因此而产生的RDL 144可包括焊盘，其中过孔142不直接在焊盘下方，而可以阻隔层和籽晶层138作为衬垫。这样，由于采用穿过抗蚀剂镀覆以在图1中产生RDL 144，不需要CMP步骤以去除Cu覆盖层(而在单和双镶嵌RDL构造技术或流程中是需要的)。这为生产过程节省了成本和时间。
在图13中，采用湿法或干法刻蚀工艺去除在精细间距再分布迹线(仅有其中之一被示出，且具有以下理解，额外的RDL迹线可被置于RDL 144剖视图的左侧、右侧、后面，或前面)之间的薄铜籽晶层170(见方框1930)。适合的湿法刻蚀剂包括氯化铁或硫酸/过氧化氢混合物。适合的干法刻蚀工艺包括氩溅射。采用湿法或干法刻蚀工艺去除在精细间距再分布迹线之间的薄钛阻隔171层(见方框1932)。
现参考图14，钝化层146被沉积于RDL 144上方(见方框1934，这称为“LMI”钝化，因为该钝化层会被用作创建逻辑芯片160和存储器芯片之间的逻辑-存储器接口(LMI)，由图17和18进行说明)。合适的材料包括但不仅限于氮化硅，其可提供密封阻隔，这保护其免受迹线金属和水汽污染，同时也保护了RDL 144避免氧化。在图15中，光致抗蚀剂材料随后被涂覆于钝化层146之上，曝光并显影以形成图案化光致抗蚀剂层148(见方框1936)。在显影抗蚀剂之后，在光致抗蚀剂层148中RDL 144将要终止于芯片至芯片连接所需的焊盘的位置处，存在开口150。在图16中，随后，采用适合的技术，诸如采用图案化光致抗蚀剂层148作为掩模版、停止于下方的RDL 144焊盘上的等离子刻蚀，穿过钝化层146来刻蚀开口(见方框1938)。
在图17中，光致抗蚀剂层148随后被去除，而任何剩余的刻蚀聚合物或残留可被清除(见方框1940)。导电凸块154被形成于每个暴露的RDL 144焊盘之上(见方框1944)。任何适合的技术可被实现以形成导电凸块154，诸如，但不仅限于，焊料凸起、采用图案化工艺的电镀，以及化学镀。
在图17中所示的特定实施例中，用焊料兼容的表面抛光155涂覆暴露的RDL 144焊盘(即，位于钝化层间隙之间的区域，其允许接触RDL线的顶面)。导电凸块154的示例表面抛光包括化学镀CoP/浸金、化学镀CoWP/浸金、化学镀NiP/浸金、化学镀NiP/化学镀Pd/浸金、化学镀Sn、化学镀NiP/化学镀Sn、化学镀CoP/化学镀Sn、化学镀CoWP/化学镀Sn、化学镀Cu/化学镀CoP/浸金、化学镀Cu/化学镀CoWP/浸金、化学镀Cu/化学镀NiP/浸金、化学镀Cu/化学镀NiP化学镀Pd/浸金、化学镀Cu/化学镀Sn、化学镀Cu/化学镀NiP/化学镀Sn、化学镀Cu/化学镀CoP/浸金、化学镀Cu/化学镀CoWP/化学镀Sn。其他表面抛光也可适用，取决于所运用的芯片至芯片焊接材料和/或芯片至芯片附着方法。在另一实施例中，导电凸块154可以是C4或由诸如PbSn、Sn、SnAg、Cu、In、SnAgCu、SnCu、Au等材料形成的倒装芯片凸块。
然后，载体晶片200和粘合剂208可采用市售晶片剥离设备和工艺从器件晶片100移除(见方框1946)。一旦载体晶片200和粘合剂208被移除，图17中所示产生的多个3D互连结构160可被单片化，然后可或可不被进一步处理以形成芯片，其随后可被集成至3D封装结构中。
尽管所描述的发明实施例中，TSV阵列不直接在焊盘阵列和/或导电凸块下方，需要理解的是，一些TSV可直接在焊盘阵列和/或导电凸块下方。本发明实施例通过集成穿过抗蚀剂镀覆工艺而为TSV的位置提供了灵活性。因此，TSV阵列的位置不需要直接在TSV所连接的对应焊盘阵列或导电凸块的下方。
为了进一步说明本发明实施例的能力，以允许电路设计灵活性，在一个示例中，焊盘阵列可具有50μm的垂直间距和40μm的水平间距，而焊盘(诸如图17中所示RDL 144的部分)具有20μm的直径。在一特定示例中，这在两行焊盘之间留下了30μm来走六条RDL。假设，六条RDL线宽和临近及RDL之间的七个间隔是相同的，则每一RDL可具有2.3μm线宽(然而，其他实施例可包括2、3、4、5、6、7、8μm或更大线宽)。根据本发明实施例的穿过抗蚀剂镀覆类型工艺可尤其适合实现这样的示例性精细间距RDL架构，尽管实施例并不被如此限制，且还可被用于任意间距的RDL架构。
现参考图20，所示是一种根据本发明实施例的系统实施例1000的框图。所示是一多处理器系统1000，包括第一处理单元1070和第二处理单元1080。尽管两个处理单元1070和1080被示出，需要理解的是，系统1000的实施例还可仅包括一个这样的处理单元。系统1000被示作点对点互连系统，其中第一处理单元1070和第二处理单元1080通过点对点互连1050进行耦合。应当理解的是，任意或所有所示的互连可作为多点总线而非点对点互连来实现。如所示，每个处理单元1070和1080可以是多核处理器，包括第一和第二处理器核(即，处理器核1074a和1074b以及处理器核1084a和1084b)。这样的核1074a、1074b、1084a、1084b可被配置以类似本文中所讨论方法的方式来执行指令代码。
每个处理单元1070、1080可包括至少一个共享缓存。共享缓存可储存由一个或多个处理器元件，诸如核1074a、1074b和1084a、1084b各自所使用的数据(例如，指令)例如，为使处理器元件更快地访问，共享缓存可在本地缓存储存在存储器1032、1034中的数据。在一个或多个实施例中，共享缓存可包括一个或多个中间级缓存，诸如2级(L2)、3级(L3)、4级(L4)、或其他等级缓存、末级缓存(LLC)，和/或其组合。
尽管仅用两个处理单元1070、1080示出，需要理解的是，本发明的范围并不如此限制。在其他实施例中，一个或多个额外的处理单元可存在于指定的处理器中。另外，一个或多个处理单元1070、1080可以是一个单元而非处理器，诸如加速器或现场可编程门阵列。例如，额外的处理单元可包括与第一处理器1070相同的额外的处理器、与第一处理器1070异构或不对称的额外的处理器、加速器(诸如，举例而言，图形加速器或数字信号处理(DSP)单元)、现场可编程门阵列，或任何其他处理单元。处理单元1070、1080之间，在一系列优点衡量，包括架构、微架构、热、功耗特性等方面可以存在各种区别。这些区别可有效地将其自身在处理单元1070、1080中表现为对称和异构。对于至少一个实施例，不同的处理单元1070、1080可位于相同的管芯封装中。
第一处理单元1070还可包括存储器控制器逻辑(MC)1072和点对点(P-P)接口1076和1078。类似的，第二处理单元1080可包括MC 1082和P-P接口1086和1088。MC 1072和1082将处理器耦合至各自的存储器，也就是存储器1032和存储器1034，其可以是在本地附于各自处理器的主存储器的部分。尽管MC逻辑1072和1082被示作集成至处理单元1070、1080，而对于替代实施例，MC逻辑可以是处理单元1070、1080外部而非集成于其中的分立逻辑。
第一处理单元1070和第二处理单元1080可通过P-P接口1076、1086通过P-P互连1062、10104分别被耦合至I/O子系统1090。如所示，I/O子系统1090包括P-P接口1094和1098。另外，I/O子系统1090包括将I/O子系统1090与高性能图形引擎1038耦合的接口1092。在一实施例中，总线可被用以将图形引擎1038耦合至I/O子系统1090。另外，点对点互连1039可耦合这些元件。
反过来，I/O子系统1090可通过接口1096被耦合至第一总线10110。在一实施例中，尽管本发明的范围并不如此限制，但第一总线10110可以是外部设备互连(PCI)总线，或诸如PCI快速总线或另一第三代I/O互连总线的总线。
如所示，不同的I/O设备1014、1024可连同可将第一总线10110耦合至第二总线1020的总线桥一起被耦合至第一总线10110。在一实施例中，第二总线1020可以是低管脚数(LPC)总线。在一实施例中，不同的设备可被耦合至第二总线1020，包括，举例而言，键盘/鼠标1022、通信设备1026(其可依次与计算机网络通信)，以及数据储存单元1028，诸如硬盘驱动或其他大容量存储设备，其可包括代码1030。代码1030可包括执行一个或多个上述方法的实施例的指令。另外，音频I/O 1024可被耦合至第二总线1020。
注意，其他实施例是可被考虑的。例如，取代所示点对点架构，相同可实现多点总线或另一个这样的通信拓扑结构。另外，图中的元素可采用比图中所示更多或更少的集成芯片可替代地被划分。
示于系统300中的一个或多个元件可被包括于和/或可包括一个或多个集成电路半导体封装，诸如图17的芯片160或图18的3D封装。例如，元件1070、1080、1032、1034、1038、1090或这些元件的组合可被包括于集成电路封装中，包括在不同实施例中所描述的至少一个互连结构实施例。
示例1包括一互连装置，包括：半导体基板，该半导体基板具有正面和背面；过孔，该过孔从正面延伸至背面；再分布层(RDL)，该再分布层形成于背面和过孔之上；以及第一钝化层，该第一钝化层直接接触RDL的一个表面。
RDL可组成焊盘，而这可构成扩展RDL线(也被称为RDL)的部分，等等。RDL可不直接与基板的背面接触。虽然一些实施例的RDL包括Cu或Au，另一些实施例并不如此限制，而可包括其他金属和/或未具体提及的合金。当一元件“直接接触”另一元件时，尽管在这两个元件之间(例如，在钝化层和RDL之间)存在某种程度的氧化或污染，该接触仍然存在。这也适用于本文中涉及“直接接触”的其他地方。另外，籽晶层可包括与RDL线相同的材料，即使是以不同于RDL线的方式来操作(例如，籽晶层可以是用于RDL线的合金，反之亦然，籽晶层可包括与RDL线不同的材料配比(即使是相同的材料)，等等)。有时，在本文中RDL线可被称为RDL层(反之亦然)。然而，这么做仅仅只是意味着许多RDL线是由单一层次形成的。RDL层，在被图案化之后，可包括许多RDL线。
在示例2中，示例1的主题可选择性地包括，其中第一钝化层直接接触RDL的顶面。
在示例3中，示例1-2的主题可选择性地包括第二钝化层，该第二钝化层被置于(a)背面和RDL之间，以及(b)在第一钝化层下。
在示例4中，示例1-3的主题可选择性地包括，其中第一钝化层包括碳化硅和氮化硅中的至少一项，而第二钝化层包括碳化硅和氮化硅中的至少一项。
在示例5中，示例1-4的主题可选择性地包括，其中过孔还包括：绝缘衬垫层，所述绝缘衬垫层直接接触所述过孔的侧表面；阻隔层，所述阻隔层在所述过孔中，并直接接触所述绝缘衬垫；以及导电金属，所述导电金属充填所述过孔。
在示例6中，示例1-5的主题可选择性地包括，阻隔层，所述阻隔层在所述RDL和所述过孔之间；以及籽晶层，所述籽晶层在所述阻隔层和所述RDL之间，所述籽晶层和所述RDL包括导电材料；其中，所述阻隔层和籽晶层与所述过孔垂直对准。
在示例7中，示例1-6的主题可选择性地包括，焊盘阵列，所述焊盘阵列以一系列行和列的方式被排布在所述背面之上；穿硅过孔(TSV)，包括所述过孔的阵列，所述阵列被排布在所述背面之下，从而使得所述TSV阵列不是直接在所述焊盘阵列下方；以及多个RDL，所述多个RDL在所述焊盘的两行之间，将所述两行之一连接至所述TSV阵列中对应数量的TSV。
在示例8中，示例1-7的主题可选择性地包括，其中两行焊盘被10μm至500μm的间距分隔。
在示例9中，示例1-8的主题可选择性地包括，其中RDL包括具有两个RDL侧壁以及RDL线宽的图案化RDL线，RDL线宽小于5微米，与两个RDL侧壁正交，并在其之间伸展。在其他实施例中，宽度可以是2、3、4、6、7、8或更多微米。
在示例10中，示例1-9的主题可选择性地包括表面抛光层(a)在所述RDL的接触焊盘部分上垂直对准，以及(b)垂直偏离所述过孔。表面抛光层可被形成于凸块上，该凸块直接或间接接触RDL的焊盘或接触焊盘部分。
在示例11中，示例1-10的主题可选择性地包括，其中第一和第二钝化层牢牢地封闭基板。
在示例12中，示例1-11的主题可选择性地包括，其中第一钝化层与过孔垂直对准。通过“垂直对准”纵轴，以过孔为中心在过孔顶、底之间延伸，贯穿第一钝化层的部分。
示例13包括一半导体封装，包括：基底基板；以及芯片堆叠，所述芯片堆叠形成于所述基底基板之上；其中所述芯片堆叠包括芯片，其包括：半导体基板，该半导体基板具有正面和背面；过孔，该过孔从正面延伸至背面；再分布层(RDL)，该再分布层形成于背面和过孔之上；以及第一钝化层，该第一钝化层直接接触RDL的侧表面。
在示例14中，示例13的主题可选择性地包括，其中芯片是逻辑芯片。
在示例15中，示例13-14的主题可选择性地包括，其中逻辑芯片还包括：焊盘阵列，所述焊盘阵列以一系列行和列的方式被排布在所述背面之上；穿硅过孔(TSV)阵列，所述阵列被排布在所述背面之下，从而使得所述TSV阵列不是直接在所述焊盘阵列底下；以及多个RDL，所述多个RDL在所述两行焊盘之间，将所述两行之一连接至所述TSV阵列中对应数量的TSV。
在示例16中，示例13-15的主题可选择性地包括，其中焊盘阵列与存储器芯片的对应焊盘阵列耦合。
示例17包括形成互连结构的方法，包括：提供半导体基板，所述半导体基板具有正面和背面；形成过孔，所述过孔从正面延伸至背面；形成再分布层(RDL)，所述再分布层形成于背面和所述过孔之上；以及形成第一钝化层，所述第一钝化层直接接触所述RDL的侧表面。
在示例18中，示例17的主题可选择性地包括采用穿过抗蚀剂镀覆工艺形成RDL。
在示例19中，示例17-18的主题可选择性地包括不利用单或双镶嵌工艺而形成RDL。
在示例20中，示例17-19的主题可选择性地包括不利用化学机械抛光(CMP)而形成RDL的顶面。
本发明实施例的以上描述是以说明和描述的目的给出。这并不旨在穷举或将本发明限制于所公开的准确形式。该描述和以上权利要求，包括术语，诸如左、右、顶、底、上方、下方、上层、下层、第一、第二等仅用于描述性的目的，而不应被视为限制。例如，标明相对垂直位置的术语是指以下情况，其中基板或继承电路的器件侧(或有源表面)是该基板的“顶部”表面；基板实际上可以是任意方向的，因此在标准大地参考系中，基板的“顶部”侧可低于“底部”侧，而仍然落入术语“顶部”的含义之中。如本文所使用的术语“在……上”(包括在权利要求中)，除非特别声明，否则第一层次“在”第二层次“上”并不表明是直接“在其之上”并与第二层次直接接触；在第一层次和在第一层次上的第二层次之间可以有第三层次或其他结构。本文所描述的器件或项的实施例能以多个位置和方向被制造、使用或运输。相关领域的技术人员可以理解，根据以上的教导，许多修改和变化是可能的。本领域的技术人员会辨识出图中所示不同元件的各种等效组合和替代。因此，本发明的范围不是由此详细说明，而是由为此所附的权利要求所限制。
虽然本发明关于有限数量的实施例被描述，本领域的技术人员会理解从中的许多修改和变化。其意图在于，所附权利要求覆盖落入本发明真实精神和范围内的所有这样的修改和变化。

Claims (18)

1.一种互连装置，包括：
半导体基板，所述半导体基板具有正面和背面；
过孔，所述过孔从正面延伸至背面；
再分布层RDL，所述再分布层形成于背面和所述过孔之上；
第一钝化层，所述第一钝化层直接接触所述RDL的侧表面；
第二钝化层，所述第二钝化层被置于所述背面和所述RDL之间；
阻隔层，所述阻隔层在所述RDL和所述过孔之间；以及
籽晶层，所述籽晶层在所述阻隔层和所述RDL之间，所述籽晶层和所述RDL包括导电材料；
其中，所述阻隔层和籽晶层与所述过孔垂直对准并且在所述过孔与所述RDL之间，使得垂直轴与所述RDL、所述过孔、所述阻隔层以及所述籽晶层相交，
其中所述过孔还包括：
绝缘衬垫层，所述绝缘衬垫层直接接触所述过孔的侧表面；
第二阻隔层，所述阻隔层在所述过孔中，并直接接触所述绝缘衬垫；以及
导电金属，所述导电金属充填所述过孔。
2.如权利要求1所述的装置，其特征在于，所述第一钝化层直接接触所述RDL的顶面。
3.如权利要求2所述的装置，其特征在于，所述第二钝化层在所述第一钝化层下。
4.如权利要求3所述的装置，其特征在于，所述第一钝化层包括碳化硅和氮化硅中的至少一项，而所述第二钝化层包括碳化硅和氮化硅中的至少一项。
5.如权利要求3所述的装置，还包括：
焊盘阵列，所述焊盘阵列以一系列行和列的方式被排布在所述背面之上；
包括所述过孔的穿硅过孔TSV的阵列，所述阵列被排布在所述背面之下，从而使得所述TSV阵列不是直接在所述焊盘阵列底下；以及
多个RDL，所述多个RDL在所述焊盘的两行之间，将所述两行中的一行连接至所述TSV阵列中的对应数量的TSV。
6.如权利要求5所述的装置，其特征在于，所述焊盘的两行由10μm至500μm的间距隔开，并且彼此相邻，在所述两行之间没有其他焊盘行。
7.如权利要求2所述的装置，其特征在于，所述RDL包括具有两个RDL侧壁以及RDL线宽的图案化RDL线，所述RDL线宽小于5微米、与所述两个RDL侧壁正交、并在所述两个RDL侧壁之间伸展。
8.如权利要求2所述的装置，包括表面抛光层，所述表面抛光层a在所述RDL的接触焊盘部分上垂直对准并且b垂直偏离所述过孔。
9.如权利要求2所述的装置，其特征在于，所述第一和第二钝化层牢牢地封闭所述基板。
10.如权利要求1所述的装置，其特征在于，所述第一钝化层与所述过孔垂直对准，使得所述垂直轴与所述第一钝化层和所述过孔相交。
11.一种半导体封装，包括：
基底基板；以及
芯片堆叠，所述芯片堆叠形成于所述基底基板之上；
其中所述芯片堆叠包括芯片，其包括：
半导体基板，所述半导体基板具有正面和背面；
过孔，所述过孔从正面延伸至背面；
再分布层RDL，所述再分布层形成于背面和所述过孔之上；
第一钝化层，所述第一钝化层直接接触所述RDL的侧表面；
第二钝化层，所述第二钝化层被置于所述背面和所述RDL之间；
阻隔层，所述阻隔层在所述RDL和所述过孔之间；以及
籽晶层，所述籽晶层在所述阻隔层和所述RDL之间，所述籽晶层和所述RDL包括导电材料；
其中，所述阻隔层和籽晶层与所述过孔垂直对准并且在所述过孔与所述RDL之间，使得垂直轴与所述RDL、所述过孔、所述阻隔层以及所述籽晶层相交，
其中所述过孔还包括：
绝缘衬垫层，所述绝缘衬垫层直接接触所述过孔的侧表面；
第二阻隔层，所述阻隔层在所述过孔中，并直接接触所述绝缘衬垫；以及
导电金属，所述导电金属充填所述过孔。
12.如权利要求11所述的封装，其特征在于，所述芯片是逻辑芯片。
13.如权利要求12所述的封装，其特征在于，所述逻辑芯片还包括：
焊盘阵列，所述焊盘阵列以一系列行和列的方式被排布在所述背面之上；
穿硅过孔TSV阵列，所述阵列被排布在所述背面之下，从而使得所述TSV阵列不是直接在所述焊盘阵列底下；以及
多个RDL，所述多个RDL在所述焊盘的两行之间，将所述两行中的一行连接至所述TSV阵列中的对应数量的TSV。
14.如权利要求13所述的封装，其特征在于，所述焊盘阵列与存储器芯片的对应焊盘阵列耦合。
15.一种形成互连结构的方法，包括：
提供半导体基板，所述半导体基板具有正面和背面；
形成过孔，所述过孔从正面延伸至背面；
形成再分布层RDL，所述再分布层形成于背面和所述过孔之上；
形成第一钝化层，所述第一钝化层直接接触所述RDL的侧表面；
形成第二钝化层，所述第二钝化层被置于所述背面和所述RDL之间；
形成阻隔层，所述阻隔层在所述RDL和所述过孔之间；以及
形成籽晶层，所述籽晶层在所述阻隔层和所述RDL之间，所述籽晶层和所述RDL包括导电材料；
其中，所述阻隔层和籽晶层与所述过孔垂直对准并且在所述过孔与所述RDL之间，使得垂直轴与所述RDL、所述过孔、所述阻隔层以及所述籽晶层相交，
其中形成所述过孔还包括：
形成绝缘衬垫层，所述绝缘衬垫层直接接触所述过孔的侧表面；
形成第二阻隔层，所述阻隔层在所述过孔中，并直接接触所述绝缘衬垫；以及
形成导电金属，所述导电金属充填所述过孔。
16.如权利要求15所述的方法，其特征在于，包括采用穿过抗蚀剂镀覆工艺形成所述RDL。
17.如权利要求15所述的方法，其特征在于，还包括不利用单或双镶嵌工艺而形成所述RDL。
18.如权利要求15所述的方法，其特征在于，还包括不利用化学机械抛光CMP而形成所述RDL的顶面。
CN201380077033.XA 2013-06-29 2013-06-29 包括与过孔结合的精细间距背面金属再分布线的互连结构 Active CN105684140B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2013/048792 WO2014209404A1 (en) 2013-06-29 2013-06-29 Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

Publications (2)

Publication Number Publication Date
CN105684140A CN105684140A (zh) 2016-06-15
CN105684140B true CN105684140B (zh) 2019-11-05

Family

ID=52142524

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380077033.XA Active CN105684140B (zh) 2013-06-29 2013-06-29 包括与过孔结合的精细间距背面金属再分布线的互连结构

Country Status (6)

Country Link
US (1) US9716066B2 (zh)
KR (1) KR102101377B1 (zh)
CN (1) CN105684140B (zh)
DE (1) DE112013007038T5 (zh)
GB (1) GB2530671A (zh)
WO (1) WO2014209404A1 (zh)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9443796B2 (en) * 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
CN103730379A (zh) * 2014-01-16 2014-04-16 苏州晶方半导体科技股份有限公司 芯片封装方法及结构
EP3178162A4 (en) 2014-08-07 2018-04-04 Intel Corporation Method and apparatus for forming backside die planar devices and saw filter
TWI566354B (zh) * 2014-08-13 2017-01-11 矽品精密工業股份有限公司 中介板及其製法
US20160284626A1 (en) 2015-03-25 2016-09-29 Micron Technology, Inc. Semiconductor devices having conductive vias and methods of forming the same
US9728498B2 (en) * 2015-06-30 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure
US10147682B2 (en) * 2015-11-30 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for stacked logic performance improvement
US10418311B2 (en) * 2017-03-28 2019-09-17 Micron Technology, Inc. Method of forming vias using silicon on insulator substrate
CN110730631B (zh) * 2017-04-19 2023-02-21 传感技术股份有限公司 对分析物指示剂变化的检测和修正
KR102432627B1 (ko) 2018-01-11 2022-08-17 삼성전자주식회사 반도체 패키지
TWI741367B (zh) * 2018-09-14 2021-10-01 美商應用材料股份有限公司 用於3d互連件的同時金屬圖案化
US10707151B2 (en) * 2018-11-20 2020-07-07 Nanya Technology Corporation Through silicon via structure and method for manufacturing the same
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
US11139262B2 (en) * 2019-02-07 2021-10-05 Micron Technology, Inc. Use of pre-channeled materials for anisotropic conductors
KR102431331B1 (ko) * 2019-04-04 2022-08-11 주식회사 네패스 반도체 패키지 및 그 제조 방법
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
KR20210017663A (ko) 2019-08-09 2021-02-17 삼성전자주식회사 두꺼운 금속층 및 범프를 갖는 반도체 소자들
CN110572593B (zh) * 2019-08-19 2022-03-04 上海集成电路研发中心有限公司 一种3d堆叠式图像传感器
US11195818B2 (en) * 2019-09-12 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside contact for thermal displacement in a multi-wafer stacked integrated circuit
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11309246B2 (en) 2020-02-05 2022-04-19 Apple Inc. High density 3D interconnect configuration
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
DE102020124131A1 (de) * 2020-03-26 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und verfahren
KR20210120532A (ko) 2020-03-27 2021-10-07 삼성전자주식회사 반도체 패키지
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US20210375816A1 (en) * 2020-06-02 2021-12-02 Texas Instruments Incorporated Ic device with chip to package interconnects from a copper metal interconnect level
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1755916A (zh) * 2004-09-29 2006-04-05 三洋电机株式会社 半导体装置及其制造方法
CN101719484A (zh) * 2008-10-09 2010-06-02 台湾积体电路制造股份有限公司 具有再分布线的tsv的背连接

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4130158B2 (ja) * 2003-06-09 2008-08-06 三洋電機株式会社 半導体装置の製造方法、半導体装置
KR20080101635A (ko) * 2007-05-18 2008-11-21 삼성전자주식회사 반도체 패키지, 그 제조 방법, 및 반도체 패키지를 이용한패키지 모듈 및 전자 제품
KR101483273B1 (ko) * 2008-09-29 2015-01-16 삼성전자주식회사 구리 패드와 패드 장벽층을 포함하는 반도체 소자와 그의 배선 구조 및 그 제조 방법들
US8759949B2 (en) 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
WO2013062590A1 (en) 2011-10-28 2013-05-02 Intel Corporation 3d interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
US9449913B2 (en) 2011-10-28 2016-09-20 Intel Corporation 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
KR101906860B1 (ko) * 2011-11-24 2018-10-12 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법
US9112007B2 (en) * 2012-09-14 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Through via structure and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1755916A (zh) * 2004-09-29 2006-04-05 三洋电机株式会社 半导体装置及其制造方法
CN101719484A (zh) * 2008-10-09 2010-06-02 台湾积体电路制造股份有限公司 具有再分布线的tsv的背连接

Also Published As

Publication number Publication date
KR20160051688A (ko) 2016-05-11
GB201518443D0 (en) 2015-12-02
CN105684140A (zh) 2016-06-15
DE112013007038T5 (de) 2016-01-28
GB2530671A (en) 2016-03-30
KR102101377B1 (ko) 2020-04-16
US9716066B2 (en) 2017-07-25
WO2014209404A1 (en) 2014-12-31
US20160049371A1 (en) 2016-02-18

Similar Documents

Publication Publication Date Title
CN105684140B (zh) 包括与过孔结合的精细间距背面金属再分布线的互连结构
US10854567B2 (en) 3D packages and methods for forming the same
US11830745B2 (en) 3D packages and methods for forming the same
CN103890939B (zh) 包括与穿硅过孔组合的细间距单镶嵌后侧金属再分布线的3d互连结构
US8994188B2 (en) Interconnect structures for substrate
CN105336578B (zh) 具有通孔的堆叠结构上的缓冲层
CN106409810B (zh) 具有堆叠通孔的再分布线
TWI591736B (zh) 積體電路封裝接墊及其形成方法
TWI550808B (zh) 3d互連結構、3d封裝體及形成一雙鑲嵌3d互連結構之方法
CN104051379B (zh) 具有超薄介电层的无焊内建层（bbul）半导体封装
US9633929B2 (en) TSV formation
TW201715674A (zh) 半導體元件的形成方法
JP2012253392A (ja) モールド再構成ウェハーを利用したスタックパッケージ及びその製造方法
JP2020074436A (ja) アンダーバンプメタル構造体用のカラー並びにそれに関連するシステム及び方法
US11699638B2 (en) Package and manufacturing method thereof
US11769731B2 (en) Architecture for computing system package
TWI543263B (zh) 半導體裝置及其製造方法
US11315802B2 (en) Method for manufacturing semiconductor package having redistribution layer
KR102320821B1 (ko) 반도체 패키지
CN103367139A (zh) 一种tsv孔底部介质层刻蚀方法
US20240038631A1 (en) Three-dimensional integrated circuit module and fabrication method therefor
CN108470722A (zh) 半导体结构及其形成方法
CN105405822A (zh) 晶圆级tsv封装结构及封装工艺
TW202147435A (zh) 半導體裝置及其製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant